PDK API Guide for J721E
cslr_dss.h
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1 /********************************************************************
2  * Copyright (C) 2018-2019 Texas Instruments Incorporated.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
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9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  * Name : cslr_dss.h
33 */
34 #ifndef CSLR_DSS_H_
35 #define CSLR_DSS_H_
36 
37 #ifdef __cplusplus
38 extern "C"
39 {
40 #endif
41 #include <ti/csl/cslr.h>
42 #include <stdint.h>
43 
44 /**************************************************************************
45 * Hardware Region : COMMON_M Registers
46 **************************************************************************/
47 
48 
49 /**************************************************************************
50 * Register Overlay Structure
51 **************************************************************************/
52 
53 typedef struct {
54  volatile uint8_t Resv_4[4];
55  volatile uint32_t DSS_REVISION; /* DSS_REVISION */
56  volatile uint32_t DSS_SYSCONFIG; /* DSS_SYSCONFIG */
57  volatile uint8_t Resv_32[20];
58  volatile uint32_t DSS_SYSSTATUS; /* DSS_SYSSTATUS */
59  volatile uint8_t Resv_40[4];
60  volatile uint32_t DISPC_IRQSTATUS_RAW; /* DISPC_IRQSTATUS_RAW */
61  volatile uint32_t DISPC_IRQSTATUS; /* DISPC_IRQSTATUS */
62  volatile uint32_t DISPC_IRQENABLE_SET; /* DISPC_IRQENABLE_SET */
63  volatile uint32_t DISPC_IRQENABLE_CLR; /* DISPC_IRQENABLE_CLR */
64  volatile uint32_t VID_IRQENABLE_0; /* VID_IRQENABLE_0 */
65  volatile uint32_t VID_IRQENABLE_1; /* VID_IRQENABLE_1 */
66  volatile uint32_t VID_IRQENABLE_2; /* VID_IRQENABLE_2 */
67  volatile uint32_t VID_IRQENABLE_3; /* VID_IRQENABLE_3 */
68  volatile uint32_t VID_IRQSTATUS_0; /* VID_IRQSTATUS_0 */
69  volatile uint32_t VID_IRQSTATUS_1; /* VID_IRQSTATUS_1 */
70  volatile uint32_t VID_IRQSTATUS_2; /* VID_IRQSTATUS_2 */
71  volatile uint32_t VID_IRQSTATUS_3; /* VID_IRQSTATUS_3 */
72  volatile uint32_t VP_IRQENABLE_0; /* VP_IRQENABLE_0 */
73  volatile uint32_t VP_IRQENABLE_1; /* VP_IRQENABLE_1 */
74  volatile uint32_t VP_IRQENABLE_2; /* VP_IRQENABLE_2 */
75  volatile uint32_t VP_IRQENABLE_3; /* VP_IRQENABLE_3 */
76  volatile uint32_t VP_IRQSTATUS_0; /* VP_IRQSTATUS_0 */
77  volatile uint32_t VP_IRQSTATUS_1; /* VP_IRQSTATUS_1 */
78  volatile uint32_t VP_IRQSTATUS_2; /* VP_IRQSTATUS_2 */
79  volatile uint32_t VP_IRQSTATUS_3; /* VP_IRQSTATUS_3 */
80  volatile uint32_t WB_IRQENABLE; /* WB_IRQENABLE */
81  volatile uint32_t WB_IRQSTATUS; /* WB_IRQSTATUS */
82  volatile uint32_t DISPC_IRQ_EOI_FUNC; /* DISPC_IRQ_EOI_FUNC */
83  volatile uint32_t DISPC_IRQ_EOI_SAFETY; /* DISPC_IRQ_EOI_SAFETY */
84  volatile uint32_t DISPC_IRQ_EOI_SECURITY; /* DISPC_IRQ_EOI_SECURITY */
85  volatile uint8_t Resv_144[4];
86  volatile uint32_t DISPC_SECURE_DISABLE; /* DISPC_SECURE_DISABLE */
87  volatile uint8_t Resv_152[4];
88  volatile uint32_t DISPC_GLOBAL_MFLAG_ATTRIBUTE; /* DISPC_GLOBAL_MFLAG_ATTRIBUTE */
89  volatile uint32_t DISPC_GLOBAL_OUTPUT_ENABLE; /* DISPC_GLOBAL_OUTPUT_ENABLE */
90  volatile uint32_t DISPC_GLOBAL_BUFFER; /* DISPC_GLOBAL_BUFFER */
91  volatile uint32_t DSS_CBA_CFG; /* DSS_CBA_CFG */
92  volatile uint32_t DISPC_DBG_CONTROL; /* DISPC_DBG_CONTROL */
93  volatile uint32_t DISPC_DBG_STATUS; /* DISPC_DBG_STATUS */
94  volatile uint32_t DISPC_CLKGATING_DISABLE; /* DISPC_CLKGATING_DISABLE */
95  volatile uint8_t Resv_184[4];
96  volatile uint32_t FBDC_REVISION_1; /* FBDC_REVISION_1 */
97  volatile uint32_t FBDC_REVISION_2; /* FBDC_REVISION_2 */
98  volatile uint32_t FBDC_REVISION_3; /* FBDC_REVISION_3 */
99  volatile uint32_t FBDC_REVISION_4; /* FBDC_REVISION_4 */
100  volatile uint32_t FBDC_REVISION_5; /* FBDC_REVISION_5 */
101  volatile uint32_t FBDC_REVISION_6; /* FBDC_REVISION_6 */
102  volatile uint32_t FBDC_COMMON_CONTROL; /* FBDC_COMMON_CONTROL */
103  volatile uint32_t FBDC_CONSTANT_COLOR_0; /* FBDC_CONSTANT_COLOR_0 */
104  volatile uint32_t FBDC_CONSTANT_COLOR_1; /* FBDC_CONSTANT_COLOR_1 */
105  volatile uint8_t Resv_228[8];
106  volatile uint32_t DISPC_CONNECTIONS; /* DISPC_CONNECTIONS */
107  volatile uint32_t DISPC_MSS_VP1; /* DISPC_MERGESPLIT_VP1 */
108  volatile uint32_t DISPC_MSS_VP3; /* DISPC_MERGESPLIT_VP3 */
109  volatile uint32_t GLOBAL_DMA_THREADSIZE; /* DMA_THREADSIZE */
110  volatile uint32_t GLOBAL_DMA_THREADSIZESTATUS; /* DMA_THREADSIZESTATUS */
111  volatile uint32_t GLOBAL_GOBITMODE; /* GLOBAL_GOBITMODE */
113 
114 
115 /**************************************************************************
116 * Register Macros
117 **************************************************************************/
118 
119 #define CSL_DSS_COMMON_M_DSS_REVISION (0x00000004U)
120 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG (0x00000008U)
121 #define CSL_DSS_COMMON_M_DSS_SYSSTATUS (0x00000020U)
122 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW (0x00000028U)
123 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS (0x0000002CU)
124 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET (0x00000030U)
125 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR (0x00000034U)
126 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0 (0x00000038U)
127 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1 (0x0000003CU)
128 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2 (0x00000040U)
129 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3 (0x00000044U)
130 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0 (0x00000048U)
131 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1 (0x0000004CU)
132 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2 (0x00000050U)
133 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3 (0x00000054U)
134 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0 (0x00000058U)
135 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1 (0x0000005CU)
136 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2 (0x00000060U)
137 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3 (0x00000064U)
138 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0 (0x00000068U)
139 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1 (0x0000006CU)
140 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2 (0x00000070U)
141 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3 (0x00000074U)
142 #define CSL_DSS_COMMON_M_WB_IRQENABLE (0x00000078U)
143 #define CSL_DSS_COMMON_M_WB_IRQSTATUS (0x0000007CU)
144 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_FUNC (0x00000080U)
145 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_SAFETY (0x00000084U)
146 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_SECURITY (0x00000088U)
147 #define CSL_DSS_COMMON_M_DISPC_SECURE_DISABLE (0x00000090U)
148 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE (0x00000098U)
149 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_OUTPUT_ENABLE (0x0000009CU)
150 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER (0x000000A0U)
151 #define CSL_DSS_COMMON_M_DSS_CBA_CFG (0x000000A4U)
152 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL (0x000000A8U)
153 #define CSL_DSS_COMMON_M_DISPC_DBG_STATUS (0x000000ACU)
154 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE (0x000000B0U)
155 #define CSL_DSS_COMMON_M_FBDC_REVISION_1 (0x000000B8U)
156 #define CSL_DSS_COMMON_M_FBDC_REVISION_2 (0x000000BCU)
157 #define CSL_DSS_COMMON_M_FBDC_REVISION_3 (0x000000C0U)
158 #define CSL_DSS_COMMON_M_FBDC_REVISION_4 (0x000000C4U)
159 #define CSL_DSS_COMMON_M_FBDC_REVISION_5 (0x000000C8U)
160 #define CSL_DSS_COMMON_M_FBDC_REVISION_6 (0x000000CCU)
161 #define CSL_DSS_COMMON_M_FBDC_COMMON_CONTROL (0x000000D0U)
162 #define CSL_DSS_COMMON_M_FBDC_CONSTANT_COLOR_0 (0x000000D4U)
163 #define CSL_DSS_COMMON_M_FBDC_CONSTANT_COLOR_1 (0x000000D8U)
164 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS (0x000000E4U)
165 #define CSL_DSS_COMMON_M_DISPC_MSS_VP1 (0x000000E8U)
166 #define CSL_DSS_COMMON_M_DISPC_MSS_VP3 (0x000000ECU)
167 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZE (0x000000F0U)
168 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZESTATUS (0x000000F4U)
169 #define CSL_DSS_COMMON_M_GLOBAL_GOBITMODE (0x000000F8U)
170 
171 /**************************************************************************
172 * Field Definition Macros
173 **************************************************************************/
174 
175 
176 /* DSS_REVISION */
177 
178 #define CSL_DSS_COMMON_M_DSS_REVISION_REVMIN_MASK (0x0000003FU)
179 #define CSL_DSS_COMMON_M_DSS_REVISION_REVMIN_SHIFT (0x00000000U)
180 #define CSL_DSS_COMMON_M_DSS_REVISION_REVMIN_MAX (0x0000003FU)
181 
182 #define CSL_DSS_COMMON_M_DSS_REVISION_CUSTOM_MASK (0x000000C0U)
183 #define CSL_DSS_COMMON_M_DSS_REVISION_CUSTOM_SHIFT (0x00000006U)
184 #define CSL_DSS_COMMON_M_DSS_REVISION_CUSTOM_MAX (0x00000003U)
185 
186 #define CSL_DSS_COMMON_M_DSS_REVISION_REVMAJOR_MASK (0x00000700U)
187 #define CSL_DSS_COMMON_M_DSS_REVISION_REVMAJOR_SHIFT (0x00000008U)
188 #define CSL_DSS_COMMON_M_DSS_REVISION_REVMAJOR_MAX (0x00000007U)
189 
190 #define CSL_DSS_COMMON_M_DSS_REVISION_REVRTL_MASK (0x0000F800U)
191 #define CSL_DSS_COMMON_M_DSS_REVISION_REVRTL_SHIFT (0x0000000BU)
192 #define CSL_DSS_COMMON_M_DSS_REVISION_REVRTL_MAX (0x0000001FU)
193 
194 #define CSL_DSS_COMMON_M_DSS_REVISION_MODID_MASK (0xFFFF0000U)
195 #define CSL_DSS_COMMON_M_DSS_REVISION_MODID_SHIFT (0x00000010U)
196 #define CSL_DSS_COMMON_M_DSS_REVISION_MODID_MAX (0x0000FFFFU)
197 
198 /* DSS_SYSCONFIG */
199 
200 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_AUTOCLKGATING_MASK (0x00000001U)
201 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_AUTOCLKGATING_SHIFT (0x00000000U)
202 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_AUTOCLKGATING_MAX (0x00000001U)
203 
204 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_AUTOCLKGATING_VAL_CLKFREE (0x0U)
205 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_AUTOCLKGATING_VAL_CLKGATED (0x1U)
206 
207 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_SOFTRESET_MASK (0x00000002U)
208 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_SOFTRESET_SHIFT (0x00000001U)
209 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_SOFTRESET_MAX (0x00000001U)
210 
211 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_RESERVED1_MASK (0x00000004U)
212 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_RESERVED1_SHIFT (0x00000002U)
213 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_RESERVED1_MAX (0x00000001U)
214 
215 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_IDLEMODE_MASK (0x00000018U)
216 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_IDLEMODE_SHIFT (0x00000003U)
217 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_IDLEMODE_MAX (0x00000003U)
218 
219 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_WARMRESET_MASK (0x00000020U)
220 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_WARMRESET_SHIFT (0x00000005U)
221 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_WARMRESET_MAX (0x00000001U)
222 
223 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_RESERVED2_MASK (0x000000C0U)
224 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_RESERVED2_SHIFT (0x00000006U)
225 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_RESERVED2_MAX (0x00000003U)
226 
227 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_RESERVED3_MASK (0x00003F00U)
228 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_RESERVED3_SHIFT (0x00000008U)
229 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_RESERVED3_MAX (0x0000003FU)
230 
231 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_RESERVED4_MASK (0xFFFFC000U)
232 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_RESERVED4_SHIFT (0x0000000EU)
233 #define CSL_DSS_COMMON_M_DSS_SYSCONFIG_RESERVED4_MAX (0x0003FFFFU)
234 
235 /* DSS_SYSSTATUS */
236 
237 #define CSL_DSS_COMMON_M_DSS_SYSSTATUS_DISPC_FUNC_RESETDONE_MASK (0x00000001U)
238 #define CSL_DSS_COMMON_M_DSS_SYSSTATUS_DISPC_FUNC_RESETDONE_SHIFT (0x00000000U)
239 #define CSL_DSS_COMMON_M_DSS_SYSSTATUS_DISPC_FUNC_RESETDONE_MAX (0x00000001U)
240 
241 #define CSL_DSS_COMMON_M_DSS_SYSSTATUS_DISPC_FUNC_RESETDONE_VAL_RSTONGOING (0x0U)
242 #define CSL_DSS_COMMON_M_DSS_SYSSTATUS_DISPC_FUNC_RESETDONE_VAL_RSTCOMP (0x1U)
243 
244 #define CSL_DSS_COMMON_M_DSS_SYSSTATUS_DISPC_VP_RESETDONE_MASK (0x0000001EU)
245 #define CSL_DSS_COMMON_M_DSS_SYSSTATUS_DISPC_VP_RESETDONE_SHIFT (0x00000001U)
246 #define CSL_DSS_COMMON_M_DSS_SYSSTATUS_DISPC_VP_RESETDONE_MAX (0x0000000FU)
247 
248 #define CSL_DSS_COMMON_M_DSS_SYSSTATUS_DISPC_VP_RESETDONE_VAL_RSTONGOING (0x0U)
249 #define CSL_DSS_COMMON_M_DSS_SYSSTATUS_DISPC_VP_RESETDONE_VAL_RSTCOMP (0x1U)
250 
251 #define CSL_DSS_COMMON_M_DSS_SYSSTATUS_RESERVED5_MASK (0x000001E0U)
252 #define CSL_DSS_COMMON_M_DSS_SYSSTATUS_RESERVED5_SHIFT (0x00000005U)
253 #define CSL_DSS_COMMON_M_DSS_SYSSTATUS_RESERVED5_MAX (0x0000000FU)
254 
255 #define CSL_DSS_COMMON_M_DSS_SYSSTATUS_RESERVED5_VAL_RSTONGOING (0x0U)
256 #define CSL_DSS_COMMON_M_DSS_SYSSTATUS_RESERVED5_VAL_RSTCOMP (0x1U)
257 
258 #define CSL_DSS_COMMON_M_DSS_SYSSTATUS_DISPC_IDLE_STATUS_MASK (0x00000200U)
259 #define CSL_DSS_COMMON_M_DSS_SYSSTATUS_DISPC_IDLE_STATUS_SHIFT (0x00000009U)
260 #define CSL_DSS_COMMON_M_DSS_SYSSTATUS_DISPC_IDLE_STATUS_MAX (0x00000001U)
261 
262 #define CSL_DSS_COMMON_M_DSS_SYSSTATUS_DISPC_IDLE_STATUS_VAL_NOTIDLE (0x0U)
263 #define CSL_DSS_COMMON_M_DSS_SYSSTATUS_DISPC_IDLE_STATUS_VAL_IDLE (0x1U)
264 
265 #define CSL_DSS_COMMON_M_DSS_SYSSTATUS_RESERVED4_MASK (0xFFFFFC00U)
266 #define CSL_DSS_COMMON_M_DSS_SYSSTATUS_RESERVED4_SHIFT (0x0000000AU)
267 #define CSL_DSS_COMMON_M_DSS_SYSSTATUS_RESERVED4_MAX (0x003FFFFFU)
268 
269 /* DISPC_IRQSTATUS_RAW */
270 
271 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_VP_IRQ_MASK (0x0000000FU)
272 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_VP_IRQ_SHIFT (0x00000000U)
273 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_VP_IRQ_MAX (0x0000000FU)
274 
275 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_VP_IRQ_VAL_NOACTION (0x0U)
276 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_VP_IRQ_VAL_SET_EVENT (0x1U)
277 
278 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_VID_IRQ_MASK (0x000000F0U)
279 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_VID_IRQ_SHIFT (0x00000004U)
280 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_VID_IRQ_MAX (0x0000000FU)
281 
282 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_VID_IRQ_VAL_NOACTION (0x0U)
283 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_VID_IRQ_VAL_SET_EVENT (0x1U)
284 
285 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_RESERVED_VID_MASK (0x00001F00U)
286 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_RESERVED_VID_SHIFT (0x00000008U)
287 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_RESERVED_VID_MAX (0x0000001FU)
288 
289 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_RESERVED_CUR_MASK (0x00002000U)
290 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_RESERVED_CUR_SHIFT (0x0000000DU)
291 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_RESERVED_CUR_MAX (0x00000001U)
292 
293 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_WB_IRQ_MASK (0x00004000U)
294 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_WB_IRQ_SHIFT (0x0000000EU)
295 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_WB_IRQ_MAX (0x00000001U)
296 
297 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_WB_IRQ_VAL_NOACTION (0x0U)
298 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_WB_IRQ_VAL_SET_EVENT (0x1U)
299 
300 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_DUMMY1_IRQ_MASK (0x00008000U)
301 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_DUMMY1_IRQ_SHIFT (0x0000000FU)
302 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_DUMMY1_IRQ_MAX (0x00000001U)
303 
304 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_DUMMY1_IRQ_VAL_NOACTION (0x0U)
305 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_DUMMY1_IRQ_VAL_SET_EVENT (0x1U)
306 
307 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_DUMMY_IRQ_MASK (0x00010000U)
308 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_DUMMY_IRQ_SHIFT (0x00000010U)
309 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_DUMMY_IRQ_MAX (0x00000001U)
310 
311 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_DUMMY_IRQ_VAL_NOACTION (0x0U)
312 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_DUMMY_IRQ_VAL_SET_EVENT (0x1U)
313 
314 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_RESERVED_MASK (0xFFFE0000U)
315 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_RESERVED_SHIFT (0x00000011U)
316 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RAW_RESERVED_MAX (0x00007FFFU)
317 
318 /* DISPC_IRQSTATUS */
319 
320 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_VP_IRQ_MASK (0x0000000FU)
321 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_VP_IRQ_SHIFT (0x00000000U)
322 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_VP_IRQ_MAX (0x0000000FU)
323 
324 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_VP_IRQ_VAL_NOACTION (0x0U)
325 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_VP_IRQ_VAL_CLEAR (0x1U)
326 
327 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_VID_IRQ_MASK (0x000000F0U)
328 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_VID_IRQ_SHIFT (0x00000004U)
329 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_VID_IRQ_MAX (0x0000000FU)
330 
331 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_VID_IRQ_VAL_NOACTION (0x0U)
332 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_VID_IRQ_VAL_CLEAR (0x1U)
333 
334 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RESERVED_VID_MASK (0x00001F00U)
335 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RESERVED_VID_SHIFT (0x00000008U)
336 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RESERVED_VID_MAX (0x0000001FU)
337 
338 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RESERVED_CUR_MASK (0x00002000U)
339 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RESERVED_CUR_SHIFT (0x0000000DU)
340 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RESERVED_CUR_MAX (0x00000001U)
341 
342 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_WB_IRQ_MASK (0x00004000U)
343 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_WB_IRQ_SHIFT (0x0000000EU)
344 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_WB_IRQ_MAX (0x00000001U)
345 
346 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_WB_IRQ_VAL_NOACTION (0x0U)
347 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_WB_IRQ_VAL_CLEAR (0x1U)
348 
349 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_DUMMY1_IRQ_MASK (0x00008000U)
350 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_DUMMY1_IRQ_SHIFT (0x0000000FU)
351 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_DUMMY1_IRQ_MAX (0x00000001U)
352 
353 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_DUMMY1_IRQ_VAL_NOACTION (0x0U)
354 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_DUMMY1_IRQ_VAL_CLEAR (0x1U)
355 
356 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_DUMMY_IRQ_MASK (0x00010000U)
357 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_DUMMY_IRQ_SHIFT (0x00000010U)
358 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_DUMMY_IRQ_MAX (0x00000001U)
359 
360 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_DUMMY_IRQ_VAL_NOACTION (0x0U)
361 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_DUMMY_IRQ_VAL_CLEAR (0x1U)
362 
363 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RESERVED_MASK (0xFFFE0000U)
364 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RESERVED_SHIFT (0x00000011U)
365 #define CSL_DSS_COMMON_M_DISPC_IRQSTATUS_RESERVED_MAX (0x00007FFFU)
366 
367 /* DISPC_IRQENABLE_SET */
368 
369 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_SET_VP_IRQ_MASK (0x0000000FU)
370 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_SET_VP_IRQ_SHIFT (0x00000000U)
371 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_SET_VP_IRQ_MAX (0x0000000FU)
372 
373 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_SET_VP_IRQ_VAL_NOACTION (0x0U)
374 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_SET_VP_IRQ_VAL_ENABLE (0x1U)
375 
376 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_SET_VID_IRQ_MASK (0x000000F0U)
377 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_SET_VID_IRQ_SHIFT (0x00000004U)
378 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_SET_VID_IRQ_MAX (0x0000000FU)
379 
380 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_SET_VID_IRQ_VAL_NOACTION (0x0U)
381 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_SET_VID_IRQ_VAL_ENABLE (0x1U)
382 
383 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_RESERVED_VID_MASK (0x00001F00U)
384 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_RESERVED_VID_SHIFT (0x00000008U)
385 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_RESERVED_VID_MAX (0x0000001FU)
386 
387 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_RESERVED_CUR_MASK (0x00002000U)
388 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_RESERVED_CUR_SHIFT (0x0000000DU)
389 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_RESERVED_CUR_MAX (0x00000001U)
390 
391 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_SET_WB_IRQ_MASK (0x00004000U)
392 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_SET_WB_IRQ_SHIFT (0x0000000EU)
393 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_SET_WB_IRQ_MAX (0x00000001U)
394 
395 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_SET_WB_IRQ_VAL_NOACTION (0x0U)
396 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_SET_WB_IRQ_VAL_ENABLE (0x1U)
397 
398 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_SET_DUMMY1_IRQ_MASK (0x00008000U)
399 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_SET_DUMMY1_IRQ_SHIFT (0x0000000FU)
400 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_SET_DUMMY1_IRQ_MAX (0x00000001U)
401 
402 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_SET_DUMMY1_IRQ_VAL_NOACTION (0x0U)
403 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_SET_DUMMY1_IRQ_VAL_ENABLE (0x1U)
404 
405 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_SET_DUMMY_IRQ_MASK (0x00010000U)
406 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_SET_DUMMY_IRQ_SHIFT (0x00000010U)
407 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_SET_DUMMY_IRQ_MAX (0x00000001U)
408 
409 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_SET_DUMMY_IRQ_VAL_NOACTION (0x0U)
410 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_SET_DUMMY_IRQ_VAL_ENABLE (0x1U)
411 
412 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_RESERVED_MASK (0xFFFE0000U)
413 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_RESERVED_SHIFT (0x00000011U)
414 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_SET_RESERVED_MAX (0x00007FFFU)
415 
416 /* DISPC_IRQENABLE_CLR */
417 
418 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_MASK (0x0000000FU)
419 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_SHIFT (0x00000000U)
420 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_MAX (0x0000000FU)
421 
422 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_VAL_NOACTION (0x0U)
423 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_VAL_CLEAR (0x1U)
424 
425 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_MASK (0x000000F0U)
426 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_SHIFT (0x00000004U)
427 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_MAX (0x0000000FU)
428 
429 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_VAL_NOACTION (0x0U)
430 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_VAL_CLEAR (0x1U)
431 
432 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_RESERVED_VID_MASK (0x00001F00U)
433 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_RESERVED_VID_SHIFT (0x00000008U)
434 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_RESERVED_VID_MAX (0x0000001FU)
435 
436 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_RESERVED_CUR_MASK (0x00002000U)
437 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_RESERVED_CUR_SHIFT (0x0000000DU)
438 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_RESERVED_CUR_MAX (0x00000001U)
439 
440 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_CLR_WB_IRQ_MASK (0x00004000U)
441 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_CLR_WB_IRQ_SHIFT (0x0000000EU)
442 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_CLR_WB_IRQ_MAX (0x00000001U)
443 
444 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_CLR_WB_IRQ_VAL_NOACTION (0x0U)
445 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_CLR_WB_IRQ_VAL_CLEAR (0x1U)
446 
447 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_CLR_DUMMY1_IRQ_MASK (0x00008000U)
448 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_CLR_DUMMY1_IRQ_SHIFT (0x0000000FU)
449 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_CLR_DUMMY1_IRQ_MAX (0x00000001U)
450 
451 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_CLR_DUMMY1_IRQ_VAL_NOACTION (0x0U)
452 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_CLR_DUMMY1_IRQ_VAL_CLEAR (0x1U)
453 
454 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_CLR_DUMMY_IRQ_MASK (0x00010000U)
455 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_CLR_DUMMY_IRQ_SHIFT (0x00000010U)
456 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_CLR_DUMMY_IRQ_MAX (0x00000001U)
457 
458 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_CLR_DUMMY_IRQ_VAL_NOACTION (0x0U)
459 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_CLR_DUMMY_IRQ_VAL_CLEAR (0x1U)
460 
461 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_RESERVED_MASK (0xFFFE0000U)
462 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_RESERVED_SHIFT (0x00000011U)
463 #define CSL_DSS_COMMON_M_DISPC_IRQENABLE_CLR_RESERVED_MAX (0x00007FFFU)
464 
465 /* VID_IRQENABLE_0 */
466 
467 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_MASK (0x00000001U)
468 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_SHIFT (0x00000000U)
469 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_MAX (0x00000001U)
470 
471 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_VAL_MASKED (0x0U)
472 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_VAL_GENINT (0x1U)
473 
474 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_VIDENDWINDOW_EN_MASK (0x00000002U)
475 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_VIDENDWINDOW_EN_SHIFT (0x00000001U)
476 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_VIDENDWINDOW_EN_MAX (0x00000001U)
477 
478 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_VIDENDWINDOW_EN_VAL_MASKED (0x0U)
479 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_VIDENDWINDOW_EN_VAL_GENINT (0x1U)
480 
481 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_SAFETYREGION_EN_MASK (0x00000004U)
482 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_SAFETYREGION_EN_SHIFT (0x00000002U)
483 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_SAFETYREGION_EN_MAX (0x00000001U)
484 
485 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_SAFETYREGION_EN_VAL_MASKED (0x0U)
486 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_SAFETYREGION_EN_VAL_GENINT (0x1U)
487 
488 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_FBDC_CORRUPTTILE_EN_MASK (0x00000008U)
489 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_FBDC_CORRUPTTILE_EN_SHIFT (0x00000003U)
490 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_FBDC_CORRUPTTILE_EN_MAX (0x00000001U)
491 
492 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_FBDC_CORRUPTTILE_EN_VAL_MASKED (0x0U)
493 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_FBDC_CORRUPTTILE_EN_VAL_GENINT (0x1U)
494 
495 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_FBDC_ILLEGALTILEREQ_EN_MASK (0x00000010U)
496 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_FBDC_ILLEGALTILEREQ_EN_SHIFT (0x00000004U)
497 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_FBDC_ILLEGALTILEREQ_EN_MAX (0x00000001U)
498 
499 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_FBDC_ILLEGALTILEREQ_EN_VAL_MASKED (0x0U)
500 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_FBDC_ILLEGALTILEREQ_EN_VAL_GENINT (0x1U)
501 
502 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_RESERVED_MASK (0xFFFFFFE0U)
503 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_RESERVED_SHIFT (0x00000005U)
504 #define CSL_DSS_COMMON_M_VID_IRQENABLE_0_RESERVED_MAX (0x07FFFFFFU)
505 
506 /* VID_IRQENABLE_1 */
507 
508 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_MASK (0x00000001U)
509 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_SHIFT (0x00000000U)
510 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_MAX (0x00000001U)
511 
512 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_VAL_MASKED (0x0U)
513 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_VAL_GENINT (0x1U)
514 
515 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_VIDENDWINDOW_EN_MASK (0x00000002U)
516 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_VIDENDWINDOW_EN_SHIFT (0x00000001U)
517 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_VIDENDWINDOW_EN_MAX (0x00000001U)
518 
519 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_VIDENDWINDOW_EN_VAL_MASKED (0x0U)
520 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_VIDENDWINDOW_EN_VAL_GENINT (0x1U)
521 
522 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_SAFETYREGION_EN_MASK (0x00000004U)
523 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_SAFETYREGION_EN_SHIFT (0x00000002U)
524 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_SAFETYREGION_EN_MAX (0x00000001U)
525 
526 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_SAFETYREGION_EN_VAL_MASKED (0x0U)
527 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_SAFETYREGION_EN_VAL_GENINT (0x1U)
528 
529 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_FBDC_CORRUPTTILE_EN_MASK (0x00000008U)
530 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_FBDC_CORRUPTTILE_EN_SHIFT (0x00000003U)
531 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_FBDC_CORRUPTTILE_EN_MAX (0x00000001U)
532 
533 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_FBDC_CORRUPTTILE_EN_VAL_MASKED (0x0U)
534 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_FBDC_CORRUPTTILE_EN_VAL_GENINT (0x1U)
535 
536 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_FBDC_ILLEGALTILEREQ_EN_MASK (0x00000010U)
537 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_FBDC_ILLEGALTILEREQ_EN_SHIFT (0x00000004U)
538 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_FBDC_ILLEGALTILEREQ_EN_MAX (0x00000001U)
539 
540 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_FBDC_ILLEGALTILEREQ_EN_VAL_MASKED (0x0U)
541 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_FBDC_ILLEGALTILEREQ_EN_VAL_GENINT (0x1U)
542 
543 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_RESERVED_MASK (0xFFFFFFE0U)
544 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_RESERVED_SHIFT (0x00000005U)
545 #define CSL_DSS_COMMON_M_VID_IRQENABLE_1_RESERVED_MAX (0x07FFFFFFU)
546 
547 /* VID_IRQENABLE_2 */
548 
549 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_VIDBUFFERUNDERFLOW_EN_MASK (0x00000001U)
550 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_VIDBUFFERUNDERFLOW_EN_SHIFT (0x00000000U)
551 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_VIDBUFFERUNDERFLOW_EN_MAX (0x00000001U)
552 
553 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_VIDBUFFERUNDERFLOW_EN_VAL_MASKED (0x0U)
554 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_VIDBUFFERUNDERFLOW_EN_VAL_GENINT (0x1U)
555 
556 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_VIDENDWINDOW_EN_MASK (0x00000002U)
557 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_VIDENDWINDOW_EN_SHIFT (0x00000001U)
558 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_VIDENDWINDOW_EN_MAX (0x00000001U)
559 
560 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_VIDENDWINDOW_EN_VAL_MASKED (0x0U)
561 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_VIDENDWINDOW_EN_VAL_GENINT (0x1U)
562 
563 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_SAFETYREGION_EN_MASK (0x00000004U)
564 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_SAFETYREGION_EN_SHIFT (0x00000002U)
565 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_SAFETYREGION_EN_MAX (0x00000001U)
566 
567 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_SAFETYREGION_EN_VAL_MASKED (0x0U)
568 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_SAFETYREGION_EN_VAL_GENINT (0x1U)
569 
570 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_FBDC_CORRUPTTILE_EN_MASK (0x00000008U)
571 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_FBDC_CORRUPTTILE_EN_SHIFT (0x00000003U)
572 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_FBDC_CORRUPTTILE_EN_MAX (0x00000001U)
573 
574 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_FBDC_CORRUPTTILE_EN_VAL_MASKED (0x0U)
575 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_FBDC_CORRUPTTILE_EN_VAL_GENINT (0x1U)
576 
577 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_FBDC_ILLEGALTILEREQ_EN_MASK (0x00000010U)
578 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_FBDC_ILLEGALTILEREQ_EN_SHIFT (0x00000004U)
579 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_FBDC_ILLEGALTILEREQ_EN_MAX (0x00000001U)
580 
581 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_FBDC_ILLEGALTILEREQ_EN_VAL_MASKED (0x0U)
582 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_FBDC_ILLEGALTILEREQ_EN_VAL_GENINT (0x1U)
583 
584 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_RESERVED_MASK (0xFFFFFFE0U)
585 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_RESERVED_SHIFT (0x00000005U)
586 #define CSL_DSS_COMMON_M_VID_IRQENABLE_2_RESERVED_MAX (0x07FFFFFFU)
587 
588 /* VID_IRQENABLE_3 */
589 
590 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_VIDBUFFERUNDERFLOW_EN_MASK (0x00000001U)
591 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_VIDBUFFERUNDERFLOW_EN_SHIFT (0x00000000U)
592 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_VIDBUFFERUNDERFLOW_EN_MAX (0x00000001U)
593 
594 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_VIDBUFFERUNDERFLOW_EN_VAL_MASKED (0x0U)
595 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_VIDBUFFERUNDERFLOW_EN_VAL_GENINT (0x1U)
596 
597 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_VIDENDWINDOW_EN_MASK (0x00000002U)
598 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_VIDENDWINDOW_EN_SHIFT (0x00000001U)
599 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_VIDENDWINDOW_EN_MAX (0x00000001U)
600 
601 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_VIDENDWINDOW_EN_VAL_MASKED (0x0U)
602 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_VIDENDWINDOW_EN_VAL_GENINT (0x1U)
603 
604 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_SAFETYREGION_EN_MASK (0x00000004U)
605 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_SAFETYREGION_EN_SHIFT (0x00000002U)
606 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_SAFETYREGION_EN_MAX (0x00000001U)
607 
608 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_SAFETYREGION_EN_VAL_MASKED (0x0U)
609 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_SAFETYREGION_EN_VAL_GENINT (0x1U)
610 
611 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_FBDC_CORRUPTTILE_EN_MASK (0x00000008U)
612 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_FBDC_CORRUPTTILE_EN_SHIFT (0x00000003U)
613 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_FBDC_CORRUPTTILE_EN_MAX (0x00000001U)
614 
615 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_FBDC_CORRUPTTILE_EN_VAL_MASKED (0x0U)
616 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_FBDC_CORRUPTTILE_EN_VAL_GENINT (0x1U)
617 
618 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_FBDC_ILLEGALTILEREQ_EN_MASK (0x00000010U)
619 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_FBDC_ILLEGALTILEREQ_EN_SHIFT (0x00000004U)
620 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_FBDC_ILLEGALTILEREQ_EN_MAX (0x00000001U)
621 
622 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_FBDC_ILLEGALTILEREQ_EN_VAL_MASKED (0x0U)
623 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_FBDC_ILLEGALTILEREQ_EN_VAL_GENINT (0x1U)
624 
625 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_RESERVED_MASK (0xFFFFFFE0U)
626 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_RESERVED_SHIFT (0x00000005U)
627 #define CSL_DSS_COMMON_M_VID_IRQENABLE_3_RESERVED_MAX (0x07FFFFFFU)
628 
629 /* VID_IRQSTATUS_0 */
630 
631 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_MASK (0x00000001U)
632 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_SHIFT (0x00000000U)
633 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_MAX (0x00000001U)
634 
635 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_VAL_NOPEND (0x0U)
636 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_VAL_PEND (0x1U)
637 
638 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_MASK (0x00000002U)
639 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_SHIFT (0x00000001U)
640 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_MAX (0x00000001U)
641 
642 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_VAL_NOPEND (0x0U)
643 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_VAL_PEND (0x1U)
644 
645 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_SAFETYREGION_IRQ_MASK (0x00000004U)
646 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_SAFETYREGION_IRQ_SHIFT (0x00000002U)
647 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_SAFETYREGION_IRQ_MAX (0x00000001U)
648 
649 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
650 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_PEND (0x1U)
651 
652 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_FBDC_CORRUPTTILE_IRQ_MASK (0x00000008U)
653 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_FBDC_CORRUPTTILE_IRQ_SHIFT (0x00000003U)
654 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_FBDC_CORRUPTTILE_IRQ_MAX (0x00000001U)
655 
656 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_FBDC_CORRUPTTILE_IRQ_VAL_NOPEND (0x0U)
657 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_FBDC_CORRUPTTILE_IRQ_VAL_PEND (0x1U)
658 
659 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_FBDC_ILLEGALTILEREQ_IRQ_MASK (0x00000010U)
660 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_FBDC_ILLEGALTILEREQ_IRQ_SHIFT (0x00000004U)
661 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_FBDC_ILLEGALTILEREQ_IRQ_MAX (0x00000001U)
662 
663 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_FBDC_ILLEGALTILEREQ_IRQ_VAL_NOPEND (0x0U)
664 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_FBDC_ILLEGALTILEREQ_IRQ_VAL_PEND (0x1U)
665 
666 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_RESERVED_MASK (0xFFFFFFE0U)
667 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_RESERVED_SHIFT (0x00000005U)
668 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_0_RESERVED_MAX (0x07FFFFFFU)
669 
670 /* VID_IRQSTATUS_1 */
671 
672 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_MASK (0x00000001U)
673 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_SHIFT (0x00000000U)
674 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_MAX (0x00000001U)
675 
676 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_VAL_NOPEND (0x0U)
677 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_VAL_PEND (0x1U)
678 
679 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_MASK (0x00000002U)
680 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_SHIFT (0x00000001U)
681 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_MAX (0x00000001U)
682 
683 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_VAL_NOPEND (0x0U)
684 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_VAL_PEND (0x1U)
685 
686 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_SAFETYREGION_IRQ_MASK (0x00000004U)
687 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_SAFETYREGION_IRQ_SHIFT (0x00000002U)
688 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_SAFETYREGION_IRQ_MAX (0x00000001U)
689 
690 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
691 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_PEND (0x1U)
692 
693 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_FBDC_CORRUPTTILE_IRQ_MASK (0x00000008U)
694 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_FBDC_CORRUPTTILE_IRQ_SHIFT (0x00000003U)
695 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_FBDC_CORRUPTTILE_IRQ_MAX (0x00000001U)
696 
697 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_FBDC_CORRUPTTILE_IRQ_VAL_NOPEND (0x0U)
698 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_FBDC_CORRUPTTILE_IRQ_VAL_PEND (0x1U)
699 
700 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_FBDC_ILLEGALTILEREQ_IRQ_MASK (0x00000010U)
701 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_FBDC_ILLEGALTILEREQ_IRQ_SHIFT (0x00000004U)
702 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_FBDC_ILLEGALTILEREQ_IRQ_MAX (0x00000001U)
703 
704 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_FBDC_ILLEGALTILEREQ_IRQ_VAL_NOPEND (0x0U)
705 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_FBDC_ILLEGALTILEREQ_IRQ_VAL_PEND (0x1U)
706 
707 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_RESERVED_MASK (0xFFFFFFE0U)
708 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_RESERVED_SHIFT (0x00000005U)
709 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_1_RESERVED_MAX (0x07FFFFFFU)
710 
711 /* VID_IRQSTATUS_2 */
712 
713 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_VIDBUFFERUNDERFLOW_IRQ_MASK (0x00000001U)
714 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_VIDBUFFERUNDERFLOW_IRQ_SHIFT (0x00000000U)
715 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_VIDBUFFERUNDERFLOW_IRQ_MAX (0x00000001U)
716 
717 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_VIDBUFFERUNDERFLOW_IRQ_VAL_NOPEND (0x0U)
718 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_VIDBUFFERUNDERFLOW_IRQ_VAL_PEND (0x1U)
719 
720 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_VIDENDWINDOW_IRQ_MASK (0x00000002U)
721 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_VIDENDWINDOW_IRQ_SHIFT (0x00000001U)
722 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_VIDENDWINDOW_IRQ_MAX (0x00000001U)
723 
724 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_VIDENDWINDOW_IRQ_VAL_NOPEND (0x0U)
725 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_VIDENDWINDOW_IRQ_VAL_PEND (0x1U)
726 
727 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_SAFETYREGION_IRQ_MASK (0x00000004U)
728 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_SAFETYREGION_IRQ_SHIFT (0x00000002U)
729 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_SAFETYREGION_IRQ_MAX (0x00000001U)
730 
731 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
732 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_SAFETYREGION_IRQ_VAL_PEND (0x1U)
733 
734 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_FBDC_CORRUPTTILE_IRQ_MASK (0x00000008U)
735 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_FBDC_CORRUPTTILE_IRQ_SHIFT (0x00000003U)
736 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_FBDC_CORRUPTTILE_IRQ_MAX (0x00000001U)
737 
738 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_FBDC_CORRUPTTILE_IRQ_VAL_NOPEND (0x0U)
739 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_FBDC_CORRUPTTILE_IRQ_VAL_PEND (0x1U)
740 
741 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_FBDC_ILLEGALTILEREQ_IRQ_MASK (0x00000010U)
742 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_FBDC_ILLEGALTILEREQ_IRQ_SHIFT (0x00000004U)
743 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_FBDC_ILLEGALTILEREQ_IRQ_MAX (0x00000001U)
744 
745 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_FBDC_ILLEGALTILEREQ_IRQ_VAL_NOPEND (0x0U)
746 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_FBDC_ILLEGALTILEREQ_IRQ_VAL_PEND (0x1U)
747 
748 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_RESERVED_MASK (0xFFFFFFE0U)
749 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_RESERVED_SHIFT (0x00000005U)
750 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_2_RESERVED_MAX (0x07FFFFFFU)
751 
752 /* VID_IRQSTATUS_3 */
753 
754 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_VIDBUFFERUNDERFLOW_IRQ_MASK (0x00000001U)
755 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_VIDBUFFERUNDERFLOW_IRQ_SHIFT (0x00000000U)
756 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_VIDBUFFERUNDERFLOW_IRQ_MAX (0x00000001U)
757 
758 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_VIDBUFFERUNDERFLOW_IRQ_VAL_NOPEND (0x0U)
759 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_VIDBUFFERUNDERFLOW_IRQ_VAL_PEND (0x1U)
760 
761 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_VIDENDWINDOW_IRQ_MASK (0x00000002U)
762 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_VIDENDWINDOW_IRQ_SHIFT (0x00000001U)
763 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_VIDENDWINDOW_IRQ_MAX (0x00000001U)
764 
765 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_VIDENDWINDOW_IRQ_VAL_NOPEND (0x0U)
766 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_VIDENDWINDOW_IRQ_VAL_PEND (0x1U)
767 
768 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_SAFETYREGION_IRQ_MASK (0x00000004U)
769 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_SAFETYREGION_IRQ_SHIFT (0x00000002U)
770 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_SAFETYREGION_IRQ_MAX (0x00000001U)
771 
772 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
773 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_SAFETYREGION_IRQ_VAL_PEND (0x1U)
774 
775 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_FBDC_CORRUPTTILE_IRQ_MASK (0x00000008U)
776 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_FBDC_CORRUPTTILE_IRQ_SHIFT (0x00000003U)
777 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_FBDC_CORRUPTTILE_IRQ_MAX (0x00000001U)
778 
779 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_FBDC_CORRUPTTILE_IRQ_VAL_NOPEND (0x0U)
780 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_FBDC_CORRUPTTILE_IRQ_VAL_PEND (0x1U)
781 
782 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_FBDC_ILLEGALTILEREQ_IRQ_MASK (0x00000010U)
783 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_FBDC_ILLEGALTILEREQ_IRQ_SHIFT (0x00000004U)
784 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_FBDC_ILLEGALTILEREQ_IRQ_MAX (0x00000001U)
785 
786 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_FBDC_ILLEGALTILEREQ_IRQ_VAL_NOPEND (0x0U)
787 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_FBDC_ILLEGALTILEREQ_IRQ_VAL_PEND (0x1U)
788 
789 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_RESERVED_MASK (0xFFFFFFE0U)
790 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_RESERVED_SHIFT (0x00000005U)
791 #define CSL_DSS_COMMON_M_VID_IRQSTATUS_3_RESERVED_MAX (0x07FFFFFFU)
792 
793 /* VP_IRQENABLE_0 */
794 
795 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPFRAMEDONE_EN_MASK (0x00000001U)
796 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPFRAMEDONE_EN_SHIFT (0x00000000U)
797 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPFRAMEDONE_EN_MAX (0x00000001U)
798 
799 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPFRAMEDONE_EN_VAL_MASKED (0x0U)
800 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPFRAMEDONE_EN_VAL_GENINT (0x1U)
801 
802 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPVSYNC_EN_MASK (0x00000002U)
803 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPVSYNC_EN_SHIFT (0x00000001U)
804 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPVSYNC_EN_MAX (0x00000001U)
805 
806 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPVSYNC_EN_VAL_MASKED (0x0U)
807 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPVSYNC_EN_VAL_GENINT (0x1U)
808 
809 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPVSYNC_ODD_EN_MASK (0x00000004U)
810 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPVSYNC_ODD_EN_SHIFT (0x00000002U)
811 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPVSYNC_ODD_EN_MAX (0x00000001U)
812 
813 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPVSYNC_ODD_EN_VAL_MASKED (0x0U)
814 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPVSYNC_ODD_EN_VAL_GENINT (0x1U)
815 
816 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_MASK (0x00000008U)
817 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_SHIFT (0x00000003U)
818 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_MAX (0x00000001U)
819 
820 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_VAL_MASKED (0x0U)
821 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_VAL_GENINT (0x1U)
822 
823 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPSYNCLOST_EN_MASK (0x00000010U)
824 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPSYNCLOST_EN_SHIFT (0x00000004U)
825 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPSYNCLOST_EN_MAX (0x00000001U)
826 
827 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPSYNCLOST_EN_VAL_MASKED (0x0U)
828 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPSYNCLOST_EN_VAL_GENINT (0x1U)
829 
830 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_MASK (0x00000020U)
831 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_SHIFT (0x00000005U)
832 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_MAX (0x00000001U)
833 
834 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_VAL_MASKED (0x0U)
835 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_VAL_GENINT (0x1U)
836 
837 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_SAFETYREGION_EN_MASK (0x000003C0U)
838 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_SAFETYREGION_EN_SHIFT (0x00000006U)
839 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_SAFETYREGION_EN_MAX (0x0000000FU)
840 
841 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_SAFETYREGION_EN_VAL_MASKED (0x0U)
842 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_SAFETYREGION_EN_VAL_GENINT (0x1U)
843 
844 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_SECURITYVIOLATION_EN_MASK (0x00000400U)
845 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_SECURITYVIOLATION_EN_SHIFT (0x0000000AU)
846 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_SECURITYVIOLATION_EN_MAX (0x00000001U)
847 
848 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
849 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
850 
851 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPSYNC_EN_MASK (0x00000800U)
852 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPSYNC_EN_SHIFT (0x0000000BU)
853 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPSYNC_EN_MAX (0x00000001U)
854 
855 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPSYNC_EN_VAL_MASKED (0x0U)
856 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPSYNC_EN_VAL_GENINT (0x1U)
857 
858 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_DUMMY_EN_MASK (0x00001000U)
859 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_DUMMY_EN_SHIFT (0x0000000CU)
860 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_DUMMY_EN_MAX (0x00000001U)
861 
862 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_DUMMY_EN_VAL_MASKED (0x0U)
863 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_DUMMY_EN_VAL_GENINT (0x1U)
864 
865 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_SAFETYREGION1_EN_MASK (0x0001E000U)
866 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_SAFETYREGION1_EN_SHIFT (0x0000000DU)
867 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_SAFETYREGION1_EN_MAX (0x0000000FU)
868 
869 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_SAFETYREGION1_EN_VAL_MASKED (0x0U)
870 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_SAFETYREGION1_EN_VAL_GENINT (0x1U)
871 
872 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_RESERVED_MASK (0xFFFE0000U)
873 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_RESERVED_SHIFT (0x00000011U)
874 #define CSL_DSS_COMMON_M_VP_IRQENABLE_0_RESERVED_MAX (0x00007FFFU)
875 
876 /* VP_IRQENABLE_1 */
877 
878 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPFRAMEDONE_EN_MASK (0x00000001U)
879 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPFRAMEDONE_EN_SHIFT (0x00000000U)
880 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPFRAMEDONE_EN_MAX (0x00000001U)
881 
882 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPFRAMEDONE_EN_VAL_MASKED (0x0U)
883 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPFRAMEDONE_EN_VAL_GENINT (0x1U)
884 
885 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPVSYNC_EN_MASK (0x00000002U)
886 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPVSYNC_EN_SHIFT (0x00000001U)
887 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPVSYNC_EN_MAX (0x00000001U)
888 
889 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPVSYNC_EN_VAL_MASKED (0x0U)
890 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPVSYNC_EN_VAL_GENINT (0x1U)
891 
892 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPVSYNC_ODD_EN_MASK (0x00000004U)
893 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPVSYNC_ODD_EN_SHIFT (0x00000002U)
894 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPVSYNC_ODD_EN_MAX (0x00000001U)
895 
896 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPVSYNC_ODD_EN_VAL_MASKED (0x0U)
897 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPVSYNC_ODD_EN_VAL_GENINT (0x1U)
898 
899 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_MASK (0x00000008U)
900 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_SHIFT (0x00000003U)
901 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_MAX (0x00000001U)
902 
903 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_VAL_MASKED (0x0U)
904 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_VAL_GENINT (0x1U)
905 
906 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPSYNCLOST_EN_MASK (0x00000010U)
907 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPSYNCLOST_EN_SHIFT (0x00000004U)
908 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPSYNCLOST_EN_MAX (0x00000001U)
909 
910 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPSYNCLOST_EN_VAL_MASKED (0x0U)
911 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPSYNCLOST_EN_VAL_GENINT (0x1U)
912 
913 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_MASK (0x00000020U)
914 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_SHIFT (0x00000005U)
915 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_MAX (0x00000001U)
916 
917 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_VAL_MASKED (0x0U)
918 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_VAL_GENINT (0x1U)
919 
920 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_SAFETYREGION_EN_MASK (0x000003C0U)
921 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_SAFETYREGION_EN_SHIFT (0x00000006U)
922 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_SAFETYREGION_EN_MAX (0x0000000FU)
923 
924 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_SAFETYREGION_EN_VAL_MASKED (0x0U)
925 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_SAFETYREGION_EN_VAL_GENINT (0x1U)
926 
927 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_SECURITYVIOLATION_EN_MASK (0x00000400U)
928 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_SECURITYVIOLATION_EN_SHIFT (0x0000000AU)
929 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_SECURITYVIOLATION_EN_MAX (0x00000001U)
930 
931 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
932 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
933 
934 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPSYNC_EN_MASK (0x00000800U)
935 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPSYNC_EN_SHIFT (0x0000000BU)
936 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPSYNC_EN_MAX (0x00000001U)
937 
938 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPSYNC_EN_VAL_MASKED (0x0U)
939 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_VPSYNC_EN_VAL_GENINT (0x1U)
940 
941 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_DUMMY_EN_MASK (0x00001000U)
942 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_DUMMY_EN_SHIFT (0x0000000CU)
943 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_DUMMY_EN_MAX (0x00000001U)
944 
945 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_DUMMY_EN_VAL_MASKED (0x0U)
946 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_DUMMY_EN_VAL_GENINT (0x1U)
947 
948 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_SAFETYREGION1_EN_MASK (0x0001E000U)
949 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_SAFETYREGION1_EN_SHIFT (0x0000000DU)
950 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_SAFETYREGION1_EN_MAX (0x0000000FU)
951 
952 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_SAFETYREGION1_EN_VAL_MASKED (0x0U)
953 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_SAFETYREGION1_EN_VAL_GENINT (0x1U)
954 
955 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_RESERVED_MASK (0xFFFE0000U)
956 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_RESERVED_SHIFT (0x00000011U)
957 #define CSL_DSS_COMMON_M_VP_IRQENABLE_1_RESERVED_MAX (0x00007FFFU)
958 
959 /* VP_IRQENABLE_2 */
960 
961 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPFRAMEDONE_EN_MASK (0x00000001U)
962 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPFRAMEDONE_EN_SHIFT (0x00000000U)
963 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPFRAMEDONE_EN_MAX (0x00000001U)
964 
965 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPFRAMEDONE_EN_VAL_MASKED (0x0U)
966 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPFRAMEDONE_EN_VAL_GENINT (0x1U)
967 
968 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPVSYNC_EN_MASK (0x00000002U)
969 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPVSYNC_EN_SHIFT (0x00000001U)
970 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPVSYNC_EN_MAX (0x00000001U)
971 
972 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPVSYNC_EN_VAL_MASKED (0x0U)
973 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPVSYNC_EN_VAL_GENINT (0x1U)
974 
975 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPVSYNC_ODD_EN_MASK (0x00000004U)
976 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPVSYNC_ODD_EN_SHIFT (0x00000002U)
977 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPVSYNC_ODD_EN_MAX (0x00000001U)
978 
979 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPVSYNC_ODD_EN_VAL_MASKED (0x0U)
980 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPVSYNC_ODD_EN_VAL_GENINT (0x1U)
981 
982 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPPROGRAMMEDLINENUMBER_EN_MASK (0x00000008U)
983 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPPROGRAMMEDLINENUMBER_EN_SHIFT (0x00000003U)
984 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPPROGRAMMEDLINENUMBER_EN_MAX (0x00000001U)
985 
986 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPPROGRAMMEDLINENUMBER_EN_VAL_MASKED (0x0U)
987 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPPROGRAMMEDLINENUMBER_EN_VAL_GENINT (0x1U)
988 
989 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPSYNCLOST_EN_MASK (0x00000010U)
990 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPSYNCLOST_EN_SHIFT (0x00000004U)
991 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPSYNCLOST_EN_MAX (0x00000001U)
992 
993 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPSYNCLOST_EN_VAL_MASKED (0x0U)
994 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPSYNCLOST_EN_VAL_GENINT (0x1U)
995 
996 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_ACBIASCOUNTSTATUS_EN_MASK (0x00000020U)
997 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_ACBIASCOUNTSTATUS_EN_SHIFT (0x00000005U)
998 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_ACBIASCOUNTSTATUS_EN_MAX (0x00000001U)
999 
1000 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_ACBIASCOUNTSTATUS_EN_VAL_MASKED (0x0U)
1001 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_ACBIASCOUNTSTATUS_EN_VAL_GENINT (0x1U)
1002 
1003 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_SAFETYREGION_EN_MASK (0x000003C0U)
1004 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_SAFETYREGION_EN_SHIFT (0x00000006U)
1005 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_SAFETYREGION_EN_MAX (0x0000000FU)
1006 
1007 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_SAFETYREGION_EN_VAL_MASKED (0x0U)
1008 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_SAFETYREGION_EN_VAL_GENINT (0x1U)
1009 
1010 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_SECURITYVIOLATION_EN_MASK (0x00000400U)
1011 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_SECURITYVIOLATION_EN_SHIFT (0x0000000AU)
1012 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_SECURITYVIOLATION_EN_MAX (0x00000001U)
1013 
1014 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
1015 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
1016 
1017 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPSYNC_EN_MASK (0x00000800U)
1018 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPSYNC_EN_SHIFT (0x0000000BU)
1019 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPSYNC_EN_MAX (0x00000001U)
1020 
1021 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPSYNC_EN_VAL_MASKED (0x0U)
1022 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_VPSYNC_EN_VAL_GENINT (0x1U)
1023 
1024 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_DUMMY_EN_MASK (0x00001000U)
1025 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_DUMMY_EN_SHIFT (0x0000000CU)
1026 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_DUMMY_EN_MAX (0x00000001U)
1027 
1028 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_DUMMY_EN_VAL_MASKED (0x0U)
1029 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_DUMMY_EN_VAL_GENINT (0x1U)
1030 
1031 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_SAFETYREGION1_EN_MASK (0x0001E000U)
1032 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_SAFETYREGION1_EN_SHIFT (0x0000000DU)
1033 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_SAFETYREGION1_EN_MAX (0x0000000FU)
1034 
1035 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_SAFETYREGION1_EN_VAL_MASKED (0x0U)
1036 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_SAFETYREGION1_EN_VAL_GENINT (0x1U)
1037 
1038 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_RESERVED_MASK (0xFFFE0000U)
1039 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_RESERVED_SHIFT (0x00000011U)
1040 #define CSL_DSS_COMMON_M_VP_IRQENABLE_2_RESERVED_MAX (0x00007FFFU)
1041 
1042 /* VP_IRQENABLE_3 */
1043 
1044 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPFRAMEDONE_EN_MASK (0x00000001U)
1045 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPFRAMEDONE_EN_SHIFT (0x00000000U)
1046 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPFRAMEDONE_EN_MAX (0x00000001U)
1047 
1048 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPFRAMEDONE_EN_VAL_MASKED (0x0U)
1049 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPFRAMEDONE_EN_VAL_GENINT (0x1U)
1050 
1051 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPVSYNC_EN_MASK (0x00000002U)
1052 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPVSYNC_EN_SHIFT (0x00000001U)
1053 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPVSYNC_EN_MAX (0x00000001U)
1054 
1055 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPVSYNC_EN_VAL_MASKED (0x0U)
1056 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPVSYNC_EN_VAL_GENINT (0x1U)
1057 
1058 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPVSYNC_ODD_EN_MASK (0x00000004U)
1059 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPVSYNC_ODD_EN_SHIFT (0x00000002U)
1060 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPVSYNC_ODD_EN_MAX (0x00000001U)
1061 
1062 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPVSYNC_ODD_EN_VAL_MASKED (0x0U)
1063 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPVSYNC_ODD_EN_VAL_GENINT (0x1U)
1064 
1065 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPPROGRAMMEDLINENUMBER_EN_MASK (0x00000008U)
1066 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPPROGRAMMEDLINENUMBER_EN_SHIFT (0x00000003U)
1067 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPPROGRAMMEDLINENUMBER_EN_MAX (0x00000001U)
1068 
1069 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPPROGRAMMEDLINENUMBER_EN_VAL_MASKED (0x0U)
1070 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPPROGRAMMEDLINENUMBER_EN_VAL_GENINT (0x1U)
1071 
1072 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPSYNCLOST_EN_MASK (0x00000010U)
1073 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPSYNCLOST_EN_SHIFT (0x00000004U)
1074 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPSYNCLOST_EN_MAX (0x00000001U)
1075 
1076 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPSYNCLOST_EN_VAL_MASKED (0x0U)
1077 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPSYNCLOST_EN_VAL_GENINT (0x1U)
1078 
1079 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_ACBIASCOUNTSTATUS_EN_MASK (0x00000020U)
1080 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_ACBIASCOUNTSTATUS_EN_SHIFT (0x00000005U)
1081 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_ACBIASCOUNTSTATUS_EN_MAX (0x00000001U)
1082 
1083 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_ACBIASCOUNTSTATUS_EN_VAL_MASKED (0x0U)
1084 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_ACBIASCOUNTSTATUS_EN_VAL_GENINT (0x1U)
1085 
1086 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_SAFETYREGION_EN_MASK (0x000003C0U)
1087 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_SAFETYREGION_EN_SHIFT (0x00000006U)
1088 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_SAFETYREGION_EN_MAX (0x0000000FU)
1089 
1090 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_SAFETYREGION_EN_VAL_MASKED (0x0U)
1091 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_SAFETYREGION_EN_VAL_GENINT (0x1U)
1092 
1093 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_SECURITYVIOLATION_EN_MASK (0x00000400U)
1094 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_SECURITYVIOLATION_EN_SHIFT (0x0000000AU)
1095 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_SECURITYVIOLATION_EN_MAX (0x00000001U)
1096 
1097 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
1098 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
1099 
1100 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPSYNC_EN_MASK (0x00000800U)
1101 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPSYNC_EN_SHIFT (0x0000000BU)
1102 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPSYNC_EN_MAX (0x00000001U)
1103 
1104 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPSYNC_EN_VAL_MASKED (0x0U)
1105 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_VPSYNC_EN_VAL_GENINT (0x1U)
1106 
1107 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_DUMMY_EN_MASK (0x00001000U)
1108 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_DUMMY_EN_SHIFT (0x0000000CU)
1109 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_DUMMY_EN_MAX (0x00000001U)
1110 
1111 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_DUMMY_EN_VAL_MASKED (0x0U)
1112 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_DUMMY_EN_VAL_GENINT (0x1U)
1113 
1114 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_SAFETYREGION1_EN_MASK (0x0001E000U)
1115 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_SAFETYREGION1_EN_SHIFT (0x0000000DU)
1116 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_SAFETYREGION1_EN_MAX (0x0000000FU)
1117 
1118 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_SAFETYREGION1_EN_VAL_MASKED (0x0U)
1119 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_SAFETYREGION1_EN_VAL_GENINT (0x1U)
1120 
1121 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_RESERVED_MASK (0xFFFE0000U)
1122 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_RESERVED_SHIFT (0x00000011U)
1123 #define CSL_DSS_COMMON_M_VP_IRQENABLE_3_RESERVED_MAX (0x00007FFFU)
1124 
1125 /* VP_IRQSTATUS_0 */
1126 
1127 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_MASK (0x00000001U)
1128 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_SHIFT (0x00000000U)
1129 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_MAX (0x00000001U)
1130 
1131 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
1132 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_VAL_PEND (0x1U)
1133 
1134 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPVSYNC_IRQ_MASK (0x00000002U)
1135 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPVSYNC_IRQ_SHIFT (0x00000001U)
1136 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPVSYNC_IRQ_MAX (0x00000001U)
1137 
1138 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPVSYNC_IRQ_VAL_NOPEND (0x0U)
1139 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPVSYNC_IRQ_VAL_PEND (0x1U)
1140 
1141 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_MASK (0x00000004U)
1142 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_SHIFT (0x00000002U)
1143 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_MAX (0x00000001U)
1144 
1145 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_VAL_NOPEND (0x0U)
1146 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_VAL_PEND (0x1U)
1147 
1148 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_MASK (0x00000008U)
1149 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_SHIFT (0x00000003U)
1150 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_MAX (0x00000001U)
1151 
1152 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_VAL_NOPEND (0x0U)
1153 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_VAL_PEND (0x1U)
1154 
1155 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_MASK (0x00000010U)
1156 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_SHIFT (0x00000004U)
1157 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_MAX (0x00000001U)
1158 
1159 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_VAL_NOPEND (0x0U)
1160 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_VAL_PEND (0x1U)
1161 
1162 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_MASK (0x00000020U)
1163 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_SHIFT (0x00000005U)
1164 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_MAX (0x00000001U)
1165 
1166 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_VAL_NOPEND (0x0U)
1167 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_VAL_PEND (0x1U)
1168 
1169 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_SAFETYREGION_IRQ_MASK (0x000003C0U)
1170 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_SAFETYREGION_IRQ_SHIFT (0x00000006U)
1171 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_SAFETYREGION_IRQ_MAX (0x0000000FU)
1172 
1173 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
1174 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_PEND (0x1U)
1175 
1176 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_MASK (0x00000400U)
1177 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_SHIFT (0x0000000AU)
1178 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
1179 
1180 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
1181 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
1182 
1183 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPSYNC_IRQ_MASK (0x00000800U)
1184 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPSYNC_IRQ_SHIFT (0x0000000BU)
1185 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPSYNC_IRQ_MAX (0x00000001U)
1186 
1187 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPSYNC_IRQ_VAL_NOPEND (0x0U)
1188 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_VPSYNC_IRQ_VAL_PEND (0x1U)
1189 
1190 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_DUMMY_IRQ_MASK (0x00001000U)
1191 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_DUMMY_IRQ_SHIFT (0x0000000CU)
1192 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_DUMMY_IRQ_MAX (0x00000001U)
1193 
1194 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_DUMMY_IRQ_VAL_NOPEND (0x0U)
1195 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_DUMMY_IRQ_VAL_PEND (0x1U)
1196 
1197 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_SAFETYREGION1_IRQ_MASK (0x0001E000U)
1198 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_SAFETYREGION1_IRQ_SHIFT (0x0000000DU)
1199 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_SAFETYREGION1_IRQ_MAX (0x0000000FU)
1200 
1201 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_SAFETYREGION1_IRQ_VAL_NOPEND (0x0U)
1202 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_SAFETYREGION1_IRQ_VAL_PEND (0x1U)
1203 
1204 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_RESERVED_MASK (0xFFFE0000U)
1205 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_RESERVED_SHIFT (0x00000011U)
1206 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_0_RESERVED_MAX (0x00007FFFU)
1207 
1208 /* VP_IRQSTATUS_1 */
1209 
1210 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_MASK (0x00000001U)
1211 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_SHIFT (0x00000000U)
1212 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_MAX (0x00000001U)
1213 
1214 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
1215 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_VAL_PEND (0x1U)
1216 
1217 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPVSYNC_IRQ_MASK (0x00000002U)
1218 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPVSYNC_IRQ_SHIFT (0x00000001U)
1219 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPVSYNC_IRQ_MAX (0x00000001U)
1220 
1221 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPVSYNC_IRQ_VAL_NOPEND (0x0U)
1222 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPVSYNC_IRQ_VAL_PEND (0x1U)
1223 
1224 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_MASK (0x00000004U)
1225 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_SHIFT (0x00000002U)
1226 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_MAX (0x00000001U)
1227 
1228 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_VAL_NOPEND (0x0U)
1229 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_VAL_PEND (0x1U)
1230 
1231 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_MASK (0x00000008U)
1232 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_SHIFT (0x00000003U)
1233 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_MAX (0x00000001U)
1234 
1235 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_VAL_NOPEND (0x0U)
1236 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_VAL_PEND (0x1U)
1237 
1238 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_MASK (0x00000010U)
1239 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_SHIFT (0x00000004U)
1240 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_MAX (0x00000001U)
1241 
1242 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_VAL_NOPEND (0x0U)
1243 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_VAL_PEND (0x1U)
1244 
1245 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_MASK (0x00000020U)
1246 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_SHIFT (0x00000005U)
1247 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_MAX (0x00000001U)
1248 
1249 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_VAL_NOPEND (0x0U)
1250 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_VAL_PEND (0x1U)
1251 
1252 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_SAFETYREGION_IRQ_MASK (0x000003C0U)
1253 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_SAFETYREGION_IRQ_SHIFT (0x00000006U)
1254 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_SAFETYREGION_IRQ_MAX (0x0000000FU)
1255 
1256 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
1257 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_PEND (0x1U)
1258 
1259 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_MASK (0x00000400U)
1260 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_SHIFT (0x0000000AU)
1261 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
1262 
1263 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
1264 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
1265 
1266 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPSYNC_IRQ_MASK (0x00000800U)
1267 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPSYNC_IRQ_SHIFT (0x0000000BU)
1268 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPSYNC_IRQ_MAX (0x00000001U)
1269 
1270 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPSYNC_IRQ_VAL_NOPEND (0x0U)
1271 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_VPSYNC_IRQ_VAL_PEND (0x1U)
1272 
1273 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_DUMMY_IRQ_MASK (0x00001000U)
1274 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_DUMMY_IRQ_SHIFT (0x0000000CU)
1275 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_DUMMY_IRQ_MAX (0x00000001U)
1276 
1277 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_DUMMY_IRQ_VAL_NOPEND (0x0U)
1278 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_DUMMY_IRQ_VAL_PEND (0x1U)
1279 
1280 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_SAFETYREGION1_IRQ_MASK (0x0001E000U)
1281 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_SAFETYREGION1_IRQ_SHIFT (0x0000000DU)
1282 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_SAFETYREGION1_IRQ_MAX (0x0000000FU)
1283 
1284 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_SAFETYREGION1_IRQ_VAL_NOPEND (0x0U)
1285 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_SAFETYREGION1_IRQ_VAL_PEND (0x1U)
1286 
1287 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_RESERVED_MASK (0xFFFE0000U)
1288 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_RESERVED_SHIFT (0x00000011U)
1289 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_1_RESERVED_MAX (0x00007FFFU)
1290 
1291 /* VP_IRQSTATUS_2 */
1292 
1293 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPFRAMEDONE_IRQ_MASK (0x00000001U)
1294 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPFRAMEDONE_IRQ_SHIFT (0x00000000U)
1295 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPFRAMEDONE_IRQ_MAX (0x00000001U)
1296 
1297 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
1298 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPFRAMEDONE_IRQ_VAL_PEND (0x1U)
1299 
1300 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPVSYNC_IRQ_MASK (0x00000002U)
1301 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPVSYNC_IRQ_SHIFT (0x00000001U)
1302 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPVSYNC_IRQ_MAX (0x00000001U)
1303 
1304 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPVSYNC_IRQ_VAL_NOPEND (0x0U)
1305 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPVSYNC_IRQ_VAL_PEND (0x1U)
1306 
1307 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPVSYNC_ODD_IRQ_MASK (0x00000004U)
1308 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPVSYNC_ODD_IRQ_SHIFT (0x00000002U)
1309 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPVSYNC_ODD_IRQ_MAX (0x00000001U)
1310 
1311 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPVSYNC_ODD_IRQ_VAL_NOPEND (0x0U)
1312 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPVSYNC_ODD_IRQ_VAL_PEND (0x1U)
1313 
1314 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPPROGRAMMEDLINENUMBER_IRQ_MASK (0x00000008U)
1315 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPPROGRAMMEDLINENUMBER_IRQ_SHIFT (0x00000003U)
1316 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPPROGRAMMEDLINENUMBER_IRQ_MAX (0x00000001U)
1317 
1318 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPPROGRAMMEDLINENUMBER_IRQ_VAL_NOPEND (0x0U)
1319 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPPROGRAMMEDLINENUMBER_IRQ_VAL_PEND (0x1U)
1320 
1321 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPSYNCLOST_IRQ_MASK (0x00000010U)
1322 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPSYNCLOST_IRQ_SHIFT (0x00000004U)
1323 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPSYNCLOST_IRQ_MAX (0x00000001U)
1324 
1325 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPSYNCLOST_IRQ_VAL_NOPEND (0x0U)
1326 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPSYNCLOST_IRQ_VAL_PEND (0x1U)
1327 
1328 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_ACBIASCOUNTSTATUS_IRQ_MASK (0x00000020U)
1329 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_ACBIASCOUNTSTATUS_IRQ_SHIFT (0x00000005U)
1330 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_ACBIASCOUNTSTATUS_IRQ_MAX (0x00000001U)
1331 
1332 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_ACBIASCOUNTSTATUS_IRQ_VAL_NOPEND (0x0U)
1333 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_ACBIASCOUNTSTATUS_IRQ_VAL_PEND (0x1U)
1334 
1335 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_SAFETYREGION_IRQ_MASK (0x000003C0U)
1336 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_SAFETYREGION_IRQ_SHIFT (0x00000006U)
1337 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_SAFETYREGION_IRQ_MAX (0x0000000FU)
1338 
1339 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
1340 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_SAFETYREGION_IRQ_VAL_PEND (0x1U)
1341 
1342 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_SECURITYVIOLATION_IRQ_MASK (0x00000400U)
1343 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_SECURITYVIOLATION_IRQ_SHIFT (0x0000000AU)
1344 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
1345 
1346 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
1347 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
1348 
1349 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPSYNC_IRQ_MASK (0x00000800U)
1350 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPSYNC_IRQ_SHIFT (0x0000000BU)
1351 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPSYNC_IRQ_MAX (0x00000001U)
1352 
1353 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPSYNC_IRQ_VAL_NOPEND (0x0U)
1354 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_VPSYNC_IRQ_VAL_PEND (0x1U)
1355 
1356 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_DUMMY_IRQ_MASK (0x00001000U)
1357 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_DUMMY_IRQ_SHIFT (0x0000000CU)
1358 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_DUMMY_IRQ_MAX (0x00000001U)
1359 
1360 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_DUMMY_IRQ_VAL_NOPEND (0x0U)
1361 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_DUMMY_IRQ_VAL_PEND (0x1U)
1362 
1363 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_SAFETYREGION1_IRQ_MASK (0x0001E000U)
1364 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_SAFETYREGION1_IRQ_SHIFT (0x0000000DU)
1365 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_SAFETYREGION1_IRQ_MAX (0x0000000FU)
1366 
1367 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_SAFETYREGION1_IRQ_VAL_NOPEND (0x0U)
1368 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_SAFETYREGION1_IRQ_VAL_PEND (0x1U)
1369 
1370 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_RESERVED_MASK (0xFFFE0000U)
1371 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_RESERVED_SHIFT (0x00000011U)
1372 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_2_RESERVED_MAX (0x00007FFFU)
1373 
1374 /* VP_IRQSTATUS_3 */
1375 
1376 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPFRAMEDONE_IRQ_MASK (0x00000001U)
1377 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPFRAMEDONE_IRQ_SHIFT (0x00000000U)
1378 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPFRAMEDONE_IRQ_MAX (0x00000001U)
1379 
1380 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
1381 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPFRAMEDONE_IRQ_VAL_PEND (0x1U)
1382 
1383 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPVSYNC_IRQ_MASK (0x00000002U)
1384 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPVSYNC_IRQ_SHIFT (0x00000001U)
1385 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPVSYNC_IRQ_MAX (0x00000001U)
1386 
1387 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPVSYNC_IRQ_VAL_NOPEND (0x0U)
1388 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPVSYNC_IRQ_VAL_PEND (0x1U)
1389 
1390 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPVSYNC_ODD_IRQ_MASK (0x00000004U)
1391 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPVSYNC_ODD_IRQ_SHIFT (0x00000002U)
1392 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPVSYNC_ODD_IRQ_MAX (0x00000001U)
1393 
1394 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPVSYNC_ODD_IRQ_VAL_NOPEND (0x0U)
1395 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPVSYNC_ODD_IRQ_VAL_PEND (0x1U)
1396 
1397 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPPROGRAMMEDLINENUMBER_IRQ_MASK (0x00000008U)
1398 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPPROGRAMMEDLINENUMBER_IRQ_SHIFT (0x00000003U)
1399 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPPROGRAMMEDLINENUMBER_IRQ_MAX (0x00000001U)
1400 
1401 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPPROGRAMMEDLINENUMBER_IRQ_VAL_NOPEND (0x0U)
1402 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPPROGRAMMEDLINENUMBER_IRQ_VAL_PEND (0x1U)
1403 
1404 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPSYNCLOST_IRQ_MASK (0x00000010U)
1405 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPSYNCLOST_IRQ_SHIFT (0x00000004U)
1406 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPSYNCLOST_IRQ_MAX (0x00000001U)
1407 
1408 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPSYNCLOST_IRQ_VAL_NOPEND (0x0U)
1409 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPSYNCLOST_IRQ_VAL_PEND (0x1U)
1410 
1411 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_ACBIASCOUNTSTATUS_IRQ_MASK (0x00000020U)
1412 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_ACBIASCOUNTSTATUS_IRQ_SHIFT (0x00000005U)
1413 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_ACBIASCOUNTSTATUS_IRQ_MAX (0x00000001U)
1414 
1415 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_ACBIASCOUNTSTATUS_IRQ_VAL_NOPEND (0x0U)
1416 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_ACBIASCOUNTSTATUS_IRQ_VAL_PEND (0x1U)
1417 
1418 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_SAFETYREGION_IRQ_MASK (0x000003C0U)
1419 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_SAFETYREGION_IRQ_SHIFT (0x00000006U)
1420 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_SAFETYREGION_IRQ_MAX (0x0000000FU)
1421 
1422 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
1423 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_SAFETYREGION_IRQ_VAL_PEND (0x1U)
1424 
1425 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_SECURITYVIOLATION_IRQ_MASK (0x00000400U)
1426 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_SECURITYVIOLATION_IRQ_SHIFT (0x0000000AU)
1427 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
1428 
1429 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
1430 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
1431 
1432 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPSYNC_IRQ_MASK (0x00000800U)
1433 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPSYNC_IRQ_SHIFT (0x0000000BU)
1434 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPSYNC_IRQ_MAX (0x00000001U)
1435 
1436 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPSYNC_IRQ_VAL_NOPEND (0x0U)
1437 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_VPSYNC_IRQ_VAL_PEND (0x1U)
1438 
1439 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_DUMMY_IRQ_MASK (0x00001000U)
1440 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_DUMMY_IRQ_SHIFT (0x0000000CU)
1441 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_DUMMY_IRQ_MAX (0x00000001U)
1442 
1443 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_DUMMY_IRQ_VAL_NOPEND (0x0U)
1444 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_DUMMY_IRQ_VAL_PEND (0x1U)
1445 
1446 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_SAFETYREGION1_IRQ_MASK (0x0001E000U)
1447 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_SAFETYREGION1_IRQ_SHIFT (0x0000000DU)
1448 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_SAFETYREGION1_IRQ_MAX (0x0000000FU)
1449 
1450 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_SAFETYREGION1_IRQ_VAL_NOPEND (0x0U)
1451 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_SAFETYREGION1_IRQ_VAL_PEND (0x1U)
1452 
1453 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_RESERVED_MASK (0xFFFE0000U)
1454 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_RESERVED_SHIFT (0x00000011U)
1455 #define CSL_DSS_COMMON_M_VP_IRQSTATUS_3_RESERVED_MAX (0x00007FFFU)
1456 
1457 /* WB_IRQENABLE */
1458 
1459 #define CSL_DSS_COMMON_M_WB_IRQENABLE_WBBUFFEROVERFLOW_EN_MASK (0x00000001U)
1460 #define CSL_DSS_COMMON_M_WB_IRQENABLE_WBBUFFEROVERFLOW_EN_SHIFT (0x00000000U)
1461 #define CSL_DSS_COMMON_M_WB_IRQENABLE_WBBUFFEROVERFLOW_EN_MAX (0x00000001U)
1462 
1463 #define CSL_DSS_COMMON_M_WB_IRQENABLE_WBBUFFEROVERFLOW_EN_VAL_MASKED (0x0U)
1464 #define CSL_DSS_COMMON_M_WB_IRQENABLE_WBBUFFEROVERFLOW_EN_VAL_GENINT (0x1U)
1465 
1466 #define CSL_DSS_COMMON_M_WB_IRQENABLE_WBUNCOMPLETEERROR_EN_MASK (0x00000002U)
1467 #define CSL_DSS_COMMON_M_WB_IRQENABLE_WBUNCOMPLETEERROR_EN_SHIFT (0x00000001U)
1468 #define CSL_DSS_COMMON_M_WB_IRQENABLE_WBUNCOMPLETEERROR_EN_MAX (0x00000001U)
1469 
1470 #define CSL_DSS_COMMON_M_WB_IRQENABLE_WBUNCOMPLETEERROR_EN_VAL_MASKED (0x0U)
1471 #define CSL_DSS_COMMON_M_WB_IRQENABLE_WBUNCOMPLETEERROR_EN_VAL_GENINT (0x1U)
1472 
1473 #define CSL_DSS_COMMON_M_WB_IRQENABLE_WBFRAMEDONE_EN_MASK (0x00000004U)
1474 #define CSL_DSS_COMMON_M_WB_IRQENABLE_WBFRAMEDONE_EN_SHIFT (0x00000002U)
1475 #define CSL_DSS_COMMON_M_WB_IRQENABLE_WBFRAMEDONE_EN_MAX (0x00000001U)
1476 
1477 #define CSL_DSS_COMMON_M_WB_IRQENABLE_WBFRAMEDONE_EN_VAL_MASKED (0x0U)
1478 #define CSL_DSS_COMMON_M_WB_IRQENABLE_WBFRAMEDONE_EN_VAL_GENINT (0x1U)
1479 
1480 #define CSL_DSS_COMMON_M_WB_IRQENABLE_SECURITYVIOLATION_EN_MASK (0x00000008U)
1481 #define CSL_DSS_COMMON_M_WB_IRQENABLE_SECURITYVIOLATION_EN_SHIFT (0x00000003U)
1482 #define CSL_DSS_COMMON_M_WB_IRQENABLE_SECURITYVIOLATION_EN_MAX (0x00000001U)
1483 
1484 #define CSL_DSS_COMMON_M_WB_IRQENABLE_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
1485 #define CSL_DSS_COMMON_M_WB_IRQENABLE_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
1486 
1487 #define CSL_DSS_COMMON_M_WB_IRQENABLE_WBSYNC_EN_MASK (0x00000010U)
1488 #define CSL_DSS_COMMON_M_WB_IRQENABLE_WBSYNC_EN_SHIFT (0x00000004U)
1489 #define CSL_DSS_COMMON_M_WB_IRQENABLE_WBSYNC_EN_MAX (0x00000001U)
1490 
1491 #define CSL_DSS_COMMON_M_WB_IRQENABLE_WBSYNC_EN_VAL_MASKED (0x0U)
1492 #define CSL_DSS_COMMON_M_WB_IRQENABLE_WBSYNC_EN_VAL_GENINT (0x1U)
1493 
1494 #define CSL_DSS_COMMON_M_WB_IRQENABLE_RESERVED_MASK (0xFFFFFFE0U)
1495 #define CSL_DSS_COMMON_M_WB_IRQENABLE_RESERVED_SHIFT (0x00000005U)
1496 #define CSL_DSS_COMMON_M_WB_IRQENABLE_RESERVED_MAX (0x07FFFFFFU)
1497 
1498 /* WB_IRQSTATUS */
1499 
1500 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_WBBUFFEROVERFLOW_IRQ_MASK (0x00000001U)
1501 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_WBBUFFEROVERFLOW_IRQ_SHIFT (0x00000000U)
1502 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_WBBUFFEROVERFLOW_IRQ_MAX (0x00000001U)
1503 
1504 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_WBBUFFEROVERFLOW_IRQ_VAL_NOPEND (0x0U)
1505 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_WBBUFFEROVERFLOW_IRQ_VAL_PEND (0x1U)
1506 
1507 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_WBUNCOMPLETEERROR_IRQ_MASK (0x00000002U)
1508 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_WBUNCOMPLETEERROR_IRQ_SHIFT (0x00000001U)
1509 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_WBUNCOMPLETEERROR_IRQ_MAX (0x00000001U)
1510 
1511 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_WBUNCOMPLETEERROR_IRQ_VAL_NOPEND (0x0U)
1512 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_WBUNCOMPLETEERROR_IRQ_VAL_PEND (0x1U)
1513 
1514 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_WBFRAMEDONE_IRQ_MASK (0x00000004U)
1515 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_WBFRAMEDONE_IRQ_SHIFT (0x00000002U)
1516 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_WBFRAMEDONE_IRQ_MAX (0x00000001U)
1517 
1518 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_WBFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
1519 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_WBFRAMEDONE_IRQ_VAL_PEND (0x1U)
1520 
1521 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_SECURITYVIOLATION_IRQ_MASK (0x00000008U)
1522 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_SECURITYVIOLATION_IRQ_SHIFT (0x00000003U)
1523 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
1524 
1525 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
1526 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
1527 
1528 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_WBSYNC_IRQ_MASK (0x00000010U)
1529 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_WBSYNC_IRQ_SHIFT (0x00000004U)
1530 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_WBSYNC_IRQ_MAX (0x00000001U)
1531 
1532 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_WBSYNC_IRQ_VAL_NOPEND (0x0U)
1533 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_WBSYNC_IRQ_VAL_PEND (0x1U)
1534 
1535 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_RESERVED_MASK (0xFFFFFFE0U)
1536 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_RESERVED_SHIFT (0x00000005U)
1537 #define CSL_DSS_COMMON_M_WB_IRQSTATUS_RESERVED_MAX (0x07FFFFFFU)
1538 
1539 /* DISPC_IRQ_EOI_FUNC */
1540 
1541 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_FUNC_EOI_MASK (0x00000001U)
1542 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_FUNC_EOI_SHIFT (0x00000000U)
1543 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_FUNC_EOI_MAX (0x00000001U)
1544 
1545 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_FUNC_EOI_VAL_NOACTION (0x0U)
1546 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_FUNC_EOI_VAL_EOI (0x1U)
1547 
1548 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_FUNC_RESERVED_MASK (0xFFFFFFFEU)
1549 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_FUNC_RESERVED_SHIFT (0x00000001U)
1550 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_FUNC_RESERVED_MAX (0x7FFFFFFFU)
1551 
1552 /* DISPC_IRQ_EOI_SAFETY */
1553 
1554 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_SAFETY_EOI_MASK (0x00000001U)
1555 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_SAFETY_EOI_SHIFT (0x00000000U)
1556 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_SAFETY_EOI_MAX (0x00000001U)
1557 
1558 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_SAFETY_EOI_VAL_NOACTION (0x0U)
1559 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_SAFETY_EOI_VAL_EOI (0x1U)
1560 
1561 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_SAFETY_RESERVED_MASK (0xFFFFFFFEU)
1562 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_SAFETY_RESERVED_SHIFT (0x00000001U)
1563 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_SAFETY_RESERVED_MAX (0x7FFFFFFFU)
1564 
1565 /* DISPC_IRQ_EOI_SECURITY */
1566 
1567 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_SECURITY_EOI_MASK (0x00000001U)
1568 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_SECURITY_EOI_SHIFT (0x00000000U)
1569 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_SECURITY_EOI_MAX (0x00000001U)
1570 
1571 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_SECURITY_EOI_VAL_NOACTION (0x0U)
1572 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_SECURITY_EOI_VAL_EOI (0x1U)
1573 
1574 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_SECURITY_RESERVED_MASK (0xFFFFFFFEU)
1575 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_SECURITY_RESERVED_SHIFT (0x00000001U)
1576 #define CSL_DSS_COMMON_M_DISPC_IRQ_EOI_SECURITY_RESERVED_MAX (0x7FFFFFFFU)
1577 
1578 /* DISPC_SECURE_DISABLE */
1579 
1580 #define CSL_DSS_COMMON_M_DISPC_SECURE_DISABLE_SECURE_DISABLE_MASK (0x00000001U)
1581 #define CSL_DSS_COMMON_M_DISPC_SECURE_DISABLE_SECURE_DISABLE_SHIFT (0x00000000U)
1582 #define CSL_DSS_COMMON_M_DISPC_SECURE_DISABLE_SECURE_DISABLE_MAX (0x00000001U)
1583 
1584 #define CSL_DSS_COMMON_M_DISPC_SECURE_DISABLE_SECURE_DISABLE_VAL_SECUREEN (0x0U)
1585 #define CSL_DSS_COMMON_M_DISPC_SECURE_DISABLE_SECURE_DISABLE_VAL_SECUREDIS (0x1U)
1586 
1587 #define CSL_DSS_COMMON_M_DISPC_SECURE_DISABLE_RESERVED_MASK (0xFFFFFFFEU)
1588 #define CSL_DSS_COMMON_M_DISPC_SECURE_DISABLE_RESERVED_SHIFT (0x00000001U)
1589 #define CSL_DSS_COMMON_M_DISPC_SECURE_DISABLE_RESERVED_MAX (0x7FFFFFFFU)
1590 
1591 /* DISPC_GLOBAL_MFLAG_ATTRIBUTE */
1592 
1593 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MASK (0x00000003U)
1594 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_SHIFT (0x00000000U)
1595 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MAX (0x00000003U)
1596 
1597 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_VAL_MFLAGDIS (0x0U)
1598 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_VAL_MFLAGFORCE (0x1U)
1599 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_VAL_MFLAGEN (0x2U)
1600 
1601 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED1_MASK (0x0000003CU)
1602 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED1_SHIFT (0x00000002U)
1603 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED1_MAX (0x0000000FU)
1604 
1605 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_MASK (0x00000040U)
1606 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_SHIFT (0x00000006U)
1607 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_MAX (0x00000001U)
1608 
1609 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_VAL_MFLAGNORMALSTARTMODE (0x0U)
1610 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_VAL_MFLAGFORCESTARTMODE (0x1U)
1611 
1612 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED2_MASK (0x00000180U)
1613 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED2_SHIFT (0x00000007U)
1614 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED2_MAX (0x00000003U)
1615 
1616 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED_MASK (0xFFFFFE00U)
1617 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED_SHIFT (0x00000009U)
1618 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED_MAX (0x007FFFFFU)
1619 
1620 /* DISPC_GLOBAL_OUTPUT_ENABLE */
1621 
1622 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_OUTPUT_ENABLE_VP_ENABLE_MASK (0x0000000FU)
1623 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_OUTPUT_ENABLE_VP_ENABLE_SHIFT (0x00000000U)
1624 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_OUTPUT_ENABLE_VP_ENABLE_MAX (0x0000000FU)
1625 
1626 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_OUTPUT_ENABLE_VP_ENABLE_VAL_DISABLE (0x0U)
1627 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_OUTPUT_ENABLE_VP_ENABLE_VAL_ENABLE (0x1U)
1628 
1629 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED1_MASK (0x0000FFF0U)
1630 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED1_SHIFT (0x00000004U)
1631 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED1_MAX (0x00000FFFU)
1632 
1633 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_OUTPUT_ENABLE_VP_GO_MASK (0x000F0000U)
1634 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_OUTPUT_ENABLE_VP_GO_SHIFT (0x00000010U)
1635 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_OUTPUT_ENABLE_VP_GO_MAX (0x0000000FU)
1636 
1637 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_OUTPUT_ENABLE_VP_GO_VAL_HFUISR (0x0U)
1638 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_OUTPUT_ENABLE_VP_GO_VAL_UFPSR (0x1U)
1639 
1640 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED2_MASK (0xFFF00000U)
1641 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED2_SHIFT (0x00000014U)
1642 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED2_MAX (0x00000FFFU)
1643 
1644 /* DISPC_GLOBAL_BUFFER */
1645 
1646 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VID1_BUFFER_MASK (0x00000007U)
1647 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VID1_BUFFER_SHIFT (0x00000000U)
1648 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VID1_BUFFER_MAX (0x00000007U)
1649 
1650 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VID1_BUFFER_VAL_VID1 (0x0U)
1651 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VID1_BUFFER_VAL_VIDL1 (0x1U)
1652 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VID1_BUFFER_VAL_VID2 (0x2U)
1653 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VID1_BUFFER_VAL_VIDL2 (0x3U)
1654 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VID1_BUFFER_VAL_WB (0x4U)
1655 
1656 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VIDL1_BUFFER_MASK (0x00000038U)
1657 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VIDL1_BUFFER_SHIFT (0x00000003U)
1658 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VIDL1_BUFFER_MAX (0x00000007U)
1659 
1660 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VIDL1_BUFFER_VAL_VID1 (0x0U)
1661 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VIDL1_BUFFER_VAL_VIDL1 (0x1U)
1662 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VIDL1_BUFFER_VAL_VID2 (0x2U)
1663 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VIDL1_BUFFER_VAL_VIDL2 (0x3U)
1664 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VIDL1_BUFFER_VAL_WB (0x4U)
1665 
1666 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VID2_BUFFER_MASK (0x000001C0U)
1667 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VID2_BUFFER_SHIFT (0x00000006U)
1668 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VID2_BUFFER_MAX (0x00000007U)
1669 
1670 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VID2_BUFFER_VAL_VID1 (0x0U)
1671 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VID2_BUFFER_VAL_VIDL1 (0x1U)
1672 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VID2_BUFFER_VAL_VID2 (0x2U)
1673 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VID2_BUFFER_VAL_VIDL2 (0x3U)
1674 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VID2_BUFFER_VAL_WB (0x4U)
1675 
1676 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VIDL2_BUFFER_MASK (0x00000E00U)
1677 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VIDL2_BUFFER_SHIFT (0x00000009U)
1678 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VIDL2_BUFFER_MAX (0x00000007U)
1679 
1680 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VIDL2_BUFFER_VAL_VID1 (0x0U)
1681 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VIDL2_BUFFER_VAL_VIDL1 (0x1U)
1682 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VIDL2_BUFFER_VAL_VID2 (0x2U)
1683 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VIDL2_BUFFER_VAL_VIDL2 (0x3U)
1684 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_VIDL2_BUFFER_VAL_WB (0x4U)
1685 
1686 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_WB_BUFFER_MASK (0x00007000U)
1687 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_WB_BUFFER_SHIFT (0x0000000CU)
1688 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_WB_BUFFER_MAX (0x00000007U)
1689 
1690 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_WB_BUFFER_VAL_VID1 (0x0U)
1691 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_WB_BUFFER_VAL_VIDL1 (0x1U)
1692 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_WB_BUFFER_VAL_VID2 (0x2U)
1693 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_WB_BUFFER_VAL_VIDL2 (0x3U)
1694 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_WB_BUFFER_VAL_WB (0x4U)
1695 
1696 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_RESERVED_MASK (0x1FFF8000U)
1697 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_RESERVED_SHIFT (0x0000000FU)
1698 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_RESERVED_MAX (0x00003FFFU)
1699 
1700 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_RESERVED1_MASK (0x20000000U)
1701 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_RESERVED1_SHIFT (0x0000001DU)
1702 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_RESERVED1_MAX (0x00000001U)
1703 
1704 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_SHAREDBUFENABLE_MASK (0x40000000U)
1705 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_SHAREDBUFENABLE_SHIFT (0x0000001EU)
1706 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_SHAREDBUFENABLE_MAX (0x00000001U)
1707 
1708 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_SHAREDBUFENABLE_VAL_DISABLE (0x0U)
1709 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_SHAREDBUFENABLE_VAL_ENABLE (0x1U)
1710 
1711 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_BUFFERFILLING_MASK (0x80000000U)
1712 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_BUFFERFILLING_SHIFT (0x0000001FU)
1713 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_BUFFERFILLING_MAX (0x00000001U)
1714 
1715 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_BUFFERFILLING_VAL_INDIVIDUALPIPE (0x0U)
1716 #define CSL_DSS_COMMON_M_DISPC_GLOBAL_BUFFER_BUFFERFILLING_VAL_ALLPIPES (0x1U)
1717 
1718 /* DSS_CBA_CFG */
1719 
1720 #define CSL_DSS_COMMON_M_DSS_CBA_CFG_PRI_LO_MASK (0x00000007U)
1721 #define CSL_DSS_COMMON_M_DSS_CBA_CFG_PRI_LO_SHIFT (0x00000000U)
1722 #define CSL_DSS_COMMON_M_DSS_CBA_CFG_PRI_LO_MAX (0x00000007U)
1723 
1724 #define CSL_DSS_COMMON_M_DSS_CBA_CFG_PRI_HI_MASK (0x00000038U)
1725 #define CSL_DSS_COMMON_M_DSS_CBA_CFG_PRI_HI_SHIFT (0x00000003U)
1726 #define CSL_DSS_COMMON_M_DSS_CBA_CFG_PRI_HI_MAX (0x00000007U)
1727 
1728 #define CSL_DSS_COMMON_M_DSS_CBA_CFG_DMA_BACKLOGSTATUS_DISABLE_MASK (0x00000040U)
1729 #define CSL_DSS_COMMON_M_DSS_CBA_CFG_DMA_BACKLOGSTATUS_DISABLE_SHIFT (0x00000006U)
1730 #define CSL_DSS_COMMON_M_DSS_CBA_CFG_DMA_BACKLOGSTATUS_DISABLE_MAX (0x00000001U)
1731 
1732 #define CSL_DSS_COMMON_M_DSS_CBA_CFG_DMA_BACKLOGSTATUS_DISABLE_VAL_MASK (0x00000180U)
1733 #define CSL_DSS_COMMON_M_DSS_CBA_CFG_DMA_BACKLOGSTATUS_DISABLE_VAL_SHIFT (0x00000007U)
1734 #define CSL_DSS_COMMON_M_DSS_CBA_CFG_DMA_BACKLOGSTATUS_DISABLE_VAL_MAX (0x00000003U)
1735 
1736 #define CSL_DSS_COMMON_M_DSS_CBA_CFG_RESERVED_MASK (0xFFFFFE00U)
1737 #define CSL_DSS_COMMON_M_DSS_CBA_CFG_RESERVED_SHIFT (0x00000009U)
1738 #define CSL_DSS_COMMON_M_DSS_CBA_CFG_RESERVED_MAX (0x007FFFFFU)
1739 
1740 /* DISPC_DBG_CONTROL */
1741 
1742 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL_DBGEN_MASK (0x00000001U)
1743 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL_DBGEN_SHIFT (0x00000000U)
1744 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL_DBGEN_MAX (0x00000001U)
1745 
1746 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL_DBGEN_VAL_DBGDIS (0x0U)
1747 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL_DBGEN_VAL_DBGEN (0x1U)
1748 
1749 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL_DBGMUXSEL_MASK (0x000001FEU)
1750 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL_DBGMUXSEL_SHIFT (0x00000001U)
1751 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL_DBGMUXSEL_MAX (0x000000FFU)
1752 
1753 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_VID1SEL (0x0U)
1754 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_VIDL1SEL (0x8U)
1755 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_VID2SEL (0x10U)
1756 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_VIDL2SEL (0x18U)
1757 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_WBSEL (0x20U)
1758 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_OVR1SEL (0x21U)
1759 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_OVR2SEL (0x22U)
1760 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_OVR3SEL (0x23U)
1761 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_OVR4SEL (0x24U)
1762 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_VP1SEL (0x25U)
1763 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_VP2SEL (0x27U)
1764 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_VP3SEL (0x29U)
1765 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_VP4SEL (0x2BU)
1766 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_MISCSEL (0x2DU)
1767 
1768 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL_RESERVED_MASK (0xFFFFFE00U)
1769 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL_RESERVED_SHIFT (0x00000009U)
1770 #define CSL_DSS_COMMON_M_DISPC_DBG_CONTROL_RESERVED_MAX (0x007FFFFFU)
1771 
1772 /* DISPC_DBG_STATUS */
1773 
1774 #define CSL_DSS_COMMON_M_DISPC_DBG_STATUS_DBGOUT_MASK (0xFFFFFFFFU)
1775 #define CSL_DSS_COMMON_M_DISPC_DBG_STATUS_DBGOUT_SHIFT (0x00000000U)
1776 #define CSL_DSS_COMMON_M_DISPC_DBG_STATUS_DBGOUT_MAX (0xFFFFFFFFU)
1777 
1778 /* DISPC_CLKGATING_DISABLE */
1779 
1780 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_DMA_MASK (0x00000001U)
1781 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_DMA_SHIFT (0x00000000U)
1782 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_DMA_MAX (0x00000001U)
1783 
1784 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_DMA_VAL_CLKGATINGEN (0x0U)
1785 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_DMA_VAL_CLKGATINGDIS (0x1U)
1786 
1787 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_RESERVED1_MASK (0x00000006U)
1788 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_RESERVED1_SHIFT (0x00000001U)
1789 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_RESERVED1_MAX (0x00000003U)
1790 
1791 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_VID_MASK (0x00000078U)
1792 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_VID_SHIFT (0x00000003U)
1793 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_VID_MAX (0x0000000FU)
1794 
1795 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_VID_VAL_CLKGATINGEN (0x0U)
1796 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_VID_VAL_CLKGATINGDIS (0x1U)
1797 
1798 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_RESERVED2_MASK (0x00000F80U)
1799 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_RESERVED2_SHIFT (0x00000007U)
1800 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_RESERVED2_MAX (0x0000001FU)
1801 
1802 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_RESERVED3_MASK (0x00001000U)
1803 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_RESERVED3_SHIFT (0x0000000CU)
1804 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_RESERVED3_MAX (0x00000001U)
1805 
1806 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_WB_MASK (0x00002000U)
1807 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_WB_SHIFT (0x0000000DU)
1808 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_WB_MAX (0x00000001U)
1809 
1810 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_WB_VAL_CLKGATINGEN (0x0U)
1811 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_WB_VAL_CLKGATINGDIS (0x1U)
1812 
1813 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_OVR_MASK (0x0003C000U)
1814 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_OVR_SHIFT (0x0000000EU)
1815 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_OVR_MAX (0x0000000FU)
1816 
1817 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_OVR_VAL_CLKGATINGEN (0x0U)
1818 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_OVR_VAL_CLKGATINGDIS (0x1U)
1819 
1820 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_VP_MASK (0x003C0000U)
1821 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_VP_SHIFT (0x00000012U)
1822 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_VP_MAX (0x0000000FU)
1823 
1824 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_VP_VAL_CLKGATINGEN (0x0U)
1825 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_VP_VAL_CLKGATINGDIS (0x1U)
1826 
1827 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_RESERVED_MASK (0xFFC00000U)
1828 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_RESERVED_SHIFT (0x00000016U)
1829 #define CSL_DSS_COMMON_M_DISPC_CLKGATING_DISABLE_RESERVED_MAX (0x000003FFU)
1830 
1831 /* FBDC_REVISION_1 */
1832 
1833 #define CSL_DSS_COMMON_M_FBDC_REVISION_1_PRODUCTCODE_MASK (0x0000FFFFU)
1834 #define CSL_DSS_COMMON_M_FBDC_REVISION_1_PRODUCTCODE_SHIFT (0x00000000U)
1835 #define CSL_DSS_COMMON_M_FBDC_REVISION_1_PRODUCTCODE_MAX (0x0000FFFFU)
1836 
1837 #define CSL_DSS_COMMON_M_FBDC_REVISION_1_RESERVED_MASK (0xFFFF0000U)
1838 #define CSL_DSS_COMMON_M_FBDC_REVISION_1_RESERVED_SHIFT (0x00000010U)
1839 #define CSL_DSS_COMMON_M_FBDC_REVISION_1_RESERVED_MAX (0x0000FFFFU)
1840 
1841 /* FBDC_REVISION_2 */
1842 
1843 #define CSL_DSS_COMMON_M_FBDC_REVISION_2_BRANCHCODE_MASK (0x0000FFFFU)
1844 #define CSL_DSS_COMMON_M_FBDC_REVISION_2_BRANCHCODE_SHIFT (0x00000000U)
1845 #define CSL_DSS_COMMON_M_FBDC_REVISION_2_BRANCHCODE_MAX (0x0000FFFFU)
1846 
1847 #define CSL_DSS_COMMON_M_FBDC_REVISION_2_RESERVED_MASK (0xFFFF0000U)
1848 #define CSL_DSS_COMMON_M_FBDC_REVISION_2_RESERVED_SHIFT (0x00000010U)
1849 #define CSL_DSS_COMMON_M_FBDC_REVISION_2_RESERVED_MAX (0x0000FFFFU)
1850 
1851 /* FBDC_REVISION_3 */
1852 
1853 #define CSL_DSS_COMMON_M_FBDC_REVISION_3_VERSIONCODE_MASK (0x0000FFFFU)
1854 #define CSL_DSS_COMMON_M_FBDC_REVISION_3_VERSIONCODE_SHIFT (0x00000000U)
1855 #define CSL_DSS_COMMON_M_FBDC_REVISION_3_VERSIONCODE_MAX (0x0000FFFFU)
1856 
1857 #define CSL_DSS_COMMON_M_FBDC_REVISION_3_RESERVED_MASK (0xFFFF0000U)
1858 #define CSL_DSS_COMMON_M_FBDC_REVISION_3_RESERVED_SHIFT (0x00000010U)
1859 #define CSL_DSS_COMMON_M_FBDC_REVISION_3_RESERVED_MAX (0x0000FFFFU)
1860 
1861 /* FBDC_REVISION_4 */
1862 
1863 #define CSL_DSS_COMMON_M_FBDC_REVISION_4_CORECODE_MASK (0x0000FFFFU)
1864 #define CSL_DSS_COMMON_M_FBDC_REVISION_4_CORECODE_SHIFT (0x00000000U)
1865 #define CSL_DSS_COMMON_M_FBDC_REVISION_4_CORECODE_MAX (0x0000FFFFU)
1866 
1867 #define CSL_DSS_COMMON_M_FBDC_REVISION_4_RESERVED_MASK (0xFFFF0000U)
1868 #define CSL_DSS_COMMON_M_FBDC_REVISION_4_RESERVED_SHIFT (0x00000010U)
1869 #define CSL_DSS_COMMON_M_FBDC_REVISION_4_RESERVED_MAX (0x0000FFFFU)
1870 
1871 /* FBDC_REVISION_5 */
1872 
1873 #define CSL_DSS_COMMON_M_FBDC_REVISION_5_CONFIGCODE_MASK (0x0000FFFFU)
1874 #define CSL_DSS_COMMON_M_FBDC_REVISION_5_CONFIGCODE_SHIFT (0x00000000U)
1875 #define CSL_DSS_COMMON_M_FBDC_REVISION_5_CONFIGCODE_MAX (0x0000FFFFU)
1876 
1877 #define CSL_DSS_COMMON_M_FBDC_REVISION_5_RESERVED_MASK (0xFFFF0000U)
1878 #define CSL_DSS_COMMON_M_FBDC_REVISION_5_RESERVED_SHIFT (0x00000010U)
1879 #define CSL_DSS_COMMON_M_FBDC_REVISION_5_RESERVED_MAX (0x0000FFFFU)
1880 
1881 /* FBDC_REVISION_6 */
1882 
1883 #define CSL_DSS_COMMON_M_FBDC_REVISION_6_CHANGELISTCODE_MASK (0xFFFFFFFFU)
1884 #define CSL_DSS_COMMON_M_FBDC_REVISION_6_CHANGELISTCODE_SHIFT (0x00000000U)
1885 #define CSL_DSS_COMMON_M_FBDC_REVISION_6_CHANGELISTCODE_MAX (0xFFFFFFFFU)
1886 
1887 /* FBDC_COMMON_CONTROL */
1888 
1889 #define CSL_DSS_COMMON_M_FBDC_COMMON_CONTROL_IDLEGATE_MASK (0x00000001U)
1890 #define CSL_DSS_COMMON_M_FBDC_COMMON_CONTROL_IDLEGATE_SHIFT (0x00000000U)
1891 #define CSL_DSS_COMMON_M_FBDC_COMMON_CONTROL_IDLEGATE_MAX (0x00000001U)
1892 
1893 #define CSL_DSS_COMMON_M_FBDC_COMMON_CONTROL_CLKGATE_MASK (0x00000002U)
1894 #define CSL_DSS_COMMON_M_FBDC_COMMON_CONTROL_CLKGATE_SHIFT (0x00000001U)
1895 #define CSL_DSS_COMMON_M_FBDC_COMMON_CONTROL_CLKGATE_MAX (0x00000001U)
1896 
1897 #define CSL_DSS_COMMON_M_FBDC_COMMON_CONTROL_GPUTYPE_MASK (0x00000004U)
1898 #define CSL_DSS_COMMON_M_FBDC_COMMON_CONTROL_GPUTYPE_SHIFT (0x00000002U)
1899 #define CSL_DSS_COMMON_M_FBDC_COMMON_CONTROL_GPUTYPE_MAX (0x00000001U)
1900 
1901 #define CSL_DSS_COMMON_M_FBDC_COMMON_CONTROL_GPUTYPE_VAL_8XE (0x0U)
1902 #define CSL_DSS_COMMON_M_FBDC_COMMON_CONTROL_GPUTYPE_VAL_8XT (0x1U)
1903 
1904 /* FBDC_CONSTANT_COLOR_0 */
1905 
1906 #define CSL_DSS_COMMON_M_FBDC_CONSTANT_COLOR_0_CONSTCOLOR_MASK (0xFFFFFFFFU)
1907 #define CSL_DSS_COMMON_M_FBDC_CONSTANT_COLOR_0_CONSTCOLOR_SHIFT (0x00000000U)
1908 #define CSL_DSS_COMMON_M_FBDC_CONSTANT_COLOR_0_CONSTCOLOR_MAX (0xFFFFFFFFU)
1909 
1910 /* FBDC_CONSTANT_COLOR_1 */
1911 
1912 #define CSL_DSS_COMMON_M_FBDC_CONSTANT_COLOR_1_CONSTCOLOR_MASK (0xFFFFFFFFU)
1913 #define CSL_DSS_COMMON_M_FBDC_CONSTANT_COLOR_1_CONSTCOLOR_SHIFT (0x00000000U)
1914 #define CSL_DSS_COMMON_M_FBDC_CONSTANT_COLOR_1_CONSTCOLOR_MAX (0xFFFFFFFFU)
1915 
1916 /* DISPC_CONNECTIONS */
1917 
1918 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_DPI_0_CONN_MASK (0x0000000FU)
1919 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_DPI_0_CONN_SHIFT (0x00000000U)
1920 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_DPI_0_CONN_MAX (0x0000000FU)
1921 
1922 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_DPI_0_CONN_VAL_NULL (0x0U)
1923 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_DPI_0_CONN_VAL_VP1 (0x1U)
1924 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_DPI_0_CONN_VAL_VP2 (0x2U)
1925 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_DPI_0_CONN_VAL_VP3 (0x4U)
1926 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_DPI_0_CONN_VAL_VP4 (0x8U)
1927 
1928 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_DPI_1_CONN_MASK (0x000000F0U)
1929 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_DPI_1_CONN_SHIFT (0x00000004U)
1930 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_DPI_1_CONN_MAX (0x0000000FU)
1931 
1932 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_DPI_1_CONN_VAL_NULL (0x0U)
1933 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_DPI_1_CONN_VAL_VP1 (0x1U)
1934 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_DPI_1_CONN_VAL_VP2 (0x2U)
1935 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_DPI_1_CONN_VAL_VP3 (0x4U)
1936 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_DPI_1_CONN_VAL_VP4 (0x8U)
1937 
1938 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_WB_CONN_MASK (0x001F0000U)
1939 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_WB_CONN_SHIFT (0x00000010U)
1940 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_WB_CONN_MAX (0x0000001FU)
1941 
1942 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_WB_CONN_VAL_NULL (0x0U)
1943 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_WB_CONN_VAL_VIDL2 (0x1U)
1944 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_WB_CONN_VAL_OVR1 (0x2U)
1945 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_WB_CONN_VAL_OVR2 (0x4U)
1946 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_WB_CONN_VAL_OVR3 (0x8U)
1947 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_WB_CONN_VAL_OVR4 (0x10U)
1948 
1949 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_VIRTUALVP_CONN_MASK (0x0F000000U)
1950 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_VIRTUALVP_CONN_SHIFT (0x00000018U)
1951 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_VIRTUALVP_CONN_MAX (0x0000000FU)
1952 
1953 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_VIRTUALVP_CONN_VAL_NULL (0x0U)
1954 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_VIRTUALVP_CONN_VAL_VP1 (0x1U)
1955 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_VIRTUALVP_CONN_VAL_VP2 (0x2U)
1956 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_VIRTUALVP_CONN_VAL_VP3 (0x4U)
1957 #define CSL_DSS_COMMON_M_DISPC_CONNECTIONS_VIRTUALVP_CONN_VAL_VP4 (0x8U)
1958 
1959 /* DISPC_MSS_VP1 */
1960 
1961 #define CSL_DSS_COMMON_M_DISPC_MSS_VP1_MSSENABLE_MASK (0x00000001U)
1962 #define CSL_DSS_COMMON_M_DISPC_MSS_VP1_MSSENABLE_SHIFT (0x00000000U)
1963 #define CSL_DSS_COMMON_M_DISPC_MSS_VP1_MSSENABLE_MAX (0x00000001U)
1964 
1965 #define CSL_DSS_COMMON_M_DISPC_MSS_VP1_MSSENABLE_VAL_MSSBYPASS (0x0U)
1966 #define CSL_DSS_COMMON_M_DISPC_MSS_VP1_MSSENABLE_VAL_MSSENABLE (0x1U)
1967 
1968 #define CSL_DSS_COMMON_M_DISPC_MSS_VP1_MSSTYPE_MASK (0x00000006U)
1969 #define CSL_DSS_COMMON_M_DISPC_MSS_VP1_MSSTYPE_SHIFT (0x00000001U)
1970 #define CSL_DSS_COMMON_M_DISPC_MSS_VP1_MSSTYPE_MAX (0x00000003U)
1971 
1972 #define CSL_DSS_COMMON_M_DISPC_MSS_VP1_MSSTYPE_VAL_MERGEENB (0x0U)
1973 #define CSL_DSS_COMMON_M_DISPC_MSS_VP1_MSSTYPE_VAL_SPLITENB (0x1U)
1974 #define CSL_DSS_COMMON_M_DISPC_MSS_VP1_MSSTYPE_VAL_SYNCENB (0x2U)
1975 
1976 #define CSL_DSS_COMMON_M_DISPC_MSS_VP1_MSSFORMAT_MASK (0x00000008U)
1977 #define CSL_DSS_COMMON_M_DISPC_MSS_VP1_MSSFORMAT_SHIFT (0x00000003U)
1978 #define CSL_DSS_COMMON_M_DISPC_MSS_VP1_MSSFORMAT_MAX (0x00000001U)
1979 
1980 #define CSL_DSS_COMMON_M_DISPC_MSS_VP1_MSSFORMAT_VAL_OE (0x1U)
1981 #define CSL_DSS_COMMON_M_DISPC_MSS_VP1_MSSFORMAT_VAL_LR (0x0U)
1982 
1983 #define CSL_DSS_COMMON_M_DISPC_MSS_VP1_RESERVED_MASK (0xFFFFFFF0U)
1984 #define CSL_DSS_COMMON_M_DISPC_MSS_VP1_RESERVED_SHIFT (0x00000004U)
1985 #define CSL_DSS_COMMON_M_DISPC_MSS_VP1_RESERVED_MAX (0x0FFFFFFFU)
1986 
1987 /* DISPC_MSS_VP3 */
1988 
1989 #define CSL_DSS_COMMON_M_DISPC_MSS_VP3_MSSENABLE_MASK (0x00000001U)
1990 #define CSL_DSS_COMMON_M_DISPC_MSS_VP3_MSSENABLE_SHIFT (0x00000000U)
1991 #define CSL_DSS_COMMON_M_DISPC_MSS_VP3_MSSENABLE_MAX (0x00000001U)
1992 
1993 #define CSL_DSS_COMMON_M_DISPC_MSS_VP3_MSSENABLE_VAL_MSSBYPASS (0x0U)
1994 #define CSL_DSS_COMMON_M_DISPC_MSS_VP3_MSSENABLE_VAL_MSSENABLE (0x1U)
1995 
1996 #define CSL_DSS_COMMON_M_DISPC_MSS_VP3_MSSTYPE_MASK (0x00000006U)
1997 #define CSL_DSS_COMMON_M_DISPC_MSS_VP3_MSSTYPE_SHIFT (0x00000001U)
1998 #define CSL_DSS_COMMON_M_DISPC_MSS_VP3_MSSTYPE_MAX (0x00000003U)
1999 
2000 #define CSL_DSS_COMMON_M_DISPC_MSS_VP3_MSSTYPE_VAL_MERGEENB (0x0U)
2001 #define CSL_DSS_COMMON_M_DISPC_MSS_VP3_MSSTYPE_VAL_SPLITENB (0x1U)
2002 #define CSL_DSS_COMMON_M_DISPC_MSS_VP3_MSSTYPE_VAL_SYNCENB (0x2U)
2003 
2004 #define CSL_DSS_COMMON_M_DISPC_MSS_VP3_MSSFORMAT_MASK (0x00000008U)
2005 #define CSL_DSS_COMMON_M_DISPC_MSS_VP3_MSSFORMAT_SHIFT (0x00000003U)
2006 #define CSL_DSS_COMMON_M_DISPC_MSS_VP3_MSSFORMAT_MAX (0x00000001U)
2007 
2008 #define CSL_DSS_COMMON_M_DISPC_MSS_VP3_MSSFORMAT_VAL_OE (0x0U)
2009 #define CSL_DSS_COMMON_M_DISPC_MSS_VP3_MSSFORMAT_VAL_LR (0x1U)
2010 
2011 #define CSL_DSS_COMMON_M_DISPC_MSS_VP3_RESERVED_MASK (0xFFFFFFF0U)
2012 #define CSL_DSS_COMMON_M_DISPC_MSS_VP3_RESERVED_SHIFT (0x00000004U)
2013 #define CSL_DSS_COMMON_M_DISPC_MSS_VP3_RESERVED_MAX (0x0FFFFFFFU)
2014 
2015 /* GLOBAL_DMA_THREADSIZE */
2016 
2017 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZE_VP0THREADSIZE_MASK (0x0000001FU)
2018 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZE_VP0THREADSIZE_SHIFT (0x00000000U)
2019 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZE_VP0THREADSIZE_MAX (0x0000001FU)
2020 
2021 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZE_VP1THREADSIZE_MASK (0x000003E0U)
2022 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZE_VP1THREADSIZE_SHIFT (0x00000005U)
2023 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZE_VP1THREADSIZE_MAX (0x0000001FU)
2024 
2025 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZE_VP2THREADSIZE_MASK (0x00007C00U)
2026 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZE_VP2THREADSIZE_SHIFT (0x0000000AU)
2027 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZE_VP2THREADSIZE_MAX (0x0000001FU)
2028 
2029 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZE_VP3THREADSIZE_MASK (0x000F8000U)
2030 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZE_VP3THREADSIZE_SHIFT (0x0000000FU)
2031 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZE_VP3THREADSIZE_MAX (0x0000001FU)
2032 
2033 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZE_WBTHREADSIZE_MASK (0x01F00000U)
2034 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZE_WBTHREADSIZE_SHIFT (0x00000014U)
2035 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZE_WBTHREADSIZE_MAX (0x0000001FU)
2036 
2037 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZE_RESERVED_MASK (0xFE000000U)
2038 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZE_RESERVED_SHIFT (0x00000019U)
2039 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZE_RESERVED_MAX (0x0000007FU)
2040 
2041 /* GLOBAL_DMA_THREADSIZESTATUS */
2042 
2043 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZESTATUS_VP0THREADSIZE_MASK (0x0000001FU)
2044 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZESTATUS_VP0THREADSIZE_SHIFT (0x00000000U)
2045 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZESTATUS_VP0THREADSIZE_MAX (0x0000001FU)
2046 
2047 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZESTATUS_VP1THREADSIZE_MASK (0x000003E0U)
2048 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZESTATUS_VP1THREADSIZE_SHIFT (0x00000005U)
2049 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZESTATUS_VP1THREADSIZE_MAX (0x0000001FU)
2050 
2051 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZESTATUS_VP2THREADSIZE_MASK (0x00007C00U)
2052 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZESTATUS_VP2THREADSIZE_SHIFT (0x0000000AU)
2053 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZESTATUS_VP2THREADSIZE_MAX (0x0000001FU)
2054 
2055 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZESTATUS_VP3THREADSIZE_MASK (0x000F8000U)
2056 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZESTATUS_VP3THREADSIZE_SHIFT (0x0000000FU)
2057 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZESTATUS_VP3THREADSIZE_MAX (0x0000001FU)
2058 
2059 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZESTATUS_WBTHREADSIZE_MASK (0x01F00000U)
2060 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZESTATUS_WBTHREADSIZE_SHIFT (0x00000014U)
2061 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZESTATUS_WBTHREADSIZE_MAX (0x0000001FU)
2062 
2063 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZESTATUS_RESERVED_MASK (0xFE000000U)
2064 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZESTATUS_RESERVED_SHIFT (0x00000019U)
2065 #define CSL_DSS_COMMON_M_GLOBAL_DMA_THREADSIZESTATUS_RESERVED_MAX (0x0000007FU)
2066 
2067 /* GLOBAL_GOBITMODE */
2068 
2069 #define CSL_DSS_COMMON_M_GLOBAL_GOBITMODE_MODE_MASK (0x00000001U)
2070 #define CSL_DSS_COMMON_M_GLOBAL_GOBITMODE_MODE_SHIFT (0x00000000U)
2071 #define CSL_DSS_COMMON_M_GLOBAL_GOBITMODE_MODE_MAX (0x00000001U)
2072 
2073 #define CSL_DSS_COMMON_M_GLOBAL_GOBITMODE_MODE_VAL_PIPEGODIS (0x0U)
2074 #define CSL_DSS_COMMON_M_GLOBAL_GOBITMODE_MODE_VAL_PIPEGOEN (0x1U)
2075 
2076 #define CSL_DSS_COMMON_M_GLOBAL_GOBITMODE_RESERVED_MASK (0xFFFFFFFEU)
2077 #define CSL_DSS_COMMON_M_GLOBAL_GOBITMODE_RESERVED_SHIFT (0x00000001U)
2078 #define CSL_DSS_COMMON_M_GLOBAL_GOBITMODE_RESERVED_MAX (0x7FFFFFFFU)
2079 
2080 /**************************************************************************
2081 * Hardware Region : COMMON_S0 Registers
2082 **************************************************************************/
2083 
2084 
2085 /**************************************************************************
2086 * Register Overlay Structure
2087 **************************************************************************/
2088 
2089 typedef struct {
2090  volatile uint8_t Resv_40[40];
2091  volatile uint32_t DISPC_IRQSTATUS_RAW; /* DISPC_IRQSTATUS_RAW */
2092  volatile uint32_t DISPC_IRQSTATUS; /* DISPC_IRQSTATUS */
2093  volatile uint32_t DISPC_IRQENABLE_SET; /* DISPC_IRQENABLE_SET */
2094  volatile uint32_t DISPC_IRQENABLE_CLR; /* DISPC_IRQENABLE_CLR */
2095  volatile uint32_t VID_IRQENABLE_0; /* VID_IRQENABLE_0 */
2096  volatile uint32_t VID_IRQENABLE_1; /* VID_IRQENABLE_1 */
2097  volatile uint32_t VID_IRQENABLE_2; /* VID_IRQENABLE_2 */
2098  volatile uint32_t VID_IRQENABLE_3; /* VID_IRQENABLE_3 */
2099  volatile uint32_t VID_IRQSTATUS_0; /* VID_IRQSTATUS_0 */
2100  volatile uint32_t VID_IRQSTATUS_1; /* VID_IRQSTATUS_1 */
2101  volatile uint32_t VID_IRQSTATUS_2; /* VID_IRQSTATUS_2 */
2102  volatile uint32_t VID_IRQSTATUS_3; /* VID_IRQSTATUS_3 */
2103  volatile uint32_t VP_IRQENABLE_0; /* VP_IRQENABLE_0 */
2104  volatile uint32_t VP_IRQENABLE_1; /* VP_IRQENABLE_1 */
2105  volatile uint32_t VP_IRQENABLE_2; /* VP_IRQENABLE_2 */
2106  volatile uint32_t VP_IRQENABLE_3; /* VP_IRQENABLE_3 */
2107  volatile uint32_t VP_IRQSTATUS_0; /* VP_IRQSTATUS_0 */
2108  volatile uint32_t VP_IRQSTATUS_1; /* VP_IRQSTATUS_1 */
2109  volatile uint32_t VP_IRQSTATUS_2; /* VP_IRQSTATUS_2 */
2110  volatile uint32_t VP_IRQSTATUS_3; /* VP_IRQSTATUS_3 */
2111  volatile uint32_t WB_IRQENABLE; /* WB_IRQENABLE */
2112  volatile uint32_t WB_IRQSTATUS; /* WB_IRQSTATUS */
2113  volatile uint32_t DISPC_IRQ_EOI_FUNC; /* DISPC_IRQ_EOI_FUNC */
2114  volatile uint32_t DISPC_IRQ_EOI_SAFETY; /* DISPC_IRQ_EOI_SAFETY */
2115  volatile uint32_t DISPC_IRQ_EOI_SECURITY; /* DISPC_IRQ_EOI_SECURITY */
2117 
2118 
2119 /**************************************************************************
2120 * Register Macros
2121 **************************************************************************/
2122 
2123 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW (0x00000028U)
2124 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS (0x0000002CU)
2125 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET (0x00000030U)
2126 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR (0x00000034U)
2127 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0 (0x00000038U)
2128 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1 (0x0000003CU)
2129 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2 (0x00000040U)
2130 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3 (0x00000044U)
2131 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0 (0x00000048U)
2132 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1 (0x0000004CU)
2133 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2 (0x00000050U)
2134 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3 (0x00000054U)
2135 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0 (0x00000058U)
2136 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1 (0x0000005CU)
2137 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2 (0x00000060U)
2138 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3 (0x00000064U)
2139 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0 (0x00000068U)
2140 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1 (0x0000006CU)
2141 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2 (0x00000070U)
2142 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3 (0x00000074U)
2143 #define CSL_DSS_COMMON_S0_WB_IRQENABLE (0x00000078U)
2144 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS (0x0000007CU)
2145 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_FUNC (0x00000080U)
2146 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_SAFETY (0x00000084U)
2147 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_SECURITY (0x00000088U)
2148 
2149 /**************************************************************************
2150 * Field Definition Macros
2151 **************************************************************************/
2152 
2153 
2154 /* DISPC_IRQSTATUS_RAW */
2155 
2156 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_VP_IRQ_MASK (0x0000000FU)
2157 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_VP_IRQ_SHIFT (0x00000000U)
2158 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_VP_IRQ_MAX (0x0000000FU)
2159 
2160 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_VP_IRQ_VAL_NOACTION (0x0U)
2161 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_VP_IRQ_VAL_SET_EVENT (0x1U)
2162 
2163 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_VID_IRQ_MASK (0x000000F0U)
2164 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_VID_IRQ_SHIFT (0x00000004U)
2165 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_VID_IRQ_MAX (0x0000000FU)
2166 
2167 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_VID_IRQ_VAL_NOACTION (0x0U)
2168 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_VID_IRQ_VAL_SET_EVENT (0x1U)
2169 
2170 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_RESERVED_VID_MASK (0x00001F00U)
2171 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_RESERVED_VID_SHIFT (0x00000008U)
2172 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_RESERVED_VID_MAX (0x0000001FU)
2173 
2174 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_RESERVED_CUR_MASK (0x00002000U)
2175 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_RESERVED_CUR_SHIFT (0x0000000DU)
2176 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_RESERVED_CUR_MAX (0x00000001U)
2177 
2178 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_WB_IRQ_MASK (0x00004000U)
2179 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_WB_IRQ_SHIFT (0x0000000EU)
2180 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_WB_IRQ_MAX (0x00000001U)
2181 
2182 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_WB_IRQ_VAL_NOACTION (0x0U)
2183 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_WB_IRQ_VAL_SET_EVENT (0x1U)
2184 
2185 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_DUMMY1_IRQ_MASK (0x00008000U)
2186 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_DUMMY1_IRQ_SHIFT (0x0000000FU)
2187 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_DUMMY1_IRQ_MAX (0x00000001U)
2188 
2189 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_DUMMY1_IRQ_VAL_NOACTION (0x0U)
2190 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_DUMMY1_IRQ_VAL_SET_EVENT (0x1U)
2191 
2192 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_DUMMY_IRQ_MASK (0x00010000U)
2193 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_DUMMY_IRQ_SHIFT (0x00000010U)
2194 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_DUMMY_IRQ_MAX (0x00000001U)
2195 
2196 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_DUMMY_IRQ_VAL_NOACTION (0x0U)
2197 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_DUMMY_IRQ_VAL_SET_EVENT (0x1U)
2198 
2199 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_RESERVED_MASK (0xFFFE0000U)
2200 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_RESERVED_SHIFT (0x00000011U)
2201 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RAW_RESERVED_MAX (0x00007FFFU)
2202 
2203 /* DISPC_IRQSTATUS */
2204 
2205 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_VP_IRQ_MASK (0x0000000FU)
2206 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_VP_IRQ_SHIFT (0x00000000U)
2207 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_VP_IRQ_MAX (0x0000000FU)
2208 
2209 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_VP_IRQ_VAL_NOACTION (0x0U)
2210 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_VP_IRQ_VAL_CLEAR (0x1U)
2211 
2212 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_VID_IRQ_MASK (0x000000F0U)
2213 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_VID_IRQ_SHIFT (0x00000004U)
2214 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_VID_IRQ_MAX (0x0000000FU)
2215 
2216 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_VID_IRQ_VAL_NOACTION (0x0U)
2217 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_VID_IRQ_VAL_CLEAR (0x1U)
2218 
2219 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RESERVED_VID_MASK (0x00001F00U)
2220 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RESERVED_VID_SHIFT (0x00000008U)
2221 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RESERVED_VID_MAX (0x0000001FU)
2222 
2223 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RESERVED_CUR_MASK (0x00002000U)
2224 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RESERVED_CUR_SHIFT (0x0000000DU)
2225 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RESERVED_CUR_MAX (0x00000001U)
2226 
2227 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_WB_IRQ_MASK (0x00004000U)
2228 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_WB_IRQ_SHIFT (0x0000000EU)
2229 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_WB_IRQ_MAX (0x00000001U)
2230 
2231 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_WB_IRQ_VAL_NOACTION (0x0U)
2232 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_WB_IRQ_VAL_CLEAR (0x1U)
2233 
2234 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_DUMMY1_IRQ_MASK (0x00008000U)
2235 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_DUMMY1_IRQ_SHIFT (0x0000000FU)
2236 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_DUMMY1_IRQ_MAX (0x00000001U)
2237 
2238 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_DUMMY1_IRQ_VAL_NOACTION (0x0U)
2239 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_DUMMY1_IRQ_VAL_CLEAR (0x1U)
2240 
2241 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_DUMMY_IRQ_MASK (0x00010000U)
2242 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_DUMMY_IRQ_SHIFT (0x00000010U)
2243 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_DUMMY_IRQ_MAX (0x00000001U)
2244 
2245 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_DUMMY_IRQ_VAL_NOACTION (0x0U)
2246 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_DUMMY_IRQ_VAL_CLEAR (0x1U)
2247 
2248 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RESERVED_MASK (0xFFFE0000U)
2249 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RESERVED_SHIFT (0x00000011U)
2250 #define CSL_DSS_COMMON_S0_DISPC_IRQSTATUS_RESERVED_MAX (0x00007FFFU)
2251 
2252 /* DISPC_IRQENABLE_SET */
2253 
2254 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_SET_VP_IRQ_MASK (0x0000000FU)
2255 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_SET_VP_IRQ_SHIFT (0x00000000U)
2256 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_SET_VP_IRQ_MAX (0x0000000FU)
2257 
2258 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_SET_VP_IRQ_VAL_NOACTION (0x0U)
2259 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_SET_VP_IRQ_VAL_ENABLE (0x1U)
2260 
2261 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_SET_VID_IRQ_MASK (0x000000F0U)
2262 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_SET_VID_IRQ_SHIFT (0x00000004U)
2263 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_SET_VID_IRQ_MAX (0x0000000FU)
2264 
2265 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_SET_VID_IRQ_VAL_NOACTION (0x0U)
2266 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_SET_VID_IRQ_VAL_ENABLE (0x1U)
2267 
2268 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_RESERVED_VID_MASK (0x00001F00U)
2269 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_RESERVED_VID_SHIFT (0x00000008U)
2270 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_RESERVED_VID_MAX (0x0000001FU)
2271 
2272 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_RESERVED_CUR_MASK (0x00002000U)
2273 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_RESERVED_CUR_SHIFT (0x0000000DU)
2274 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_RESERVED_CUR_MAX (0x00000001U)
2275 
2276 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_SET_WB_IRQ_MASK (0x00004000U)
2277 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_SET_WB_IRQ_SHIFT (0x0000000EU)
2278 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_SET_WB_IRQ_MAX (0x00000001U)
2279 
2280 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_SET_WB_IRQ_VAL_NOACTION (0x0U)
2281 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_SET_WB_IRQ_VAL_ENABLE (0x1U)
2282 
2283 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_SET_DUMMY1_IRQ_MASK (0x00008000U)
2284 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_SET_DUMMY1_IRQ_SHIFT (0x0000000FU)
2285 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_SET_DUMMY1_IRQ_MAX (0x00000001U)
2286 
2287 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_SET_DUMMY1_IRQ_VAL_NOACTION (0x0U)
2288 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_SET_DUMMY1_IRQ_VAL_ENABLE (0x1U)
2289 
2290 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_SET_DUMMY_IRQ_MASK (0x00010000U)
2291 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_SET_DUMMY_IRQ_SHIFT (0x00000010U)
2292 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_SET_DUMMY_IRQ_MAX (0x00000001U)
2293 
2294 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_SET_DUMMY_IRQ_VAL_NOACTION (0x0U)
2295 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_SET_DUMMY_IRQ_VAL_ENABLE (0x1U)
2296 
2297 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_RESERVED_MASK (0xFFFE0000U)
2298 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_RESERVED_SHIFT (0x00000011U)
2299 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_SET_RESERVED_MAX (0x00007FFFU)
2300 
2301 /* DISPC_IRQENABLE_CLR */
2302 
2303 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_MASK (0x0000000FU)
2304 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_SHIFT (0x00000000U)
2305 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_MAX (0x0000000FU)
2306 
2307 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_VAL_NOACTION (0x0U)
2308 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_VAL_CLEAR (0x1U)
2309 
2310 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_MASK (0x000000F0U)
2311 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_SHIFT (0x00000004U)
2312 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_MAX (0x0000000FU)
2313 
2314 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_VAL_NOACTION (0x0U)
2315 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_VAL_CLEAR (0x1U)
2316 
2317 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_RESERVED_VID_MASK (0x00001F00U)
2318 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_RESERVED_VID_SHIFT (0x00000008U)
2319 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_RESERVED_VID_MAX (0x0000001FU)
2320 
2321 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_RESERVED_CUR_MASK (0x00002000U)
2322 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_RESERVED_CUR_SHIFT (0x0000000DU)
2323 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_RESERVED_CUR_MAX (0x00000001U)
2324 
2325 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_CLR_WB_IRQ_MASK (0x00004000U)
2326 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_CLR_WB_IRQ_SHIFT (0x0000000EU)
2327 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_CLR_WB_IRQ_MAX (0x00000001U)
2328 
2329 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_CLR_WB_IRQ_VAL_NOACTION (0x0U)
2330 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_CLR_WB_IRQ_VAL_CLEAR (0x1U)
2331 
2332 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_CLR_DUMMY1_IRQ_MASK (0x00008000U)
2333 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_CLR_DUMMY1_IRQ_SHIFT (0x0000000FU)
2334 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_CLR_DUMMY1_IRQ_MAX (0x00000001U)
2335 
2336 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_CLR_DUMMY1_IRQ_VAL_NOACTION (0x0U)
2337 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_CLR_DUMMY1_IRQ_VAL_CLEAR (0x1U)
2338 
2339 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_CLR_DUMMY_IRQ_MASK (0x00010000U)
2340 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_CLR_DUMMY_IRQ_SHIFT (0x00000010U)
2341 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_CLR_DUMMY_IRQ_MAX (0x00000001U)
2342 
2343 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_CLR_DUMMY_IRQ_VAL_NOACTION (0x0U)
2344 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_CLR_DUMMY_IRQ_VAL_CLEAR (0x1U)
2345 
2346 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_RESERVED_MASK (0xFFFE0000U)
2347 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_RESERVED_SHIFT (0x00000011U)
2348 #define CSL_DSS_COMMON_S0_DISPC_IRQENABLE_CLR_RESERVED_MAX (0x00007FFFU)
2349 
2350 /* VID_IRQENABLE_0 */
2351 
2352 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_MASK (0x00000001U)
2353 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_SHIFT (0x00000000U)
2354 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_MAX (0x00000001U)
2355 
2356 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_VAL_MASKED (0x0U)
2357 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_VAL_GENINT (0x1U)
2358 
2359 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_VIDENDWINDOW_EN_MASK (0x00000002U)
2360 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_VIDENDWINDOW_EN_SHIFT (0x00000001U)
2361 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_VIDENDWINDOW_EN_MAX (0x00000001U)
2362 
2363 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_VIDENDWINDOW_EN_VAL_MASKED (0x0U)
2364 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_VIDENDWINDOW_EN_VAL_GENINT (0x1U)
2365 
2366 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_SAFETYREGION_EN_MASK (0x00000004U)
2367 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_SAFETYREGION_EN_SHIFT (0x00000002U)
2368 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_SAFETYREGION_EN_MAX (0x00000001U)
2369 
2370 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_SAFETYREGION_EN_VAL_MASKED (0x0U)
2371 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_SAFETYREGION_EN_VAL_GENINT (0x1U)
2372 
2373 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_FBDC_CORRUPTTILE_EN_MASK (0x00000008U)
2374 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_FBDC_CORRUPTTILE_EN_SHIFT (0x00000003U)
2375 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_FBDC_CORRUPTTILE_EN_MAX (0x00000001U)
2376 
2377 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_FBDC_CORRUPTTILE_EN_VAL_MASKED (0x0U)
2378 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_FBDC_CORRUPTTILE_EN_VAL_GENINT (0x1U)
2379 
2380 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_FBDC_ILLEGALTILEREQ_EN_MASK (0x00000010U)
2381 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_FBDC_ILLEGALTILEREQ_EN_SHIFT (0x00000004U)
2382 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_FBDC_ILLEGALTILEREQ_EN_MAX (0x00000001U)
2383 
2384 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_FBDC_ILLEGALTILEREQ_EN_VAL_MASKED (0x0U)
2385 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_FBDC_ILLEGALTILEREQ_EN_VAL_GENINT (0x1U)
2386 
2387 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_RESERVED_MASK (0xFFFFFFE0U)
2388 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_RESERVED_SHIFT (0x00000005U)
2389 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_0_RESERVED_MAX (0x07FFFFFFU)
2390 
2391 /* VID_IRQENABLE_1 */
2392 
2393 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_MASK (0x00000001U)
2394 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_SHIFT (0x00000000U)
2395 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_MAX (0x00000001U)
2396 
2397 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_VAL_MASKED (0x0U)
2398 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_VAL_GENINT (0x1U)
2399 
2400 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_VIDENDWINDOW_EN_MASK (0x00000002U)
2401 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_VIDENDWINDOW_EN_SHIFT (0x00000001U)
2402 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_VIDENDWINDOW_EN_MAX (0x00000001U)
2403 
2404 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_VIDENDWINDOW_EN_VAL_MASKED (0x0U)
2405 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_VIDENDWINDOW_EN_VAL_GENINT (0x1U)
2406 
2407 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_SAFETYREGION_EN_MASK (0x00000004U)
2408 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_SAFETYREGION_EN_SHIFT (0x00000002U)
2409 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_SAFETYREGION_EN_MAX (0x00000001U)
2410 
2411 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_SAFETYREGION_EN_VAL_MASKED (0x0U)
2412 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_SAFETYREGION_EN_VAL_GENINT (0x1U)
2413 
2414 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_FBDC_CORRUPTTILE_EN_MASK (0x00000008U)
2415 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_FBDC_CORRUPTTILE_EN_SHIFT (0x00000003U)
2416 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_FBDC_CORRUPTTILE_EN_MAX (0x00000001U)
2417 
2418 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_FBDC_CORRUPTTILE_EN_VAL_MASKED (0x0U)
2419 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_FBDC_CORRUPTTILE_EN_VAL_GENINT (0x1U)
2420 
2421 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_FBDC_ILLEGALTILEREQ_EN_MASK (0x00000010U)
2422 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_FBDC_ILLEGALTILEREQ_EN_SHIFT (0x00000004U)
2423 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_FBDC_ILLEGALTILEREQ_EN_MAX (0x00000001U)
2424 
2425 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_FBDC_ILLEGALTILEREQ_EN_VAL_MASKED (0x0U)
2426 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_FBDC_ILLEGALTILEREQ_EN_VAL_GENINT (0x1U)
2427 
2428 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_RESERVED_MASK (0xFFFFFFE0U)
2429 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_RESERVED_SHIFT (0x00000005U)
2430 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_1_RESERVED_MAX (0x07FFFFFFU)
2431 
2432 /* VID_IRQENABLE_2 */
2433 
2434 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_VIDBUFFERUNDERFLOW_EN_MASK (0x00000001U)
2435 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_VIDBUFFERUNDERFLOW_EN_SHIFT (0x00000000U)
2436 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_VIDBUFFERUNDERFLOW_EN_MAX (0x00000001U)
2437 
2438 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_VIDBUFFERUNDERFLOW_EN_VAL_MASKED (0x0U)
2439 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_VIDBUFFERUNDERFLOW_EN_VAL_GENINT (0x1U)
2440 
2441 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_VIDENDWINDOW_EN_MASK (0x00000002U)
2442 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_VIDENDWINDOW_EN_SHIFT (0x00000001U)
2443 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_VIDENDWINDOW_EN_MAX (0x00000001U)
2444 
2445 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_VIDENDWINDOW_EN_VAL_MASKED (0x0U)
2446 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_VIDENDWINDOW_EN_VAL_GENINT (0x1U)
2447 
2448 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_SAFETYREGION_EN_MASK (0x00000004U)
2449 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_SAFETYREGION_EN_SHIFT (0x00000002U)
2450 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_SAFETYREGION_EN_MAX (0x00000001U)
2451 
2452 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_SAFETYREGION_EN_VAL_MASKED (0x0U)
2453 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_SAFETYREGION_EN_VAL_GENINT (0x1U)
2454 
2455 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_FBDC_CORRUPTTILE_EN_MASK (0x00000008U)
2456 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_FBDC_CORRUPTTILE_EN_SHIFT (0x00000003U)
2457 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_FBDC_CORRUPTTILE_EN_MAX (0x00000001U)
2458 
2459 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_FBDC_CORRUPTTILE_EN_VAL_MASKED (0x0U)
2460 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_FBDC_CORRUPTTILE_EN_VAL_GENINT (0x1U)
2461 
2462 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_FBDC_ILLEGALTILEREQ_EN_MASK (0x00000010U)
2463 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_FBDC_ILLEGALTILEREQ_EN_SHIFT (0x00000004U)
2464 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_FBDC_ILLEGALTILEREQ_EN_MAX (0x00000001U)
2465 
2466 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_FBDC_ILLEGALTILEREQ_EN_VAL_MASKED (0x0U)
2467 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_FBDC_ILLEGALTILEREQ_EN_VAL_GENINT (0x1U)
2468 
2469 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_RESERVED_MASK (0xFFFFFFE0U)
2470 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_RESERVED_SHIFT (0x00000005U)
2471 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_2_RESERVED_MAX (0x07FFFFFFU)
2472 
2473 /* VID_IRQENABLE_3 */
2474 
2475 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_VIDBUFFERUNDERFLOW_EN_MASK (0x00000001U)
2476 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_VIDBUFFERUNDERFLOW_EN_SHIFT (0x00000000U)
2477 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_VIDBUFFERUNDERFLOW_EN_MAX (0x00000001U)
2478 
2479 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_VIDBUFFERUNDERFLOW_EN_VAL_MASKED (0x0U)
2480 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_VIDBUFFERUNDERFLOW_EN_VAL_GENINT (0x1U)
2481 
2482 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_VIDENDWINDOW_EN_MASK (0x00000002U)
2483 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_VIDENDWINDOW_EN_SHIFT (0x00000001U)
2484 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_VIDENDWINDOW_EN_MAX (0x00000001U)
2485 
2486 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_VIDENDWINDOW_EN_VAL_MASKED (0x0U)
2487 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_VIDENDWINDOW_EN_VAL_GENINT (0x1U)
2488 
2489 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_SAFETYREGION_EN_MASK (0x00000004U)
2490 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_SAFETYREGION_EN_SHIFT (0x00000002U)
2491 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_SAFETYREGION_EN_MAX (0x00000001U)
2492 
2493 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_SAFETYREGION_EN_VAL_MASKED (0x0U)
2494 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_SAFETYREGION_EN_VAL_GENINT (0x1U)
2495 
2496 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_FBDC_CORRUPTTILE_EN_MASK (0x00000008U)
2497 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_FBDC_CORRUPTTILE_EN_SHIFT (0x00000003U)
2498 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_FBDC_CORRUPTTILE_EN_MAX (0x00000001U)
2499 
2500 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_FBDC_CORRUPTTILE_EN_VAL_MASKED (0x0U)
2501 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_FBDC_CORRUPTTILE_EN_VAL_GENINT (0x1U)
2502 
2503 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_FBDC_ILLEGALTILEREQ_EN_MASK (0x00000010U)
2504 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_FBDC_ILLEGALTILEREQ_EN_SHIFT (0x00000004U)
2505 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_FBDC_ILLEGALTILEREQ_EN_MAX (0x00000001U)
2506 
2507 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_FBDC_ILLEGALTILEREQ_EN_VAL_MASKED (0x0U)
2508 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_FBDC_ILLEGALTILEREQ_EN_VAL_GENINT (0x1U)
2509 
2510 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_RESERVED_MASK (0xFFFFFFE0U)
2511 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_RESERVED_SHIFT (0x00000005U)
2512 #define CSL_DSS_COMMON_S0_VID_IRQENABLE_3_RESERVED_MAX (0x07FFFFFFU)
2513 
2514 /* VID_IRQSTATUS_0 */
2515 
2516 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_MASK (0x00000001U)
2517 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_SHIFT (0x00000000U)
2518 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_MAX (0x00000001U)
2519 
2520 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_VAL_NOPEND (0x0U)
2521 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_VAL_PEND (0x1U)
2522 
2523 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_MASK (0x00000002U)
2524 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_SHIFT (0x00000001U)
2525 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_MAX (0x00000001U)
2526 
2527 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_VAL_NOPEND (0x0U)
2528 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_VAL_PEND (0x1U)
2529 
2530 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_SAFETYREGION_IRQ_MASK (0x00000004U)
2531 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_SAFETYREGION_IRQ_SHIFT (0x00000002U)
2532 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_SAFETYREGION_IRQ_MAX (0x00000001U)
2533 
2534 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
2535 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_PEND (0x1U)
2536 
2537 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_FBDC_CORRUPTTILE_IRQ_MASK (0x00000008U)
2538 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_FBDC_CORRUPTTILE_IRQ_SHIFT (0x00000003U)
2539 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_FBDC_CORRUPTTILE_IRQ_MAX (0x00000001U)
2540 
2541 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_FBDC_CORRUPTTILE_IRQ_VAL_NOPEND (0x0U)
2542 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_FBDC_CORRUPTTILE_IRQ_VAL_PEND (0x1U)
2543 
2544 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_FBDC_ILLEGALTILEREQ_IRQ_MASK (0x00000010U)
2545 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_FBDC_ILLEGALTILEREQ_IRQ_SHIFT (0x00000004U)
2546 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_FBDC_ILLEGALTILEREQ_IRQ_MAX (0x00000001U)
2547 
2548 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_FBDC_ILLEGALTILEREQ_IRQ_VAL_NOPEND (0x0U)
2549 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_FBDC_ILLEGALTILEREQ_IRQ_VAL_PEND (0x1U)
2550 
2551 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_RESERVED_MASK (0xFFFFFFE0U)
2552 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_RESERVED_SHIFT (0x00000005U)
2553 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_0_RESERVED_MAX (0x07FFFFFFU)
2554 
2555 /* VID_IRQSTATUS_1 */
2556 
2557 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_MASK (0x00000001U)
2558 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_SHIFT (0x00000000U)
2559 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_MAX (0x00000001U)
2560 
2561 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_VAL_NOPEND (0x0U)
2562 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_VAL_PEND (0x1U)
2563 
2564 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_MASK (0x00000002U)
2565 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_SHIFT (0x00000001U)
2566 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_MAX (0x00000001U)
2567 
2568 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_VAL_NOPEND (0x0U)
2569 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_VAL_PEND (0x1U)
2570 
2571 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_SAFETYREGION_IRQ_MASK (0x00000004U)
2572 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_SAFETYREGION_IRQ_SHIFT (0x00000002U)
2573 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_SAFETYREGION_IRQ_MAX (0x00000001U)
2574 
2575 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
2576 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_PEND (0x1U)
2577 
2578 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_FBDC_CORRUPTTILE_IRQ_MASK (0x00000008U)
2579 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_FBDC_CORRUPTTILE_IRQ_SHIFT (0x00000003U)
2580 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_FBDC_CORRUPTTILE_IRQ_MAX (0x00000001U)
2581 
2582 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_FBDC_CORRUPTTILE_IRQ_VAL_NOPEND (0x0U)
2583 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_FBDC_CORRUPTTILE_IRQ_VAL_PEND (0x1U)
2584 
2585 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_FBDC_ILLEGALTILEREQ_IRQ_MASK (0x00000010U)
2586 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_FBDC_ILLEGALTILEREQ_IRQ_SHIFT (0x00000004U)
2587 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_FBDC_ILLEGALTILEREQ_IRQ_MAX (0x00000001U)
2588 
2589 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_FBDC_ILLEGALTILEREQ_IRQ_VAL_NOPEND (0x0U)
2590 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_FBDC_ILLEGALTILEREQ_IRQ_VAL_PEND (0x1U)
2591 
2592 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_RESERVED_MASK (0xFFFFFFE0U)
2593 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_RESERVED_SHIFT (0x00000005U)
2594 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_1_RESERVED_MAX (0x07FFFFFFU)
2595 
2596 /* VID_IRQSTATUS_2 */
2597 
2598 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_VIDBUFFERUNDERFLOW_IRQ_MASK (0x00000001U)
2599 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_VIDBUFFERUNDERFLOW_IRQ_SHIFT (0x00000000U)
2600 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_VIDBUFFERUNDERFLOW_IRQ_MAX (0x00000001U)
2601 
2602 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_VIDBUFFERUNDERFLOW_IRQ_VAL_NOPEND (0x0U)
2603 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_VIDBUFFERUNDERFLOW_IRQ_VAL_PEND (0x1U)
2604 
2605 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_VIDENDWINDOW_IRQ_MASK (0x00000002U)
2606 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_VIDENDWINDOW_IRQ_SHIFT (0x00000001U)
2607 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_VIDENDWINDOW_IRQ_MAX (0x00000001U)
2608 
2609 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_VIDENDWINDOW_IRQ_VAL_NOPEND (0x0U)
2610 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_VIDENDWINDOW_IRQ_VAL_PEND (0x1U)
2611 
2612 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_SAFETYREGION_IRQ_MASK (0x00000004U)
2613 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_SAFETYREGION_IRQ_SHIFT (0x00000002U)
2614 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_SAFETYREGION_IRQ_MAX (0x00000001U)
2615 
2616 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
2617 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_SAFETYREGION_IRQ_VAL_PEND (0x1U)
2618 
2619 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_FBDC_CORRUPTTILE_IRQ_MASK (0x00000008U)
2620 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_FBDC_CORRUPTTILE_IRQ_SHIFT (0x00000003U)
2621 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_FBDC_CORRUPTTILE_IRQ_MAX (0x00000001U)
2622 
2623 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_FBDC_CORRUPTTILE_IRQ_VAL_NOPEND (0x0U)
2624 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_FBDC_CORRUPTTILE_IRQ_VAL_PEND (0x1U)
2625 
2626 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_FBDC_ILLEGALTILEREQ_IRQ_MASK (0x00000010U)
2627 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_FBDC_ILLEGALTILEREQ_IRQ_SHIFT (0x00000004U)
2628 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_FBDC_ILLEGALTILEREQ_IRQ_MAX (0x00000001U)
2629 
2630 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_FBDC_ILLEGALTILEREQ_IRQ_VAL_NOPEND (0x0U)
2631 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_FBDC_ILLEGALTILEREQ_IRQ_VAL_PEND (0x1U)
2632 
2633 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_RESERVED_MASK (0xFFFFFFE0U)
2634 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_RESERVED_SHIFT (0x00000005U)
2635 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_2_RESERVED_MAX (0x07FFFFFFU)
2636 
2637 /* VID_IRQSTATUS_3 */
2638 
2639 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_VIDBUFFERUNDERFLOW_IRQ_MASK (0x00000001U)
2640 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_VIDBUFFERUNDERFLOW_IRQ_SHIFT (0x00000000U)
2641 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_VIDBUFFERUNDERFLOW_IRQ_MAX (0x00000001U)
2642 
2643 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_VIDBUFFERUNDERFLOW_IRQ_VAL_NOPEND (0x0U)
2644 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_VIDBUFFERUNDERFLOW_IRQ_VAL_PEND (0x1U)
2645 
2646 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_VIDENDWINDOW_IRQ_MASK (0x00000002U)
2647 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_VIDENDWINDOW_IRQ_SHIFT (0x00000001U)
2648 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_VIDENDWINDOW_IRQ_MAX (0x00000001U)
2649 
2650 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_VIDENDWINDOW_IRQ_VAL_NOPEND (0x0U)
2651 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_VIDENDWINDOW_IRQ_VAL_PEND (0x1U)
2652 
2653 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_SAFETYREGION_IRQ_MASK (0x00000004U)
2654 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_SAFETYREGION_IRQ_SHIFT (0x00000002U)
2655 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_SAFETYREGION_IRQ_MAX (0x00000001U)
2656 
2657 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
2658 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_SAFETYREGION_IRQ_VAL_PEND (0x1U)
2659 
2660 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_FBDC_CORRUPTTILE_IRQ_MASK (0x00000008U)
2661 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_FBDC_CORRUPTTILE_IRQ_SHIFT (0x00000003U)
2662 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_FBDC_CORRUPTTILE_IRQ_MAX (0x00000001U)
2663 
2664 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_FBDC_CORRUPTTILE_IRQ_VAL_NOPEND (0x0U)
2665 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_FBDC_CORRUPTTILE_IRQ_VAL_PEND (0x1U)
2666 
2667 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_FBDC_ILLEGALTILEREQ_IRQ_MASK (0x00000010U)
2668 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_FBDC_ILLEGALTILEREQ_IRQ_SHIFT (0x00000004U)
2669 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_FBDC_ILLEGALTILEREQ_IRQ_MAX (0x00000001U)
2670 
2671 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_FBDC_ILLEGALTILEREQ_IRQ_VAL_NOPEND (0x0U)
2672 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_FBDC_ILLEGALTILEREQ_IRQ_VAL_PEND (0x1U)
2673 
2674 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_RESERVED_MASK (0xFFFFFFE0U)
2675 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_RESERVED_SHIFT (0x00000005U)
2676 #define CSL_DSS_COMMON_S0_VID_IRQSTATUS_3_RESERVED_MAX (0x07FFFFFFU)
2677 
2678 /* VP_IRQENABLE_0 */
2679 
2680 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPFRAMEDONE_EN_MASK (0x00000001U)
2681 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPFRAMEDONE_EN_SHIFT (0x00000000U)
2682 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPFRAMEDONE_EN_MAX (0x00000001U)
2683 
2684 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPFRAMEDONE_EN_VAL_MASKED (0x0U)
2685 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPFRAMEDONE_EN_VAL_GENINT (0x1U)
2686 
2687 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPVSYNC_EN_MASK (0x00000002U)
2688 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPVSYNC_EN_SHIFT (0x00000001U)
2689 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPVSYNC_EN_MAX (0x00000001U)
2690 
2691 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPVSYNC_EN_VAL_MASKED (0x0U)
2692 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPVSYNC_EN_VAL_GENINT (0x1U)
2693 
2694 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPVSYNC_ODD_EN_MASK (0x00000004U)
2695 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPVSYNC_ODD_EN_SHIFT (0x00000002U)
2696 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPVSYNC_ODD_EN_MAX (0x00000001U)
2697 
2698 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPVSYNC_ODD_EN_VAL_MASKED (0x0U)
2699 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPVSYNC_ODD_EN_VAL_GENINT (0x1U)
2700 
2701 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_MASK (0x00000008U)
2702 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_SHIFT (0x00000003U)
2703 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_MAX (0x00000001U)
2704 
2705 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_VAL_MASKED (0x0U)
2706 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_VAL_GENINT (0x1U)
2707 
2708 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPSYNCLOST_EN_MASK (0x00000010U)
2709 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPSYNCLOST_EN_SHIFT (0x00000004U)
2710 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPSYNCLOST_EN_MAX (0x00000001U)
2711 
2712 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPSYNCLOST_EN_VAL_MASKED (0x0U)
2713 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPSYNCLOST_EN_VAL_GENINT (0x1U)
2714 
2715 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_MASK (0x00000020U)
2716 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_SHIFT (0x00000005U)
2717 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_MAX (0x00000001U)
2718 
2719 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_VAL_MASKED (0x0U)
2720 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_VAL_GENINT (0x1U)
2721 
2722 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_SAFETYREGION_EN_MASK (0x000003C0U)
2723 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_SAFETYREGION_EN_SHIFT (0x00000006U)
2724 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_SAFETYREGION_EN_MAX (0x0000000FU)
2725 
2726 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_SAFETYREGION_EN_VAL_MASKED (0x0U)
2727 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_SAFETYREGION_EN_VAL_GENINT (0x1U)
2728 
2729 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_SECURITYVIOLATION_EN_MASK (0x00000400U)
2730 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_SECURITYVIOLATION_EN_SHIFT (0x0000000AU)
2731 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_SECURITYVIOLATION_EN_MAX (0x00000001U)
2732 
2733 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
2734 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
2735 
2736 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPSYNC_EN_MASK (0x00000800U)
2737 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPSYNC_EN_SHIFT (0x0000000BU)
2738 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPSYNC_EN_MAX (0x00000001U)
2739 
2740 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPSYNC_EN_VAL_MASKED (0x0U)
2741 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_VPSYNC_EN_VAL_GENINT (0x1U)
2742 
2743 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_DUMMY_EN_MASK (0x00001000U)
2744 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_DUMMY_EN_SHIFT (0x0000000CU)
2745 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_DUMMY_EN_MAX (0x00000001U)
2746 
2747 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_DUMMY_EN_VAL_MASKED (0x0U)
2748 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_DUMMY_EN_VAL_GENINT (0x1U)
2749 
2750 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_SAFETYREGION1_EN_MASK (0x0001E000U)
2751 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_SAFETYREGION1_EN_SHIFT (0x0000000DU)
2752 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_SAFETYREGION1_EN_MAX (0x0000000FU)
2753 
2754 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_SAFETYREGION1_EN_VAL_MASKED (0x0U)
2755 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_SAFETYREGION1_EN_VAL_GENINT (0x1U)
2756 
2757 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_RESERVED_MASK (0xFFFE0000U)
2758 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_RESERVED_SHIFT (0x00000011U)
2759 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_0_RESERVED_MAX (0x00007FFFU)
2760 
2761 /* VP_IRQENABLE_1 */
2762 
2763 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPFRAMEDONE_EN_MASK (0x00000001U)
2764 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPFRAMEDONE_EN_SHIFT (0x00000000U)
2765 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPFRAMEDONE_EN_MAX (0x00000001U)
2766 
2767 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPFRAMEDONE_EN_VAL_MASKED (0x0U)
2768 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPFRAMEDONE_EN_VAL_GENINT (0x1U)
2769 
2770 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPVSYNC_EN_MASK (0x00000002U)
2771 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPVSYNC_EN_SHIFT (0x00000001U)
2772 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPVSYNC_EN_MAX (0x00000001U)
2773 
2774 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPVSYNC_EN_VAL_MASKED (0x0U)
2775 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPVSYNC_EN_VAL_GENINT (0x1U)
2776 
2777 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPVSYNC_ODD_EN_MASK (0x00000004U)
2778 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPVSYNC_ODD_EN_SHIFT (0x00000002U)
2779 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPVSYNC_ODD_EN_MAX (0x00000001U)
2780 
2781 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPVSYNC_ODD_EN_VAL_MASKED (0x0U)
2782 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPVSYNC_ODD_EN_VAL_GENINT (0x1U)
2783 
2784 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_MASK (0x00000008U)
2785 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_SHIFT (0x00000003U)
2786 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_MAX (0x00000001U)
2787 
2788 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_VAL_MASKED (0x0U)
2789 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_VAL_GENINT (0x1U)
2790 
2791 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPSYNCLOST_EN_MASK (0x00000010U)
2792 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPSYNCLOST_EN_SHIFT (0x00000004U)
2793 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPSYNCLOST_EN_MAX (0x00000001U)
2794 
2795 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPSYNCLOST_EN_VAL_MASKED (0x0U)
2796 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPSYNCLOST_EN_VAL_GENINT (0x1U)
2797 
2798 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_MASK (0x00000020U)
2799 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_SHIFT (0x00000005U)
2800 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_MAX (0x00000001U)
2801 
2802 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_VAL_MASKED (0x0U)
2803 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_VAL_GENINT (0x1U)
2804 
2805 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_SAFETYREGION_EN_MASK (0x000003C0U)
2806 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_SAFETYREGION_EN_SHIFT (0x00000006U)
2807 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_SAFETYREGION_EN_MAX (0x0000000FU)
2808 
2809 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_SAFETYREGION_EN_VAL_MASKED (0x0U)
2810 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_SAFETYREGION_EN_VAL_GENINT (0x1U)
2811 
2812 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_SECURITYVIOLATION_EN_MASK (0x00000400U)
2813 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_SECURITYVIOLATION_EN_SHIFT (0x0000000AU)
2814 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_SECURITYVIOLATION_EN_MAX (0x00000001U)
2815 
2816 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
2817 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
2818 
2819 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPSYNC_EN_MASK (0x00000800U)
2820 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPSYNC_EN_SHIFT (0x0000000BU)
2821 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPSYNC_EN_MAX (0x00000001U)
2822 
2823 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPSYNC_EN_VAL_MASKED (0x0U)
2824 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_VPSYNC_EN_VAL_GENINT (0x1U)
2825 
2826 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_DUMMY_EN_MASK (0x00001000U)
2827 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_DUMMY_EN_SHIFT (0x0000000CU)
2828 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_DUMMY_EN_MAX (0x00000001U)
2829 
2830 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_DUMMY_EN_VAL_MASKED (0x0U)
2831 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_DUMMY_EN_VAL_GENINT (0x1U)
2832 
2833 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_SAFETYREGION1_EN_MASK (0x0001E000U)
2834 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_SAFETYREGION1_EN_SHIFT (0x0000000DU)
2835 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_SAFETYREGION1_EN_MAX (0x0000000FU)
2836 
2837 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_SAFETYREGION1_EN_VAL_MASKED (0x0U)
2838 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_SAFETYREGION1_EN_VAL_GENINT (0x1U)
2839 
2840 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_RESERVED_MASK (0xFFFE0000U)
2841 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_RESERVED_SHIFT (0x00000011U)
2842 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_1_RESERVED_MAX (0x00007FFFU)
2843 
2844 /* VP_IRQENABLE_2 */
2845 
2846 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPFRAMEDONE_EN_MASK (0x00000001U)
2847 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPFRAMEDONE_EN_SHIFT (0x00000000U)
2848 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPFRAMEDONE_EN_MAX (0x00000001U)
2849 
2850 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPFRAMEDONE_EN_VAL_MASKED (0x0U)
2851 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPFRAMEDONE_EN_VAL_GENINT (0x1U)
2852 
2853 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPVSYNC_EN_MASK (0x00000002U)
2854 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPVSYNC_EN_SHIFT (0x00000001U)
2855 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPVSYNC_EN_MAX (0x00000001U)
2856 
2857 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPVSYNC_EN_VAL_MASKED (0x0U)
2858 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPVSYNC_EN_VAL_GENINT (0x1U)
2859 
2860 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPVSYNC_ODD_EN_MASK (0x00000004U)
2861 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPVSYNC_ODD_EN_SHIFT (0x00000002U)
2862 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPVSYNC_ODD_EN_MAX (0x00000001U)
2863 
2864 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPVSYNC_ODD_EN_VAL_MASKED (0x0U)
2865 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPVSYNC_ODD_EN_VAL_GENINT (0x1U)
2866 
2867 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPPROGRAMMEDLINENUMBER_EN_MASK (0x00000008U)
2868 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPPROGRAMMEDLINENUMBER_EN_SHIFT (0x00000003U)
2869 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPPROGRAMMEDLINENUMBER_EN_MAX (0x00000001U)
2870 
2871 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPPROGRAMMEDLINENUMBER_EN_VAL_MASKED (0x0U)
2872 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPPROGRAMMEDLINENUMBER_EN_VAL_GENINT (0x1U)
2873 
2874 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPSYNCLOST_EN_MASK (0x00000010U)
2875 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPSYNCLOST_EN_SHIFT (0x00000004U)
2876 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPSYNCLOST_EN_MAX (0x00000001U)
2877 
2878 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPSYNCLOST_EN_VAL_MASKED (0x0U)
2879 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPSYNCLOST_EN_VAL_GENINT (0x1U)
2880 
2881 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_ACBIASCOUNTSTATUS_EN_MASK (0x00000020U)
2882 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_ACBIASCOUNTSTATUS_EN_SHIFT (0x00000005U)
2883 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_ACBIASCOUNTSTATUS_EN_MAX (0x00000001U)
2884 
2885 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_ACBIASCOUNTSTATUS_EN_VAL_MASKED (0x0U)
2886 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_ACBIASCOUNTSTATUS_EN_VAL_GENINT (0x1U)
2887 
2888 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_SAFETYREGION_EN_MASK (0x000003C0U)
2889 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_SAFETYREGION_EN_SHIFT (0x00000006U)
2890 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_SAFETYREGION_EN_MAX (0x0000000FU)
2891 
2892 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_SAFETYREGION_EN_VAL_MASKED (0x0U)
2893 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_SAFETYREGION_EN_VAL_GENINT (0x1U)
2894 
2895 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_SECURITYVIOLATION_EN_MASK (0x00000400U)
2896 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_SECURITYVIOLATION_EN_SHIFT (0x0000000AU)
2897 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_SECURITYVIOLATION_EN_MAX (0x00000001U)
2898 
2899 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
2900 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
2901 
2902 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPSYNC_EN_MASK (0x00000800U)
2903 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPSYNC_EN_SHIFT (0x0000000BU)
2904 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPSYNC_EN_MAX (0x00000001U)
2905 
2906 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPSYNC_EN_VAL_MASKED (0x0U)
2907 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_VPSYNC_EN_VAL_GENINT (0x1U)
2908 
2909 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_DUMMY_EN_MASK (0x00001000U)
2910 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_DUMMY_EN_SHIFT (0x0000000CU)
2911 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_DUMMY_EN_MAX (0x00000001U)
2912 
2913 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_DUMMY_EN_VAL_MASKED (0x0U)
2914 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_DUMMY_EN_VAL_GENINT (0x1U)
2915 
2916 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_SAFETYREGION1_EN_MASK (0x0001E000U)
2917 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_SAFETYREGION1_EN_SHIFT (0x0000000DU)
2918 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_SAFETYREGION1_EN_MAX (0x0000000FU)
2919 
2920 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_SAFETYREGION1_EN_VAL_MASKED (0x0U)
2921 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_SAFETYREGION1_EN_VAL_GENINT (0x1U)
2922 
2923 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_RESERVED_MASK (0xFFFE0000U)
2924 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_RESERVED_SHIFT (0x00000011U)
2925 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_2_RESERVED_MAX (0x00007FFFU)
2926 
2927 /* VP_IRQENABLE_3 */
2928 
2929 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPFRAMEDONE_EN_MASK (0x00000001U)
2930 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPFRAMEDONE_EN_SHIFT (0x00000000U)
2931 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPFRAMEDONE_EN_MAX (0x00000001U)
2932 
2933 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPFRAMEDONE_EN_VAL_MASKED (0x0U)
2934 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPFRAMEDONE_EN_VAL_GENINT (0x1U)
2935 
2936 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPVSYNC_EN_MASK (0x00000002U)
2937 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPVSYNC_EN_SHIFT (0x00000001U)
2938 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPVSYNC_EN_MAX (0x00000001U)
2939 
2940 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPVSYNC_EN_VAL_MASKED (0x0U)
2941 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPVSYNC_EN_VAL_GENINT (0x1U)
2942 
2943 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPVSYNC_ODD_EN_MASK (0x00000004U)
2944 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPVSYNC_ODD_EN_SHIFT (0x00000002U)
2945 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPVSYNC_ODD_EN_MAX (0x00000001U)
2946 
2947 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPVSYNC_ODD_EN_VAL_MASKED (0x0U)
2948 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPVSYNC_ODD_EN_VAL_GENINT (0x1U)
2949 
2950 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPPROGRAMMEDLINENUMBER_EN_MASK (0x00000008U)
2951 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPPROGRAMMEDLINENUMBER_EN_SHIFT (0x00000003U)
2952 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPPROGRAMMEDLINENUMBER_EN_MAX (0x00000001U)
2953 
2954 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPPROGRAMMEDLINENUMBER_EN_VAL_MASKED (0x0U)
2955 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPPROGRAMMEDLINENUMBER_EN_VAL_GENINT (0x1U)
2956 
2957 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPSYNCLOST_EN_MASK (0x00000010U)
2958 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPSYNCLOST_EN_SHIFT (0x00000004U)
2959 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPSYNCLOST_EN_MAX (0x00000001U)
2960 
2961 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPSYNCLOST_EN_VAL_MASKED (0x0U)
2962 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPSYNCLOST_EN_VAL_GENINT (0x1U)
2963 
2964 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_ACBIASCOUNTSTATUS_EN_MASK (0x00000020U)
2965 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_ACBIASCOUNTSTATUS_EN_SHIFT (0x00000005U)
2966 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_ACBIASCOUNTSTATUS_EN_MAX (0x00000001U)
2967 
2968 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_ACBIASCOUNTSTATUS_EN_VAL_MASKED (0x0U)
2969 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_ACBIASCOUNTSTATUS_EN_VAL_GENINT (0x1U)
2970 
2971 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_SAFETYREGION_EN_MASK (0x000003C0U)
2972 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_SAFETYREGION_EN_SHIFT (0x00000006U)
2973 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_SAFETYREGION_EN_MAX (0x0000000FU)
2974 
2975 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_SAFETYREGION_EN_VAL_MASKED (0x0U)
2976 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_SAFETYREGION_EN_VAL_GENINT (0x1U)
2977 
2978 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_SECURITYVIOLATION_EN_MASK (0x00000400U)
2979 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_SECURITYVIOLATION_EN_SHIFT (0x0000000AU)
2980 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_SECURITYVIOLATION_EN_MAX (0x00000001U)
2981 
2982 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
2983 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
2984 
2985 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPSYNC_EN_MASK (0x00000800U)
2986 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPSYNC_EN_SHIFT (0x0000000BU)
2987 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPSYNC_EN_MAX (0x00000001U)
2988 
2989 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPSYNC_EN_VAL_MASKED (0x0U)
2990 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_VPSYNC_EN_VAL_GENINT (0x1U)
2991 
2992 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_DUMMY_EN_MASK (0x00001000U)
2993 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_DUMMY_EN_SHIFT (0x0000000CU)
2994 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_DUMMY_EN_MAX (0x00000001U)
2995 
2996 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_DUMMY_EN_VAL_MASKED (0x0U)
2997 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_DUMMY_EN_VAL_GENINT (0x1U)
2998 
2999 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_SAFETYREGION1_EN_MASK (0x0001E000U)
3000 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_SAFETYREGION1_EN_SHIFT (0x0000000DU)
3001 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_SAFETYREGION1_EN_MAX (0x0000000FU)
3002 
3003 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_SAFETYREGION1_EN_VAL_MASKED (0x0U)
3004 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_SAFETYREGION1_EN_VAL_GENINT (0x1U)
3005 
3006 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_RESERVED_MASK (0xFFFE0000U)
3007 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_RESERVED_SHIFT (0x00000011U)
3008 #define CSL_DSS_COMMON_S0_VP_IRQENABLE_3_RESERVED_MAX (0x00007FFFU)
3009 
3010 /* VP_IRQSTATUS_0 */
3011 
3012 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_MASK (0x00000001U)
3013 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_SHIFT (0x00000000U)
3014 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_MAX (0x00000001U)
3015 
3016 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
3017 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_VAL_PEND (0x1U)
3018 
3019 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPVSYNC_IRQ_MASK (0x00000002U)
3020 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPVSYNC_IRQ_SHIFT (0x00000001U)
3021 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPVSYNC_IRQ_MAX (0x00000001U)
3022 
3023 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPVSYNC_IRQ_VAL_NOPEND (0x0U)
3024 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPVSYNC_IRQ_VAL_PEND (0x1U)
3025 
3026 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_MASK (0x00000004U)
3027 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_SHIFT (0x00000002U)
3028 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_MAX (0x00000001U)
3029 
3030 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_VAL_NOPEND (0x0U)
3031 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_VAL_PEND (0x1U)
3032 
3033 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_MASK (0x00000008U)
3034 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_SHIFT (0x00000003U)
3035 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_MAX (0x00000001U)
3036 
3037 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_VAL_NOPEND (0x0U)
3038 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_VAL_PEND (0x1U)
3039 
3040 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_MASK (0x00000010U)
3041 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_SHIFT (0x00000004U)
3042 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_MAX (0x00000001U)
3043 
3044 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_VAL_NOPEND (0x0U)
3045 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_VAL_PEND (0x1U)
3046 
3047 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_MASK (0x00000020U)
3048 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_SHIFT (0x00000005U)
3049 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_MAX (0x00000001U)
3050 
3051 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_VAL_NOPEND (0x0U)
3052 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_VAL_PEND (0x1U)
3053 
3054 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_SAFETYREGION_IRQ_MASK (0x000003C0U)
3055 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_SAFETYREGION_IRQ_SHIFT (0x00000006U)
3056 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_SAFETYREGION_IRQ_MAX (0x0000000FU)
3057 
3058 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
3059 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_PEND (0x1U)
3060 
3061 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_MASK (0x00000400U)
3062 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_SHIFT (0x0000000AU)
3063 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
3064 
3065 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
3066 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
3067 
3068 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPSYNC_IRQ_MASK (0x00000800U)
3069 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPSYNC_IRQ_SHIFT (0x0000000BU)
3070 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPSYNC_IRQ_MAX (0x00000001U)
3071 
3072 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPSYNC_IRQ_VAL_NOPEND (0x0U)
3073 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_VPSYNC_IRQ_VAL_PEND (0x1U)
3074 
3075 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_DUMMY_IRQ_MASK (0x00001000U)
3076 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_DUMMY_IRQ_SHIFT (0x0000000CU)
3077 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_DUMMY_IRQ_MAX (0x00000001U)
3078 
3079 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_DUMMY_IRQ_VAL_NOPEND (0x0U)
3080 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_DUMMY_IRQ_VAL_PEND (0x1U)
3081 
3082 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_SAFETYREGION1_IRQ_MASK (0x0001E000U)
3083 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_SAFETYREGION1_IRQ_SHIFT (0x0000000DU)
3084 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_SAFETYREGION1_IRQ_MAX (0x0000000FU)
3085 
3086 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_SAFETYREGION1_IRQ_VAL_NOPEND (0x0U)
3087 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_SAFETYREGION1_IRQ_VAL_PEND (0x1U)
3088 
3089 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_RESERVED_MASK (0xFFFE0000U)
3090 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_RESERVED_SHIFT (0x00000011U)
3091 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_0_RESERVED_MAX (0x00007FFFU)
3092 
3093 /* VP_IRQSTATUS_1 */
3094 
3095 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_MASK (0x00000001U)
3096 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_SHIFT (0x00000000U)
3097 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_MAX (0x00000001U)
3098 
3099 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
3100 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_VAL_PEND (0x1U)
3101 
3102 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPVSYNC_IRQ_MASK (0x00000002U)
3103 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPVSYNC_IRQ_SHIFT (0x00000001U)
3104 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPVSYNC_IRQ_MAX (0x00000001U)
3105 
3106 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPVSYNC_IRQ_VAL_NOPEND (0x0U)
3107 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPVSYNC_IRQ_VAL_PEND (0x1U)
3108 
3109 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_MASK (0x00000004U)
3110 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_SHIFT (0x00000002U)
3111 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_MAX (0x00000001U)
3112 
3113 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_VAL_NOPEND (0x0U)
3114 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_VAL_PEND (0x1U)
3115 
3116 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_MASK (0x00000008U)
3117 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_SHIFT (0x00000003U)
3118 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_MAX (0x00000001U)
3119 
3120 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_VAL_NOPEND (0x0U)
3121 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_VAL_PEND (0x1U)
3122 
3123 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_MASK (0x00000010U)
3124 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_SHIFT (0x00000004U)
3125 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_MAX (0x00000001U)
3126 
3127 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_VAL_NOPEND (0x0U)
3128 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_VAL_PEND (0x1U)
3129 
3130 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_MASK (0x00000020U)
3131 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_SHIFT (0x00000005U)
3132 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_MAX (0x00000001U)
3133 
3134 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_VAL_NOPEND (0x0U)
3135 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_VAL_PEND (0x1U)
3136 
3137 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_SAFETYREGION_IRQ_MASK (0x000003C0U)
3138 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_SAFETYREGION_IRQ_SHIFT (0x00000006U)
3139 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_SAFETYREGION_IRQ_MAX (0x0000000FU)
3140 
3141 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
3142 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_PEND (0x1U)
3143 
3144 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_MASK (0x00000400U)
3145 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_SHIFT (0x0000000AU)
3146 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
3147 
3148 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
3149 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
3150 
3151 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPSYNC_IRQ_MASK (0x00000800U)
3152 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPSYNC_IRQ_SHIFT (0x0000000BU)
3153 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPSYNC_IRQ_MAX (0x00000001U)
3154 
3155 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPSYNC_IRQ_VAL_NOPEND (0x0U)
3156 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_VPSYNC_IRQ_VAL_PEND (0x1U)
3157 
3158 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_DUMMY_IRQ_MASK (0x00001000U)
3159 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_DUMMY_IRQ_SHIFT (0x0000000CU)
3160 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_DUMMY_IRQ_MAX (0x00000001U)
3161 
3162 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_DUMMY_IRQ_VAL_NOPEND (0x0U)
3163 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_DUMMY_IRQ_VAL_PEND (0x1U)
3164 
3165 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_SAFETYREGION1_IRQ_MASK (0x0001E000U)
3166 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_SAFETYREGION1_IRQ_SHIFT (0x0000000DU)
3167 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_SAFETYREGION1_IRQ_MAX (0x0000000FU)
3168 
3169 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_SAFETYREGION1_IRQ_VAL_NOPEND (0x0U)
3170 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_SAFETYREGION1_IRQ_VAL_PEND (0x1U)
3171 
3172 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_RESERVED_MASK (0xFFFE0000U)
3173 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_RESERVED_SHIFT (0x00000011U)
3174 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_1_RESERVED_MAX (0x00007FFFU)
3175 
3176 /* VP_IRQSTATUS_2 */
3177 
3178 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPFRAMEDONE_IRQ_MASK (0x00000001U)
3179 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPFRAMEDONE_IRQ_SHIFT (0x00000000U)
3180 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPFRAMEDONE_IRQ_MAX (0x00000001U)
3181 
3182 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
3183 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPFRAMEDONE_IRQ_VAL_PEND (0x1U)
3184 
3185 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPVSYNC_IRQ_MASK (0x00000002U)
3186 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPVSYNC_IRQ_SHIFT (0x00000001U)
3187 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPVSYNC_IRQ_MAX (0x00000001U)
3188 
3189 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPVSYNC_IRQ_VAL_NOPEND (0x0U)
3190 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPVSYNC_IRQ_VAL_PEND (0x1U)
3191 
3192 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPVSYNC_ODD_IRQ_MASK (0x00000004U)
3193 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPVSYNC_ODD_IRQ_SHIFT (0x00000002U)
3194 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPVSYNC_ODD_IRQ_MAX (0x00000001U)
3195 
3196 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPVSYNC_ODD_IRQ_VAL_NOPEND (0x0U)
3197 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPVSYNC_ODD_IRQ_VAL_PEND (0x1U)
3198 
3199 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPPROGRAMMEDLINENUMBER_IRQ_MASK (0x00000008U)
3200 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPPROGRAMMEDLINENUMBER_IRQ_SHIFT (0x00000003U)
3201 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPPROGRAMMEDLINENUMBER_IRQ_MAX (0x00000001U)
3202 
3203 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPPROGRAMMEDLINENUMBER_IRQ_VAL_NOPEND (0x0U)
3204 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPPROGRAMMEDLINENUMBER_IRQ_VAL_PEND (0x1U)
3205 
3206 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPSYNCLOST_IRQ_MASK (0x00000010U)
3207 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPSYNCLOST_IRQ_SHIFT (0x00000004U)
3208 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPSYNCLOST_IRQ_MAX (0x00000001U)
3209 
3210 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPSYNCLOST_IRQ_VAL_NOPEND (0x0U)
3211 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPSYNCLOST_IRQ_VAL_PEND (0x1U)
3212 
3213 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_ACBIASCOUNTSTATUS_IRQ_MASK (0x00000020U)
3214 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_ACBIASCOUNTSTATUS_IRQ_SHIFT (0x00000005U)
3215 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_ACBIASCOUNTSTATUS_IRQ_MAX (0x00000001U)
3216 
3217 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_ACBIASCOUNTSTATUS_IRQ_VAL_NOPEND (0x0U)
3218 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_ACBIASCOUNTSTATUS_IRQ_VAL_PEND (0x1U)
3219 
3220 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_SAFETYREGION_IRQ_MASK (0x000003C0U)
3221 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_SAFETYREGION_IRQ_SHIFT (0x00000006U)
3222 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_SAFETYREGION_IRQ_MAX (0x0000000FU)
3223 
3224 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
3225 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_SAFETYREGION_IRQ_VAL_PEND (0x1U)
3226 
3227 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_SECURITYVIOLATION_IRQ_MASK (0x00000400U)
3228 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_SECURITYVIOLATION_IRQ_SHIFT (0x0000000AU)
3229 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
3230 
3231 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
3232 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
3233 
3234 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPSYNC_IRQ_MASK (0x00000800U)
3235 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPSYNC_IRQ_SHIFT (0x0000000BU)
3236 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPSYNC_IRQ_MAX (0x00000001U)
3237 
3238 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPSYNC_IRQ_VAL_NOPEND (0x0U)
3239 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_VPSYNC_IRQ_VAL_PEND (0x1U)
3240 
3241 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_DUMMY_IRQ_MASK (0x00001000U)
3242 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_DUMMY_IRQ_SHIFT (0x0000000CU)
3243 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_DUMMY_IRQ_MAX (0x00000001U)
3244 
3245 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_DUMMY_IRQ_VAL_NOPEND (0x0U)
3246 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_DUMMY_IRQ_VAL_PEND (0x1U)
3247 
3248 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_SAFETYREGION1_IRQ_MASK (0x0001E000U)
3249 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_SAFETYREGION1_IRQ_SHIFT (0x0000000DU)
3250 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_SAFETYREGION1_IRQ_MAX (0x0000000FU)
3251 
3252 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_SAFETYREGION1_IRQ_VAL_NOPEND (0x0U)
3253 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_SAFETYREGION1_IRQ_VAL_PEND (0x1U)
3254 
3255 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_RESERVED_MASK (0xFFFE0000U)
3256 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_RESERVED_SHIFT (0x00000011U)
3257 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_2_RESERVED_MAX (0x00007FFFU)
3258 
3259 /* VP_IRQSTATUS_3 */
3260 
3261 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPFRAMEDONE_IRQ_MASK (0x00000001U)
3262 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPFRAMEDONE_IRQ_SHIFT (0x00000000U)
3263 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPFRAMEDONE_IRQ_MAX (0x00000001U)
3264 
3265 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
3266 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPFRAMEDONE_IRQ_VAL_PEND (0x1U)
3267 
3268 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPVSYNC_IRQ_MASK (0x00000002U)
3269 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPVSYNC_IRQ_SHIFT (0x00000001U)
3270 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPVSYNC_IRQ_MAX (0x00000001U)
3271 
3272 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPVSYNC_IRQ_VAL_NOPEND (0x0U)
3273 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPVSYNC_IRQ_VAL_PEND (0x1U)
3274 
3275 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPVSYNC_ODD_IRQ_MASK (0x00000004U)
3276 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPVSYNC_ODD_IRQ_SHIFT (0x00000002U)
3277 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPVSYNC_ODD_IRQ_MAX (0x00000001U)
3278 
3279 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPVSYNC_ODD_IRQ_VAL_NOPEND (0x0U)
3280 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPVSYNC_ODD_IRQ_VAL_PEND (0x1U)
3281 
3282 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPPROGRAMMEDLINENUMBER_IRQ_MASK (0x00000008U)
3283 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPPROGRAMMEDLINENUMBER_IRQ_SHIFT (0x00000003U)
3284 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPPROGRAMMEDLINENUMBER_IRQ_MAX (0x00000001U)
3285 
3286 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPPROGRAMMEDLINENUMBER_IRQ_VAL_NOPEND (0x0U)
3287 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPPROGRAMMEDLINENUMBER_IRQ_VAL_PEND (0x1U)
3288 
3289 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPSYNCLOST_IRQ_MASK (0x00000010U)
3290 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPSYNCLOST_IRQ_SHIFT (0x00000004U)
3291 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPSYNCLOST_IRQ_MAX (0x00000001U)
3292 
3293 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPSYNCLOST_IRQ_VAL_NOPEND (0x0U)
3294 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPSYNCLOST_IRQ_VAL_PEND (0x1U)
3295 
3296 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_ACBIASCOUNTSTATUS_IRQ_MASK (0x00000020U)
3297 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_ACBIASCOUNTSTATUS_IRQ_SHIFT (0x00000005U)
3298 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_ACBIASCOUNTSTATUS_IRQ_MAX (0x00000001U)
3299 
3300 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_ACBIASCOUNTSTATUS_IRQ_VAL_NOPEND (0x0U)
3301 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_ACBIASCOUNTSTATUS_IRQ_VAL_PEND (0x1U)
3302 
3303 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_SAFETYREGION_IRQ_MASK (0x000003C0U)
3304 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_SAFETYREGION_IRQ_SHIFT (0x00000006U)
3305 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_SAFETYREGION_IRQ_MAX (0x0000000FU)
3306 
3307 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
3308 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_SAFETYREGION_IRQ_VAL_PEND (0x1U)
3309 
3310 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_SECURITYVIOLATION_IRQ_MASK (0x00000400U)
3311 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_SECURITYVIOLATION_IRQ_SHIFT (0x0000000AU)
3312 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
3313 
3314 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
3315 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
3316 
3317 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPSYNC_IRQ_MASK (0x00000800U)
3318 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPSYNC_IRQ_SHIFT (0x0000000BU)
3319 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPSYNC_IRQ_MAX (0x00000001U)
3320 
3321 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPSYNC_IRQ_VAL_NOPEND (0x0U)
3322 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_VPSYNC_IRQ_VAL_PEND (0x1U)
3323 
3324 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_DUMMY_IRQ_MASK (0x00001000U)
3325 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_DUMMY_IRQ_SHIFT (0x0000000CU)
3326 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_DUMMY_IRQ_MAX (0x00000001U)
3327 
3328 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_DUMMY_IRQ_VAL_NOPEND (0x0U)
3329 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_DUMMY_IRQ_VAL_PEND (0x1U)
3330 
3331 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_SAFETYREGION1_IRQ_MASK (0x0001E000U)
3332 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_SAFETYREGION1_IRQ_SHIFT (0x0000000DU)
3333 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_SAFETYREGION1_IRQ_MAX (0x0000000FU)
3334 
3335 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_SAFETYREGION1_IRQ_VAL_NOPEND (0x0U)
3336 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_SAFETYREGION1_IRQ_VAL_PEND (0x1U)
3337 
3338 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_RESERVED_MASK (0xFFFE0000U)
3339 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_RESERVED_SHIFT (0x00000011U)
3340 #define CSL_DSS_COMMON_S0_VP_IRQSTATUS_3_RESERVED_MAX (0x00007FFFU)
3341 
3342 /* WB_IRQENABLE */
3343 
3344 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_WBBUFFEROVERFLOW_EN_MASK (0x00000001U)
3345 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_WBBUFFEROVERFLOW_EN_SHIFT (0x00000000U)
3346 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_WBBUFFEROVERFLOW_EN_MAX (0x00000001U)
3347 
3348 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_WBBUFFEROVERFLOW_EN_VAL_MASKED (0x0U)
3349 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_WBBUFFEROVERFLOW_EN_VAL_GENINT (0x1U)
3350 
3351 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_WBUNCOMPLETEERROR_EN_MASK (0x00000002U)
3352 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_WBUNCOMPLETEERROR_EN_SHIFT (0x00000001U)
3353 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_WBUNCOMPLETEERROR_EN_MAX (0x00000001U)
3354 
3355 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_WBUNCOMPLETEERROR_EN_VAL_MASKED (0x0U)
3356 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_WBUNCOMPLETEERROR_EN_VAL_GENINT (0x1U)
3357 
3358 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_WBFRAMEDONE_EN_MASK (0x00000004U)
3359 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_WBFRAMEDONE_EN_SHIFT (0x00000002U)
3360 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_WBFRAMEDONE_EN_MAX (0x00000001U)
3361 
3362 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_WBFRAMEDONE_EN_VAL_MASKED (0x0U)
3363 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_WBFRAMEDONE_EN_VAL_GENINT (0x1U)
3364 
3365 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_SECURITYVIOLATION_EN_MASK (0x00000008U)
3366 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_SECURITYVIOLATION_EN_SHIFT (0x00000003U)
3367 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_SECURITYVIOLATION_EN_MAX (0x00000001U)
3368 
3369 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
3370 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
3371 
3372 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_WBSYNC_EN_MASK (0x00000010U)
3373 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_WBSYNC_EN_SHIFT (0x00000004U)
3374 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_WBSYNC_EN_MAX (0x00000001U)
3375 
3376 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_WBSYNC_EN_VAL_MASKED (0x0U)
3377 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_WBSYNC_EN_VAL_GENINT (0x1U)
3378 
3379 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_RESERVED_MASK (0xFFFFFFE0U)
3380 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_RESERVED_SHIFT (0x00000005U)
3381 #define CSL_DSS_COMMON_S0_WB_IRQENABLE_RESERVED_MAX (0x07FFFFFFU)
3382 
3383 /* WB_IRQSTATUS */
3384 
3385 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_WBBUFFEROVERFLOW_IRQ_MASK (0x00000001U)
3386 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_WBBUFFEROVERFLOW_IRQ_SHIFT (0x00000000U)
3387 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_WBBUFFEROVERFLOW_IRQ_MAX (0x00000001U)
3388 
3389 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_WBBUFFEROVERFLOW_IRQ_VAL_NOPEND (0x0U)
3390 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_WBBUFFEROVERFLOW_IRQ_VAL_PEND (0x1U)
3391 
3392 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_WBUNCOMPLETEERROR_IRQ_MASK (0x00000002U)
3393 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_WBUNCOMPLETEERROR_IRQ_SHIFT (0x00000001U)
3394 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_WBUNCOMPLETEERROR_IRQ_MAX (0x00000001U)
3395 
3396 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_WBUNCOMPLETEERROR_IRQ_VAL_NOPEND (0x0U)
3397 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_WBUNCOMPLETEERROR_IRQ_VAL_PEND (0x1U)
3398 
3399 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_WBFRAMEDONE_IRQ_MASK (0x00000004U)
3400 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_WBFRAMEDONE_IRQ_SHIFT (0x00000002U)
3401 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_WBFRAMEDONE_IRQ_MAX (0x00000001U)
3402 
3403 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_WBFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
3404 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_WBFRAMEDONE_IRQ_VAL_PEND (0x1U)
3405 
3406 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_SECURITYVIOLATION_IRQ_MASK (0x00000008U)
3407 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_SECURITYVIOLATION_IRQ_SHIFT (0x00000003U)
3408 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
3409 
3410 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
3411 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
3412 
3413 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_WBSYNC_IRQ_MASK (0x00000010U)
3414 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_WBSYNC_IRQ_SHIFT (0x00000004U)
3415 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_WBSYNC_IRQ_MAX (0x00000001U)
3416 
3417 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_WBSYNC_IRQ_VAL_NOPEND (0x0U)
3418 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_WBSYNC_IRQ_VAL_PEND (0x1U)
3419 
3420 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_RESERVED_MASK (0xFFFFFFE0U)
3421 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_RESERVED_SHIFT (0x00000005U)
3422 #define CSL_DSS_COMMON_S0_WB_IRQSTATUS_RESERVED_MAX (0x07FFFFFFU)
3423 
3424 /* DISPC_IRQ_EOI_FUNC */
3425 
3426 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_FUNC_EOI_MASK (0x00000001U)
3427 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_FUNC_EOI_SHIFT (0x00000000U)
3428 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_FUNC_EOI_MAX (0x00000001U)
3429 
3430 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_FUNC_EOI_VAL_NOACTION (0x0U)
3431 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_FUNC_EOI_VAL_EOI (0x1U)
3432 
3433 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_FUNC_RESERVED_MASK (0xFFFFFFFEU)
3434 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_FUNC_RESERVED_SHIFT (0x00000001U)
3435 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_FUNC_RESERVED_MAX (0x7FFFFFFFU)
3436 
3437 /* DISPC_IRQ_EOI_SAFETY */
3438 
3439 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_SAFETY_EOI_MASK (0x00000001U)
3440 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_SAFETY_EOI_SHIFT (0x00000000U)
3441 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_SAFETY_EOI_MAX (0x00000001U)
3442 
3443 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_SAFETY_EOI_VAL_NOACTION (0x0U)
3444 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_SAFETY_EOI_VAL_EOI (0x1U)
3445 
3446 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_SAFETY_RESERVED_MASK (0xFFFFFFFEU)
3447 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_SAFETY_RESERVED_SHIFT (0x00000001U)
3448 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_SAFETY_RESERVED_MAX (0x7FFFFFFFU)
3449 
3450 /* DISPC_IRQ_EOI_SECURITY */
3451 
3452 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_SECURITY_EOI_MASK (0x00000001U)
3453 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_SECURITY_EOI_SHIFT (0x00000000U)
3454 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_SECURITY_EOI_MAX (0x00000001U)
3455 
3456 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_SECURITY_EOI_VAL_NOACTION (0x0U)
3457 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_SECURITY_EOI_VAL_EOI (0x1U)
3458 
3459 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_SECURITY_RESERVED_MASK (0xFFFFFFFEU)
3460 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_SECURITY_RESERVED_SHIFT (0x00000001U)
3461 #define CSL_DSS_COMMON_S0_DISPC_IRQ_EOI_SECURITY_RESERVED_MAX (0x7FFFFFFFU)
3462 
3463 /**************************************************************************
3464 * Hardware Region : VIDL1 Registers
3465 **************************************************************************/
3466 
3467 
3468 /**************************************************************************
3469 * Register Overlay Structure
3470 **************************************************************************/
3471 
3472 typedef struct {
3473  volatile uint8_t Resv_32[32];
3474  volatile uint32_t ATTRIBUTES; /* ATTRIBUTES */
3475  volatile uint32_t ATTRIBUTES2; /* ATTRIBUTES2 */
3476  volatile uint32_t BA_0; /* BA_0 */
3477  volatile uint32_t BA_1; /* BA_1 */
3478  volatile uint32_t BA_UV_0; /* BA_UV_0 */
3479  volatile uint32_t BA_UV_1; /* BA_UV_1 */
3480  volatile uint32_t BUF_SIZE_STATUS; /* BUF_SIZE_STATUS */
3481  volatile uint32_t BUF_THRESHOLD; /* BUF_THRESHOLD */
3482  volatile uint32_t CSC_COEF0; /* CSC_COEF0 */
3483  volatile uint32_t CSC_COEF1; /* CSC_COEF1 */
3484  volatile uint32_t CSC_COEF2; /* CSC_COEF2 */
3485  volatile uint32_t CSC_COEF3; /* CSC_COEF3 */
3486  volatile uint32_t CSC_COEF4; /* CSC_COEF4 */
3487  volatile uint32_t CSC_COEF5; /* CSC_COEF5 */
3488  volatile uint32_t CSC_COEF6; /* CSC_COEF6 */
3489  volatile uint8_t Resv_508[416];
3490  volatile uint32_t GLOBAL_ALPHA; /* GLOBAL_ALPHA */
3491  volatile uint8_t Resv_520[8];
3492  volatile uint32_t MFLAG_THRESHOLD; /* MFLAG_THRESHOLD */
3493  volatile uint32_t PICTURE_SIZE; /* PICTURE_SIZE */
3494  volatile uint32_t PIXEL_INC; /* PIXEL_INC */
3495  volatile uint8_t Resv_536[4];
3496  volatile uint32_t PRELOAD; /* PRELOAD */
3497  volatile uint32_t ROW_INC; /* ROW_INC */
3498  volatile uint8_t Resv_556[12];
3499  volatile uint32_t BA_EXT_0; /* BA_EXT_0 */
3500  volatile uint32_t BA_EXT_1; /* BA_EXT_1 */
3501  volatile uint32_t BA_UV_EXT_0; /* BA_UV_EXT_0 */
3502  volatile uint32_t BA_UV_EXT_1; /* BA_UV_EXT_1 */
3503  volatile uint32_t CSC_COEF7; /* CSC_COEF7 */
3504  volatile uint8_t Resv_584[8];
3505  volatile uint32_t ROW_INC_UV; /* ROW_INC_UV */
3506  volatile uint32_t TILE; /* TILE */
3507  volatile uint32_t TILE2; /* TILE2 */
3508  volatile uint32_t FBDC_ATTRIBUTES; /* FBDC_ATTRIBUTES */
3509  volatile uint32_t FBDC_CLEAR_COLOR; /* FBDC_CLEAR_COLOR */
3510  volatile uint8_t Resv_608[4];
3511  volatile uint32_t CLUT_0; /* CLUT_0 */
3512  volatile uint32_t CLUT_1; /* CLUT_1 */
3513  volatile uint32_t CLUT_2; /* CLUT_2 */
3514  volatile uint32_t CLUT_3; /* CLUT_3 */
3515  volatile uint32_t CLUT_4; /* CLUT_4 */
3516  volatile uint32_t CLUT_5; /* CLUT_5 */
3517  volatile uint32_t CLUT_6; /* CLUT_6 */
3518  volatile uint32_t CLUT_7; /* CLUT_7 */
3519  volatile uint32_t CLUT_8; /* CLUT_8 */
3520  volatile uint32_t CLUT_9; /* CLUT_9 */
3521  volatile uint32_t CLUT_10; /* CLUT_10 */
3522  volatile uint32_t CLUT_11; /* CLUT_11 */
3523  volatile uint32_t CLUT_12; /* CLUT_12 */
3524  volatile uint32_t CLUT_13; /* CLUT_13 */
3525  volatile uint32_t CLUT_14; /* CLUT_14 */
3526  volatile uint32_t CLUT_15; /* CLUT_15 */
3527  volatile uint32_t SAFETY_ATTRIBUTES; /* SAFETY_ATTRIBUTES */
3528  volatile uint32_t SAFETY_CAPT_SIGNATURE; /* SAFETY_CAPT_SIGNATURE */
3529  volatile uint32_t SAFETY_POSITION; /* SAFETY_POSITION */
3530  volatile uint32_t SAFETY_REF_SIGNATURE; /* SAFETY_REF_SIGNATURE */
3531  volatile uint32_t SAFETY_SIZE; /* SAFETY_SIZE */
3532  volatile uint32_t SAFETY_LFSR_SEED; /* SAFETY_LFSR_SEED */
3533  volatile uint32_t LUMAKEY; /* LUMAKEY */
3534  volatile uint32_t DMA_BUFSIZE; /* DMA_BUFSIZE */
3535  volatile uint32_t CROP; /* CROP */
3536  volatile uint32_t SECURE; /* SECURE */
3537  volatile uint32_t PIPE_GO; /* PIPE_GO */
3539 
3540 
3541 /**************************************************************************
3542 * Register Macros
3543 **************************************************************************/
3544 
3545 #define CSL_DSS_VIDL1_ATTRIBUTES (0x00000020U)
3546 #define CSL_DSS_VIDL1_ATTRIBUTES2 (0x00000024U)
3547 #define CSL_DSS_VIDL1_BA_0 (0x00000028U)
3548 #define CSL_DSS_VIDL1_BA_1 (0x0000002CU)
3549 #define CSL_DSS_VIDL1_BA_UV_0 (0x00000030U)
3550 #define CSL_DSS_VIDL1_BA_UV_1 (0x00000034U)
3551 #define CSL_DSS_VIDL1_BUF_SIZE_STATUS (0x00000038U)
3552 #define CSL_DSS_VIDL1_BUF_THRESHOLD (0x0000003CU)
3553 #define CSL_DSS_VIDL1_CSC_COEF0 (0x00000040U)
3554 #define CSL_DSS_VIDL1_CSC_COEF1 (0x00000044U)
3555 #define CSL_DSS_VIDL1_CSC_COEF2 (0x00000048U)
3556 #define CSL_DSS_VIDL1_CSC_COEF3 (0x0000004CU)
3557 #define CSL_DSS_VIDL1_CSC_COEF4 (0x00000050U)
3558 #define CSL_DSS_VIDL1_CSC_COEF5 (0x00000054U)
3559 #define CSL_DSS_VIDL1_CSC_COEF6 (0x00000058U)
3560 #define CSL_DSS_VIDL1_GLOBAL_ALPHA (0x000001FCU)
3561 #define CSL_DSS_VIDL1_MFLAG_THRESHOLD (0x00000208U)
3562 #define CSL_DSS_VIDL1_PICTURE_SIZE (0x0000020CU)
3563 #define CSL_DSS_VIDL1_PIXEL_INC (0x00000210U)
3564 #define CSL_DSS_VIDL1_PRELOAD (0x00000218U)
3565 #define CSL_DSS_VIDL1_ROW_INC (0x0000021CU)
3566 #define CSL_DSS_VIDL1_BA_EXT_0 (0x0000022CU)
3567 #define CSL_DSS_VIDL1_BA_EXT_1 (0x00000230U)
3568 #define CSL_DSS_VIDL1_BA_UV_EXT_0 (0x00000234U)
3569 #define CSL_DSS_VIDL1_BA_UV_EXT_1 (0x00000238U)
3570 #define CSL_DSS_VIDL1_CSC_COEF7 (0x0000023CU)
3571 #define CSL_DSS_VIDL1_ROW_INC_UV (0x00000248U)
3572 #define CSL_DSS_VIDL1_TILE (0x0000024CU)
3573 #define CSL_DSS_VIDL1_TILE2 (0x00000250U)
3574 #define CSL_DSS_VIDL1_FBDC_ATTRIBUTES (0x00000254U)
3575 #define CSL_DSS_VIDL1_FBDC_CLEAR_COLOR (0x00000258U)
3576 #define CSL_DSS_VIDL1_CLUT_0 (0x00000260U)
3577 #define CSL_DSS_VIDL1_CLUT_1 (0x00000264U)
3578 #define CSL_DSS_VIDL1_CLUT_2 (0x00000268U)
3579 #define CSL_DSS_VIDL1_CLUT_3 (0x0000026CU)
3580 #define CSL_DSS_VIDL1_CLUT_4 (0x00000270U)
3581 #define CSL_DSS_VIDL1_CLUT_5 (0x00000274U)
3582 #define CSL_DSS_VIDL1_CLUT_6 (0x00000278U)
3583 #define CSL_DSS_VIDL1_CLUT_7 (0x0000027CU)
3584 #define CSL_DSS_VIDL1_CLUT_8 (0x00000280U)
3585 #define CSL_DSS_VIDL1_CLUT_9 (0x00000284U)
3586 #define CSL_DSS_VIDL1_CLUT_10 (0x00000288U)
3587 #define CSL_DSS_VIDL1_CLUT_11 (0x0000028CU)
3588 #define CSL_DSS_VIDL1_CLUT_12 (0x00000290U)
3589 #define CSL_DSS_VIDL1_CLUT_13 (0x00000294U)
3590 #define CSL_DSS_VIDL1_CLUT_14 (0x00000298U)
3591 #define CSL_DSS_VIDL1_CLUT_15 (0x0000029CU)
3592 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES (0x000002A0U)
3593 #define CSL_DSS_VIDL1_SAFETY_CAPT_SIGNATURE (0x000002A4U)
3594 #define CSL_DSS_VIDL1_SAFETY_POSITION (0x000002A8U)
3595 #define CSL_DSS_VIDL1_SAFETY_REF_SIGNATURE (0x000002ACU)
3596 #define CSL_DSS_VIDL1_SAFETY_SIZE (0x000002B0U)
3597 #define CSL_DSS_VIDL1_SAFETY_LFSR_SEED (0x000002B4U)
3598 #define CSL_DSS_VIDL1_LUMAKEY (0x000002B8U)
3599 #define CSL_DSS_VIDL1_DMA_BUFSIZE (0x000002BCU)
3600 #define CSL_DSS_VIDL1_CROP (0x000002C0U)
3601 #define CSL_DSS_VIDL1_SECURE (0x000002C4U)
3602 #define CSL_DSS_VIDL1_PIPE_GO (0x000002C8U)
3603 
3604 /**************************************************************************
3605 * Field Definition Macros
3606 **************************************************************************/
3607 
3608 
3609 /* ATTRIBUTES */
3610 
3611 #define CSL_DSS_VIDL1_ATTRIBUTES_ENABLE_MASK (0x00000001U)
3612 #define CSL_DSS_VIDL1_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
3613 #define CSL_DSS_VIDL1_ATTRIBUTES_ENABLE_MAX (0x00000001U)
3614 
3615 #define CSL_DSS_VIDL1_ATTRIBUTES_ENABLE_VAL_VIDEOENB (0x1U)
3616 #define CSL_DSS_VIDL1_ATTRIBUTES_ENABLE_VAL_VIDEODIS (0x0U)
3617 
3618 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_MASK (0x0000007EU)
3619 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_SHIFT (0x00000001U)
3620 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_MAX (0x0000003FU)
3621 
3622 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ARGB16_4444 (0x0U)
3623 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ABGR16_4444 (0x1U)
3624 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGBA16_4444 (0x2U)
3625 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGB16_565 (0x3U)
3626 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BGR16_565 (0x4U)
3627 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ARGB16_1555 (0x5U)
3628 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ABGR16_1555 (0x6U)
3629 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ARGB32_8888 (0x7U)
3630 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ABGR32_8888 (0x8U)
3631 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGBA32_8888 (0x9U)
3632 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BGRA32_8888 (0xAU)
3633 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGB24P_888 (0xBU)
3634 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BGR24P_888 (0xCU)
3635 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ARGB32_2101010 (0xEU)
3636 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ABGR32_2101010 (0xFU)
3637 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ARGB64_16161616 (0x10U)
3638 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGBA64_16161616 (0x11U)
3639 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BITMAP1 (0x12U)
3640 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BITMAP2 (0x13U)
3641 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BITMAP4 (0x14U)
3642 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BITMAP8 (0x15U)
3643 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGB565A8 (0x16U)
3644 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BGR565A8 (0x17U)
3645 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XRGB16_4444 (0x20U)
3646 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XBGR16_4444 (0x21U)
3647 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGBX16_4444 (0x22U)
3648 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XRGB16_1555 (0x25U)
3649 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XBGR16_1555 (0x26U)
3650 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XRGB32_8888 (0x27U)
3651 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XBGR32_8888 (0x28U)
3652 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGBX32_8888 (0x29U)
3653 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BGRX32_8888 (0x2AU)
3654 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XRGB32_2101010 (0x2EU)
3655 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XBGR32_2101010 (0x2FU)
3656 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XRGB64_16161616 (0x30U)
3657 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGBX64_16161616 (0x31U)
3658 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_YUV422_NV12 (0x3CU)
3659 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_YUV420_NV12 (0x3DU)
3660 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_YUV422_YUV2 (0x3EU)
3661 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_YUV422_UYVY (0x3FU)
3662 
3663 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED8_MASK (0x00000180U)
3664 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED8_SHIFT (0x00000007U)
3665 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED8_MAX (0x00000003U)
3666 
3667 #define CSL_DSS_VIDL1_ATTRIBUTES_COLORCONVENABLE_MASK (0x00000200U)
3668 #define CSL_DSS_VIDL1_ATTRIBUTES_COLORCONVENABLE_SHIFT (0x00000009U)
3669 #define CSL_DSS_VIDL1_ATTRIBUTES_COLORCONVENABLE_MAX (0x00000001U)
3670 
3671 #define CSL_DSS_VIDL1_ATTRIBUTES_COLORCONVENABLE_VAL_COLSPCENB (0x1U)
3672 #define CSL_DSS_VIDL1_ATTRIBUTES_COLORCONVENABLE_VAL_COLSPCDIS (0x0U)
3673 
3674 #define CSL_DSS_VIDL1_ATTRIBUTES_NIBBLEMODE_MASK (0x00000400U)
3675 #define CSL_DSS_VIDL1_ATTRIBUTES_NIBBLEMODE_SHIFT (0x0000000AU)
3676 #define CSL_DSS_VIDL1_ATTRIBUTES_NIBBLEMODE_MAX (0x00000001U)
3677 
3678 #define CSL_DSS_VIDL1_ATTRIBUTES_NIBBLEMODE_VAL_NIBBLEMODEEN (0x1U)
3679 #define CSL_DSS_VIDL1_ATTRIBUTES_NIBBLEMODE_VAL_NIBBLEMODEDIS (0x0U)
3680 
3681 #define CSL_DSS_VIDL1_ATTRIBUTES_FULLRANGE_MASK (0x00000800U)
3682 #define CSL_DSS_VIDL1_ATTRIBUTES_FULLRANGE_SHIFT (0x0000000BU)
3683 #define CSL_DSS_VIDL1_ATTRIBUTES_FULLRANGE_MAX (0x00000001U)
3684 
3685 #define CSL_DSS_VIDL1_ATTRIBUTES_FULLRANGE_VAL_FULLRANGE (0x1U)
3686 #define CSL_DSS_VIDL1_ATTRIBUTES_FULLRANGE_VAL_LIMRANGE (0x0U)
3687 
3688 #define CSL_DSS_VIDL1_ATTRIBUTES_FLIP_MASK (0x00001000U)
3689 #define CSL_DSS_VIDL1_ATTRIBUTES_FLIP_SHIFT (0x0000000CU)
3690 #define CSL_DSS_VIDL1_ATTRIBUTES_FLIP_MAX (0x00000001U)
3691 
3692 #define CSL_DSS_VIDL1_ATTRIBUTES_FLIP_VAL_FLIP (0x1U)
3693 #define CSL_DSS_VIDL1_ATTRIBUTES_FLIP_VAL_NOFLIP (0x0U)
3694 
3695 #define CSL_DSS_VIDL1_ATTRIBUTES_CROP_MASK (0x00002000U)
3696 #define CSL_DSS_VIDL1_ATTRIBUTES_CROP_SHIFT (0x0000000DU)
3697 #define CSL_DSS_VIDL1_ATTRIBUTES_CROP_MAX (0x00000001U)
3698 
3699 #define CSL_DSS_VIDL1_ATTRIBUTES_CROP_VAL_CROPEN (0x1U)
3700 #define CSL_DSS_VIDL1_ATTRIBUTES_CROP_VAL_CROPDIS (0x0U)
3701 
3702 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED9_MASK (0x0001C000U)
3703 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED9_SHIFT (0x0000000EU)
3704 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED9_MAX (0x00000007U)
3705 
3706 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESHAUTO_MASK (0x00020000U)
3707 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESHAUTO_SHIFT (0x00000011U)
3708 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESHAUTO_MAX (0x00000001U)
3709 
3710 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESHAUTO_VAL_SELFREFRESHAUTOEN (0x1U)
3711 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESHAUTO_VAL_SELFREFRESHAUTODIS (0x0U)
3712 
3713 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED7_MASK (0x00040000U)
3714 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED7_SHIFT (0x00000012U)
3715 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED7_MAX (0x00000001U)
3716 
3717 #define CSL_DSS_VIDL1_ATTRIBUTES_BUFPRELOAD_MASK (0x00080000U)
3718 #define CSL_DSS_VIDL1_ATTRIBUTES_BUFPRELOAD_SHIFT (0x00000013U)
3719 #define CSL_DSS_VIDL1_ATTRIBUTES_BUFPRELOAD_MAX (0x00000001U)
3720 
3721 #define CSL_DSS_VIDL1_ATTRIBUTES_BUFPRELOAD_VAL_HIGHTHRES (0x1U)
3722 #define CSL_DSS_VIDL1_ATTRIBUTES_BUFPRELOAD_VAL_DEFVAL (0x0U)
3723 
3724 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED2_MASK (0x00100000U)
3725 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED2_SHIFT (0x00000014U)
3726 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED2_MAX (0x00000001U)
3727 
3728 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED3_MASK (0x00200000U)
3729 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED3_SHIFT (0x00000015U)
3730 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED3_MAX (0x00000001U)
3731 
3732 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED6_MASK (0x00400000U)
3733 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED6_SHIFT (0x00000016U)
3734 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED6_MAX (0x00000001U)
3735 
3736 #define CSL_DSS_VIDL1_ATTRIBUTES_ARBITRATION_MASK (0x00800000U)
3737 #define CSL_DSS_VIDL1_ATTRIBUTES_ARBITRATION_SHIFT (0x00000017U)
3738 #define CSL_DSS_VIDL1_ATTRIBUTES_ARBITRATION_MAX (0x00000001U)
3739 
3740 #define CSL_DSS_VIDL1_ATTRIBUTES_ARBITRATION_VAL_HIGHPRIO (0x1U)
3741 #define CSL_DSS_VIDL1_ATTRIBUTES_ARBITRATION_VAL_NORMALPRIO (0x0U)
3742 
3743 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESH_MASK (0x01000000U)
3744 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESH_SHIFT (0x00000018U)
3745 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESH_MAX (0x00000001U)
3746 
3747 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESH_VAL_SELFREFRESHENB (0x1U)
3748 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESH_VAL_SELFREFRESHDIS (0x0U)
3749 
3750 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED5_MASK (0x0E000000U)
3751 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED5_SHIFT (0x00000019U)
3752 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED5_MAX (0x00000007U)
3753 
3754 #define CSL_DSS_VIDL1_ATTRIBUTES_PREMULTIPLYALPHA_MASK (0x10000000U)
3755 #define CSL_DSS_VIDL1_ATTRIBUTES_PREMULTIPLYALPHA_SHIFT (0x0000001CU)
3756 #define CSL_DSS_VIDL1_ATTRIBUTES_PREMULTIPLYALPHA_MAX (0x00000001U)
3757 
3758 #define CSL_DSS_VIDL1_ATTRIBUTES_PREMULTIPLYALPHA_VAL_PREMULTIPLIEDALPHA (0x1U)
3759 #define CSL_DSS_VIDL1_ATTRIBUTES_PREMULTIPLYALPHA_VAL_NONPREMULTIPLIEDALPHA (0x0U)
3760 
3761 #define CSL_DSS_VIDL1_ATTRIBUTES_GAMMAINVERSIONPOS_MASK (0x20000000U)
3762 #define CSL_DSS_VIDL1_ATTRIBUTES_GAMMAINVERSIONPOS_SHIFT (0x0000001DU)
3763 #define CSL_DSS_VIDL1_ATTRIBUTES_GAMMAINVERSIONPOS_MAX (0x00000001U)
3764 
3765 #define CSL_DSS_VIDL1_ATTRIBUTES_GAMMAINVERSIONPOS_VAL_PRESCALER (0x0U)
3766 #define CSL_DSS_VIDL1_ATTRIBUTES_GAMMAINVERSIONPOS_VAL_POSTSCALER (0x1U)
3767 
3768 #define CSL_DSS_VIDL1_ATTRIBUTES_GAMMAINVERSION_MASK (0x40000000U)
3769 #define CSL_DSS_VIDL1_ATTRIBUTES_GAMMAINVERSION_SHIFT (0x0000001EU)
3770 #define CSL_DSS_VIDL1_ATTRIBUTES_GAMMAINVERSION_MAX (0x00000001U)
3771 
3772 #define CSL_DSS_VIDL1_ATTRIBUTES_GAMMAINVERSION_VAL_INVGAMMAEN (0x1U)
3773 #define CSL_DSS_VIDL1_ATTRIBUTES_GAMMAINVERSION_VAL_INVGAMMADIS (0x0U)
3774 
3775 #define CSL_DSS_VIDL1_ATTRIBUTES_LUMAKEYENABLE_MASK (0x80000000U)
3776 #define CSL_DSS_VIDL1_ATTRIBUTES_LUMAKEYENABLE_SHIFT (0x0000001FU)
3777 #define CSL_DSS_VIDL1_ATTRIBUTES_LUMAKEYENABLE_MAX (0x00000001U)
3778 
3779 #define CSL_DSS_VIDL1_ATTRIBUTES_LUMAKEYENABLE_VAL_LUMAKEYEN (0x1U)
3780 #define CSL_DSS_VIDL1_ATTRIBUTES_LUMAKEYENABLE_VAL_LUMAKEYDIS (0x0U)
3781 
3782 /* ATTRIBUTES2 */
3783 
3784 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1ENABLE_MASK (0x00000001U)
3785 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1ENABLE_SHIFT (0x00000000U)
3786 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1ENABLE_MAX (0x00000001U)
3787 
3788 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1ENABLE_VAL_VC1ENB (0x1U)
3789 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1ENABLE_VAL_VC1DIS (0x0U)
3790 
3791 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1_RANGE_Y_MASK (0x0000000EU)
3792 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1_RANGE_Y_SHIFT (0x00000001U)
3793 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1_RANGE_Y_MAX (0x00000007U)
3794 
3795 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1_RANGE_CBCR_MASK (0x00000070U)
3796 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1_RANGE_CBCR_SHIFT (0x00000004U)
3797 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1_RANGE_CBCR_MAX (0x00000007U)
3798 
3799 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_SIZE_MASK (0x00000180U)
3800 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_SIZE_SHIFT (0x00000007U)
3801 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_SIZE_MAX (0x00000003U)
3802 
3803 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_SIZE_VAL_8B (0x0U)
3804 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_SIZE_VAL_10B (0x1U)
3805 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_SIZE_VAL_12B (0x2U)
3806 
3807 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_MODE_MASK (0x00000200U)
3808 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_MODE_SHIFT (0x00000009U)
3809 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_MODE_MAX (0x00000001U)
3810 
3811 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_MODE_VAL_PACKED (0x0U)
3812 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_MODE_VAL_UNPACKED (0x1U)
3813 
3814 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_ALIGN_MASK (0x00000400U)
3815 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_ALIGN_SHIFT (0x0000000AU)
3816 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_ALIGN_MAX (0x00000001U)
3817 
3818 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_ALIGN_VAL_MSB (0x1U)
3819 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_ALIGN_VAL_LSB (0x0U)
3820 
3821 #define CSL_DSS_VIDL1_ATTRIBUTES2_RESERVED1_MASK (0x0000F800U)
3822 #define CSL_DSS_VIDL1_ATTRIBUTES2_RESERVED1_SHIFT (0x0000000BU)
3823 #define CSL_DSS_VIDL1_ATTRIBUTES2_RESERVED1_MAX (0x0000001FU)
3824 
3825 #define CSL_DSS_VIDL1_ATTRIBUTES2_RESERVED2_MASK (0x01F00000U)
3826 #define CSL_DSS_VIDL1_ATTRIBUTES2_RESERVED2_SHIFT (0x00000014U)
3827 #define CSL_DSS_VIDL1_ATTRIBUTES2_RESERVED2_MAX (0x0000001FU)
3828 
3829 #define CSL_DSS_VIDL1_ATTRIBUTES2_MPORTSEL_MASK (0x02000000U)
3830 #define CSL_DSS_VIDL1_ATTRIBUTES2_MPORTSEL_SHIFT (0x00000019U)
3831 #define CSL_DSS_VIDL1_ATTRIBUTES2_MPORTSEL_MAX (0x00000001U)
3832 
3833 #define CSL_DSS_VIDL1_ATTRIBUTES2_MPORTSEL_VAL_PRIMARY (0x0U)
3834 #define CSL_DSS_VIDL1_ATTRIBUTES2_MPORTSEL_VAL_SECONDARY (0x1U)
3835 
3836 #define CSL_DSS_VIDL1_ATTRIBUTES2_TAGS_MASK (0x7C000000U)
3837 #define CSL_DSS_VIDL1_ATTRIBUTES2_TAGS_SHIFT (0x0000001AU)
3838 #define CSL_DSS_VIDL1_ATTRIBUTES2_TAGS_MAX (0x0000001FU)
3839 
3840 #define CSL_DSS_VIDL1_ATTRIBUTES2_RESERVED3_MASK (0x80000000U)
3841 #define CSL_DSS_VIDL1_ATTRIBUTES2_RESERVED3_SHIFT (0x0000001FU)
3842 #define CSL_DSS_VIDL1_ATTRIBUTES2_RESERVED3_MAX (0x00000001U)
3843 
3844 /* BA_0 */
3845 
3846 #define CSL_DSS_VIDL1_BA_0_BA_MASK (0xFFFFFFFFU)
3847 #define CSL_DSS_VIDL1_BA_0_BA_SHIFT (0x00000000U)
3848 #define CSL_DSS_VIDL1_BA_0_BA_MAX (0xFFFFFFFFU)
3849 
3850 /* BA_1 */
3851 
3852 #define CSL_DSS_VIDL1_BA_1_BA_MASK (0xFFFFFFFFU)
3853 #define CSL_DSS_VIDL1_BA_1_BA_SHIFT (0x00000000U)
3854 #define CSL_DSS_VIDL1_BA_1_BA_MAX (0xFFFFFFFFU)
3855 
3856 /* BA_UV_0 */
3857 
3858 #define CSL_DSS_VIDL1_BA_UV_0_BA_MASK (0xFFFFFFFFU)
3859 #define CSL_DSS_VIDL1_BA_UV_0_BA_SHIFT (0x00000000U)
3860 #define CSL_DSS_VIDL1_BA_UV_0_BA_MAX (0xFFFFFFFFU)
3861 
3862 /* BA_UV_1 */
3863 
3864 #define CSL_DSS_VIDL1_BA_UV_1_BA_MASK (0xFFFFFFFFU)
3865 #define CSL_DSS_VIDL1_BA_UV_1_BA_SHIFT (0x00000000U)
3866 #define CSL_DSS_VIDL1_BA_UV_1_BA_MAX (0xFFFFFFFFU)
3867 
3868 /* BUF_SIZE_STATUS */
3869 
3870 #define CSL_DSS_VIDL1_BUF_SIZE_STATUS_BUFSIZE_MASK (0x0000FFFFU)
3871 #define CSL_DSS_VIDL1_BUF_SIZE_STATUS_BUFSIZE_SHIFT (0x00000000U)
3872 #define CSL_DSS_VIDL1_BUF_SIZE_STATUS_BUFSIZE_MAX (0x0000FFFFU)
3873 
3874 #define CSL_DSS_VIDL1_BUF_SIZE_STATUS_RESERVED_61_MASK (0xFFFF0000U)
3875 #define CSL_DSS_VIDL1_BUF_SIZE_STATUS_RESERVED_61_SHIFT (0x00000010U)
3876 #define CSL_DSS_VIDL1_BUF_SIZE_STATUS_RESERVED_61_MAX (0x0000FFFFU)
3877 
3878 /* BUF_THRESHOLD */
3879 
3880 #define CSL_DSS_VIDL1_BUF_THRESHOLD_BUFLOWTHRESHOLD_MASK (0x0000FFFFU)
3881 #define CSL_DSS_VIDL1_BUF_THRESHOLD_BUFLOWTHRESHOLD_SHIFT (0x00000000U)
3882 #define CSL_DSS_VIDL1_BUF_THRESHOLD_BUFLOWTHRESHOLD_MAX (0x0000FFFFU)
3883 
3884 #define CSL_DSS_VIDL1_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MASK (0xFFFF0000U)
3885 #define CSL_DSS_VIDL1_BUF_THRESHOLD_BUFHIGHTHRESHOLD_SHIFT (0x00000010U)
3886 #define CSL_DSS_VIDL1_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MAX (0x0000FFFFU)
3887 
3888 /* CSC_COEF0 */
3889 
3890 #define CSL_DSS_VIDL1_CSC_COEF0_C00_MASK (0x000007FFU)
3891 #define CSL_DSS_VIDL1_CSC_COEF0_C00_SHIFT (0x00000000U)
3892 #define CSL_DSS_VIDL1_CSC_COEF0_C00_MAX (0x000007FFU)
3893 
3894 #define CSL_DSS_VIDL1_CSC_COEF0_RESERVED_53_MASK (0x0000F800U)
3895 #define CSL_DSS_VIDL1_CSC_COEF0_RESERVED_53_SHIFT (0x0000000BU)
3896 #define CSL_DSS_VIDL1_CSC_COEF0_RESERVED_53_MAX (0x0000001FU)
3897 
3898 #define CSL_DSS_VIDL1_CSC_COEF0_C01_MASK (0x07FF0000U)
3899 #define CSL_DSS_VIDL1_CSC_COEF0_C01_SHIFT (0x00000010U)
3900 #define CSL_DSS_VIDL1_CSC_COEF0_C01_MAX (0x000007FFU)
3901 
3902 #define CSL_DSS_VIDL1_CSC_COEF0_RESERVED_52_MASK (0xF8000000U)
3903 #define CSL_DSS_VIDL1_CSC_COEF0_RESERVED_52_SHIFT (0x0000001BU)
3904 #define CSL_DSS_VIDL1_CSC_COEF0_RESERVED_52_MAX (0x0000001FU)
3905 
3906 /* CSC_COEF1 */
3907 
3908 #define CSL_DSS_VIDL1_CSC_COEF1_C02_MASK (0x000007FFU)
3909 #define CSL_DSS_VIDL1_CSC_COEF1_C02_SHIFT (0x00000000U)
3910 #define CSL_DSS_VIDL1_CSC_COEF1_C02_MAX (0x000007FFU)
3911 
3912 #define CSL_DSS_VIDL1_CSC_COEF1_RESERVED_55_MASK (0x0000F800U)
3913 #define CSL_DSS_VIDL1_CSC_COEF1_RESERVED_55_SHIFT (0x0000000BU)
3914 #define CSL_DSS_VIDL1_CSC_COEF1_RESERVED_55_MAX (0x0000001FU)
3915 
3916 #define CSL_DSS_VIDL1_CSC_COEF1_C10_MASK (0x07FF0000U)
3917 #define CSL_DSS_VIDL1_CSC_COEF1_C10_SHIFT (0x00000010U)
3918 #define CSL_DSS_VIDL1_CSC_COEF1_C10_MAX (0x000007FFU)
3919 
3920 #define CSL_DSS_VIDL1_CSC_COEF1_RESERVED_54_MASK (0xF8000000U)
3921 #define CSL_DSS_VIDL1_CSC_COEF1_RESERVED_54_SHIFT (0x0000001BU)
3922 #define CSL_DSS_VIDL1_CSC_COEF1_RESERVED_54_MAX (0x0000001FU)
3923 
3924 /* CSC_COEF2 */
3925 
3926 #define CSL_DSS_VIDL1_CSC_COEF2_C11_MASK (0x000007FFU)
3927 #define CSL_DSS_VIDL1_CSC_COEF2_C11_SHIFT (0x00000000U)
3928 #define CSL_DSS_VIDL1_CSC_COEF2_C11_MAX (0x000007FFU)
3929 
3930 #define CSL_DSS_VIDL1_CSC_COEF2_RESERVED_57_MASK (0x0000F800U)
3931 #define CSL_DSS_VIDL1_CSC_COEF2_RESERVED_57_SHIFT (0x0000000BU)
3932 #define CSL_DSS_VIDL1_CSC_COEF2_RESERVED_57_MAX (0x0000001FU)
3933 
3934 #define CSL_DSS_VIDL1_CSC_COEF2_C12_MASK (0x07FF0000U)
3935 #define CSL_DSS_VIDL1_CSC_COEF2_C12_SHIFT (0x00000010U)
3936 #define CSL_DSS_VIDL1_CSC_COEF2_C12_MAX (0x000007FFU)
3937 
3938 #define CSL_DSS_VIDL1_CSC_COEF2_RESERVED_56_MASK (0xF8000000U)
3939 #define CSL_DSS_VIDL1_CSC_COEF2_RESERVED_56_SHIFT (0x0000001BU)
3940 #define CSL_DSS_VIDL1_CSC_COEF2_RESERVED_56_MAX (0x0000001FU)
3941 
3942 /* CSC_COEF3 */
3943 
3944 #define CSL_DSS_VIDL1_CSC_COEF3_C20_MASK (0x000007FFU)
3945 #define CSL_DSS_VIDL1_CSC_COEF3_C20_SHIFT (0x00000000U)
3946 #define CSL_DSS_VIDL1_CSC_COEF3_C20_MAX (0x000007FFU)
3947 
3948 #define CSL_DSS_VIDL1_CSC_COEF3_RESERVED_59_MASK (0x0000F800U)
3949 #define CSL_DSS_VIDL1_CSC_COEF3_RESERVED_59_SHIFT (0x0000000BU)
3950 #define CSL_DSS_VIDL1_CSC_COEF3_RESERVED_59_MAX (0x0000001FU)
3951 
3952 #define CSL_DSS_VIDL1_CSC_COEF3_C21_MASK (0x07FF0000U)
3953 #define CSL_DSS_VIDL1_CSC_COEF3_C21_SHIFT (0x00000010U)
3954 #define CSL_DSS_VIDL1_CSC_COEF3_C21_MAX (0x000007FFU)
3955 
3956 #define CSL_DSS_VIDL1_CSC_COEF3_RESERVED_58_MASK (0xF8000000U)
3957 #define CSL_DSS_VIDL1_CSC_COEF3_RESERVED_58_SHIFT (0x0000001BU)
3958 #define CSL_DSS_VIDL1_CSC_COEF3_RESERVED_58_MAX (0x0000001FU)
3959 
3960 /* CSC_COEF4 */
3961 
3962 #define CSL_DSS_VIDL1_CSC_COEF4_C22_MASK (0x000007FFU)
3963 #define CSL_DSS_VIDL1_CSC_COEF4_C22_SHIFT (0x00000000U)
3964 #define CSL_DSS_VIDL1_CSC_COEF4_C22_MAX (0x000007FFU)
3965 
3966 #define CSL_DSS_VIDL1_CSC_COEF4_RESERVED_60_MASK (0xFFFFF800U)
3967 #define CSL_DSS_VIDL1_CSC_COEF4_RESERVED_60_SHIFT (0x0000000BU)
3968 #define CSL_DSS_VIDL1_CSC_COEF4_RESERVED_60_MAX (0x001FFFFFU)
3969 
3970 /* CSC_COEF5 */
3971 
3972 #define CSL_DSS_VIDL1_CSC_COEF5_RESERVED_MASK (0x00000007U)
3973 #define CSL_DSS_VIDL1_CSC_COEF5_RESERVED_SHIFT (0x00000000U)
3974 #define CSL_DSS_VIDL1_CSC_COEF5_RESERVED_MAX (0x00000007U)
3975 
3976 #define CSL_DSS_VIDL1_CSC_COEF5_PREOFFSET1_MASK (0x0000FFF8U)
3977 #define CSL_DSS_VIDL1_CSC_COEF5_PREOFFSET1_SHIFT (0x00000003U)
3978 #define CSL_DSS_VIDL1_CSC_COEF5_PREOFFSET1_MAX (0x00001FFFU)
3979 
3980 #define CSL_DSS_VIDL1_CSC_COEF5_RESERVED1_MASK (0x00070000U)
3981 #define CSL_DSS_VIDL1_CSC_COEF5_RESERVED1_SHIFT (0x00000010U)
3982 #define CSL_DSS_VIDL1_CSC_COEF5_RESERVED1_MAX (0x00000007U)
3983 
3984 #define CSL_DSS_VIDL1_CSC_COEF5_PREOFFSET2_MASK (0xFFF80000U)
3985 #define CSL_DSS_VIDL1_CSC_COEF5_PREOFFSET2_SHIFT (0x00000013U)
3986 #define CSL_DSS_VIDL1_CSC_COEF5_PREOFFSET2_MAX (0x00001FFFU)
3987 
3988 /* CSC_COEF6 */
3989 
3990 #define CSL_DSS_VIDL1_CSC_COEF6_RESERVED_MASK (0x00000007U)
3991 #define CSL_DSS_VIDL1_CSC_COEF6_RESERVED_SHIFT (0x00000000U)
3992 #define CSL_DSS_VIDL1_CSC_COEF6_RESERVED_MAX (0x00000007U)
3993 
3994 #define CSL_DSS_VIDL1_CSC_COEF6_PREOFFSET3_MASK (0x0000FFF8U)
3995 #define CSL_DSS_VIDL1_CSC_COEF6_PREOFFSET3_SHIFT (0x00000003U)
3996 #define CSL_DSS_VIDL1_CSC_COEF6_PREOFFSET3_MAX (0x00001FFFU)
3997 
3998 #define CSL_DSS_VIDL1_CSC_COEF6_RESERVED1_MASK (0x00070000U)
3999 #define CSL_DSS_VIDL1_CSC_COEF6_RESERVED1_SHIFT (0x00000010U)
4000 #define CSL_DSS_VIDL1_CSC_COEF6_RESERVED1_MAX (0x00000007U)
4001 
4002 #define CSL_DSS_VIDL1_CSC_COEF6_POSTOFFSET1_MASK (0xFFF80000U)
4003 #define CSL_DSS_VIDL1_CSC_COEF6_POSTOFFSET1_SHIFT (0x00000013U)
4004 #define CSL_DSS_VIDL1_CSC_COEF6_POSTOFFSET1_MAX (0x00001FFFU)
4005 
4006 /* GLOBAL_ALPHA */
4007 
4008 #define CSL_DSS_VIDL1_GLOBAL_ALPHA_GLOBALALPHA_MASK (0x000000FFU)
4009 #define CSL_DSS_VIDL1_GLOBAL_ALPHA_GLOBALALPHA_SHIFT (0x00000000U)
4010 #define CSL_DSS_VIDL1_GLOBAL_ALPHA_GLOBALALPHA_MAX (0x000000FFU)
4011 
4012 #define CSL_DSS_VIDL1_GLOBAL_ALPHA_RESERVED_MASK (0xFFFFFF00U)
4013 #define CSL_DSS_VIDL1_GLOBAL_ALPHA_RESERVED_SHIFT (0x00000008U)
4014 #define CSL_DSS_VIDL1_GLOBAL_ALPHA_RESERVED_MAX (0x00FFFFFFU)
4015 
4016 /* MFLAG_THRESHOLD */
4017 
4018 #define CSL_DSS_VIDL1_MFLAG_THRESHOLD_LT_MFLAG_MASK (0x0000FFFFU)
4019 #define CSL_DSS_VIDL1_MFLAG_THRESHOLD_LT_MFLAG_SHIFT (0x00000000U)
4020 #define CSL_DSS_VIDL1_MFLAG_THRESHOLD_LT_MFLAG_MAX (0x0000FFFFU)
4021 
4022 #define CSL_DSS_VIDL1_MFLAG_THRESHOLD_HT_MFLAG_MASK (0xFFFF0000U)
4023 #define CSL_DSS_VIDL1_MFLAG_THRESHOLD_HT_MFLAG_SHIFT (0x00000010U)
4024 #define CSL_DSS_VIDL1_MFLAG_THRESHOLD_HT_MFLAG_MAX (0x0000FFFFU)
4025 
4026 /* PICTURE_SIZE */
4027 
4028 #define CSL_DSS_VIDL1_PICTURE_SIZE_MEMSIZEX_MASK (0x00003FFFU)
4029 #define CSL_DSS_VIDL1_PICTURE_SIZE_MEMSIZEX_SHIFT (0x00000000U)
4030 #define CSL_DSS_VIDL1_PICTURE_SIZE_MEMSIZEX_MAX (0x00003FFFU)
4031 
4032 #define CSL_DSS_VIDL1_PICTURE_SIZE_MEMSIZEY_MASK (0x3FFF0000U)
4033 #define CSL_DSS_VIDL1_PICTURE_SIZE_MEMSIZEY_SHIFT (0x00000010U)
4034 #define CSL_DSS_VIDL1_PICTURE_SIZE_MEMSIZEY_MAX (0x00003FFFU)
4035 
4036 /* PIXEL_INC */
4037 
4038 #define CSL_DSS_VIDL1_PIXEL_INC_PIXELINC_MASK (0x000000FFU)
4039 #define CSL_DSS_VIDL1_PIXEL_INC_PIXELINC_SHIFT (0x00000000U)
4040 #define CSL_DSS_VIDL1_PIXEL_INC_PIXELINC_MAX (0x000000FFU)
4041 
4042 #define CSL_DSS_VIDL1_PIXEL_INC_RESERVED_68_MASK (0xFFFFFF00U)
4043 #define CSL_DSS_VIDL1_PIXEL_INC_RESERVED_68_SHIFT (0x00000008U)
4044 #define CSL_DSS_VIDL1_PIXEL_INC_RESERVED_68_MAX (0x00FFFFFFU)
4045 
4046 /* PRELOAD */
4047 
4048 #define CSL_DSS_VIDL1_PRELOAD_PRELOAD_MASK (0x00000FFFU)
4049 #define CSL_DSS_VIDL1_PRELOAD_PRELOAD_SHIFT (0x00000000U)
4050 #define CSL_DSS_VIDL1_PRELOAD_PRELOAD_MAX (0x00000FFFU)
4051 
4052 #define CSL_DSS_VIDL1_PRELOAD_RESERVED_212_MASK (0xFFFFF000U)
4053 #define CSL_DSS_VIDL1_PRELOAD_RESERVED_212_SHIFT (0x0000000CU)
4054 #define CSL_DSS_VIDL1_PRELOAD_RESERVED_212_MAX (0x000FFFFFU)
4055 
4056 /* ROW_INC */
4057 
4058 #define CSL_DSS_VIDL1_ROW_INC_ROWINC_MASK (0xFFFFFFFFU)
4059 #define CSL_DSS_VIDL1_ROW_INC_ROWINC_SHIFT (0x00000000U)
4060 #define CSL_DSS_VIDL1_ROW_INC_ROWINC_MAX (0xFFFFFFFFU)
4061 
4062 /* BA_EXT_0 */
4063 
4064 #define CSL_DSS_VIDL1_BA_EXT_0_BA_EXT_MASK (0x0000FFFFU)
4065 #define CSL_DSS_VIDL1_BA_EXT_0_BA_EXT_SHIFT (0x00000000U)
4066 #define CSL_DSS_VIDL1_BA_EXT_0_BA_EXT_MAX (0x0000FFFFU)
4067 
4068 #define CSL_DSS_VIDL1_BA_EXT_0_RESERVED_MASK (0xFFFF0000U)
4069 #define CSL_DSS_VIDL1_BA_EXT_0_RESERVED_SHIFT (0x00000010U)
4070 #define CSL_DSS_VIDL1_BA_EXT_0_RESERVED_MAX (0x0000FFFFU)
4071 
4072 /* BA_EXT_1 */
4073 
4074 #define CSL_DSS_VIDL1_BA_EXT_1_BA_EXT_MASK (0x0000FFFFU)
4075 #define CSL_DSS_VIDL1_BA_EXT_1_BA_EXT_SHIFT (0x00000000U)
4076 #define CSL_DSS_VIDL1_BA_EXT_1_BA_EXT_MAX (0x0000FFFFU)
4077 
4078 #define CSL_DSS_VIDL1_BA_EXT_1_RESERVED_MASK (0xFFFF0000U)
4079 #define CSL_DSS_VIDL1_BA_EXT_1_RESERVED_SHIFT (0x00000010U)
4080 #define CSL_DSS_VIDL1_BA_EXT_1_RESERVED_MAX (0x0000FFFFU)
4081 
4082 /* BA_UV_EXT_0 */
4083 
4084 #define CSL_DSS_VIDL1_BA_UV_EXT_0_BA_UV_EXT_MASK (0x0000FFFFU)
4085 #define CSL_DSS_VIDL1_BA_UV_EXT_0_BA_UV_EXT_SHIFT (0x00000000U)
4086 #define CSL_DSS_VIDL1_BA_UV_EXT_0_BA_UV_EXT_MAX (0x0000FFFFU)
4087 
4088 #define CSL_DSS_VIDL1_BA_UV_EXT_0_RESERVED_MASK (0xFFFF0000U)
4089 #define CSL_DSS_VIDL1_BA_UV_EXT_0_RESERVED_SHIFT (0x00000010U)
4090 #define CSL_DSS_VIDL1_BA_UV_EXT_0_RESERVED_MAX (0x0000FFFFU)
4091 
4092 /* BA_UV_EXT_1 */
4093 
4094 #define CSL_DSS_VIDL1_BA_UV_EXT_1_BA_UV_EXT_MASK (0x0000FFFFU)
4095 #define CSL_DSS_VIDL1_BA_UV_EXT_1_BA_UV_EXT_SHIFT (0x00000000U)
4096 #define CSL_DSS_VIDL1_BA_UV_EXT_1_BA_UV_EXT_MAX (0x0000FFFFU)
4097 
4098 #define CSL_DSS_VIDL1_BA_UV_EXT_1_RESERVED_MASK (0xFFFF0000U)
4099 #define CSL_DSS_VIDL1_BA_UV_EXT_1_RESERVED_SHIFT (0x00000010U)
4100 #define CSL_DSS_VIDL1_BA_UV_EXT_1_RESERVED_MAX (0x0000FFFFU)
4101 
4102 /* CSC_COEF7 */
4103 
4104 #define CSL_DSS_VIDL1_CSC_COEF7_RESERVED_MASK (0x00000007U)
4105 #define CSL_DSS_VIDL1_CSC_COEF7_RESERVED_SHIFT (0x00000000U)
4106 #define CSL_DSS_VIDL1_CSC_COEF7_RESERVED_MAX (0x00000007U)
4107 
4108 #define CSL_DSS_VIDL1_CSC_COEF7_POSTOFFSET2_MASK (0x0000FFF8U)
4109 #define CSL_DSS_VIDL1_CSC_COEF7_POSTOFFSET2_SHIFT (0x00000003U)
4110 #define CSL_DSS_VIDL1_CSC_COEF7_POSTOFFSET2_MAX (0x00001FFFU)
4111 
4112 #define CSL_DSS_VIDL1_CSC_COEF7_RESERVED1_MASK (0x00070000U)
4113 #define CSL_DSS_VIDL1_CSC_COEF7_RESERVED1_SHIFT (0x00000010U)
4114 #define CSL_DSS_VIDL1_CSC_COEF7_RESERVED1_MAX (0x00000007U)
4115 
4116 #define CSL_DSS_VIDL1_CSC_COEF7_POSTOFFSET3_MASK (0xFFF80000U)
4117 #define CSL_DSS_VIDL1_CSC_COEF7_POSTOFFSET3_SHIFT (0x00000013U)
4118 #define CSL_DSS_VIDL1_CSC_COEF7_POSTOFFSET3_MAX (0x00001FFFU)
4119 
4120 /* ROW_INC_UV */
4121 
4122 #define CSL_DSS_VIDL1_ROW_INC_UV_ROWINC_MASK (0xFFFFFFFFU)
4123 #define CSL_DSS_VIDL1_ROW_INC_UV_ROWINC_SHIFT (0x00000000U)
4124 #define CSL_DSS_VIDL1_ROW_INC_UV_ROWINC_MAX (0xFFFFFFFFU)
4125 
4126 /* TILE */
4127 
4128 #define CSL_DSS_VIDL1_TILE_TILEINDEX_MASK (0x007FFFFFU)
4129 #define CSL_DSS_VIDL1_TILE_TILEINDEX_SHIFT (0x00000000U)
4130 #define CSL_DSS_VIDL1_TILE_TILEINDEX_MAX (0x007FFFFFU)
4131 
4132 /* TILE2 */
4133 
4134 #define CSL_DSS_VIDL1_TILE2_NUM_TILES_MASK (0x007FFFFFU)
4135 #define CSL_DSS_VIDL1_TILE2_NUM_TILES_SHIFT (0x00000000U)
4136 #define CSL_DSS_VIDL1_TILE2_NUM_TILES_MAX (0x007FFFFFU)
4137 
4138 #define CSL_DSS_VIDL1_TILE2_RESERVED_MASK (0xFF800000U)
4139 #define CSL_DSS_VIDL1_TILE2_RESERVED_SHIFT (0x00000017U)
4140 #define CSL_DSS_VIDL1_TILE2_RESERVED_MAX (0x000001FFU)
4141 
4142 /* FBDC_ATTRIBUTES */
4143 
4144 #define CSL_DSS_VIDL1_FBDC_ATTRIBUTES_ENABLE_MASK (0x00000001U)
4145 #define CSL_DSS_VIDL1_FBDC_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
4146 #define CSL_DSS_VIDL1_FBDC_ATTRIBUTES_ENABLE_MAX (0x00000001U)
4147 
4148 #define CSL_DSS_VIDL1_FBDC_ATTRIBUTES_FORMAT_MASK (0x000000FEU)
4149 #define CSL_DSS_VIDL1_FBDC_ATTRIBUTES_FORMAT_SHIFT (0x00000001U)
4150 #define CSL_DSS_VIDL1_FBDC_ATTRIBUTES_FORMAT_MAX (0x0000007FU)
4151 
4152 #define CSL_DSS_VIDL1_FBDC_ATTRIBUTES_FORMAT_VAL_U8U8U8U8 (0xCU)
4153 #define CSL_DSS_VIDL1_FBDC_ATTRIBUTES_FORMAT_VAL_A2R10B10G10 (0xEU)
4154 
4155 #define CSL_DSS_VIDL1_FBDC_ATTRIBUTES_TILETYPE_MASK (0x00000300U)
4156 #define CSL_DSS_VIDL1_FBDC_ATTRIBUTES_TILETYPE_SHIFT (0x00000008U)
4157 #define CSL_DSS_VIDL1_FBDC_ATTRIBUTES_TILETYPE_MAX (0x00000003U)
4158 
4159 #define CSL_DSS_VIDL1_FBDC_ATTRIBUTES_TILETYPE_VAL_TILE16BY4 (0x2U)
4160 #define CSL_DSS_VIDL1_FBDC_ATTRIBUTES_TILETYPE_VAL_TILE32BY2 (0x3U)
4161 
4162 /* FBDC_CLEAR_COLOR */
4163 
4164 #define CSL_DSS_VIDL1_FBDC_CLEAR_COLOR_CLEARCOLOR_MASK (0xFFFFFFFFU)
4165 #define CSL_DSS_VIDL1_FBDC_CLEAR_COLOR_CLEARCOLOR_SHIFT (0x00000000U)
4166 #define CSL_DSS_VIDL1_FBDC_CLEAR_COLOR_CLEARCOLOR_MAX (0xFFFFFFFFU)
4167 
4168 /* CLUT_0 */
4169 
4170 #define CSL_DSS_VIDL1_CLUT_0_VALUE_B_MASK (0x000003FFU)
4171 #define CSL_DSS_VIDL1_CLUT_0_VALUE_B_SHIFT (0x00000000U)
4172 #define CSL_DSS_VIDL1_CLUT_0_VALUE_B_MAX (0x000003FFU)
4173 
4174 #define CSL_DSS_VIDL1_CLUT_0_VALUE_G_MASK (0x000FFC00U)
4175 #define CSL_DSS_VIDL1_CLUT_0_VALUE_G_SHIFT (0x0000000AU)
4176 #define CSL_DSS_VIDL1_CLUT_0_VALUE_G_MAX (0x000003FFU)
4177 
4178 #define CSL_DSS_VIDL1_CLUT_0_VALUE_R_MASK (0x3FF00000U)
4179 #define CSL_DSS_VIDL1_CLUT_0_VALUE_R_SHIFT (0x00000014U)
4180 #define CSL_DSS_VIDL1_CLUT_0_VALUE_R_MAX (0x000003FFU)
4181 
4182 #define CSL_DSS_VIDL1_CLUT_0_INDEX_MASK (0x80000000U)
4183 #define CSL_DSS_VIDL1_CLUT_0_INDEX_SHIFT (0x0000001FU)
4184 #define CSL_DSS_VIDL1_CLUT_0_INDEX_MAX (0x00000001U)
4185 
4186 /* CLUT_1 */
4187 
4188 #define CSL_DSS_VIDL1_CLUT_1_VALUE_B_MASK (0x000003FFU)
4189 #define CSL_DSS_VIDL1_CLUT_1_VALUE_B_SHIFT (0x00000000U)
4190 #define CSL_DSS_VIDL1_CLUT_1_VALUE_B_MAX (0x000003FFU)
4191 
4192 #define CSL_DSS_VIDL1_CLUT_1_VALUE_G_MASK (0x000FFC00U)
4193 #define CSL_DSS_VIDL1_CLUT_1_VALUE_G_SHIFT (0x0000000AU)
4194 #define CSL_DSS_VIDL1_CLUT_1_VALUE_G_MAX (0x000003FFU)
4195 
4196 #define CSL_DSS_VIDL1_CLUT_1_VALUE_R_MASK (0x3FF00000U)
4197 #define CSL_DSS_VIDL1_CLUT_1_VALUE_R_SHIFT (0x00000014U)
4198 #define CSL_DSS_VIDL1_CLUT_1_VALUE_R_MAX (0x000003FFU)
4199 
4200 #define CSL_DSS_VIDL1_CLUT_1_INDEX_MASK (0x80000000U)
4201 #define CSL_DSS_VIDL1_CLUT_1_INDEX_SHIFT (0x0000001FU)
4202 #define CSL_DSS_VIDL1_CLUT_1_INDEX_MAX (0x00000001U)
4203 
4204 /* CLUT_2 */
4205 
4206 #define CSL_DSS_VIDL1_CLUT_2_VALUE_B_MASK (0x000003FFU)
4207 #define CSL_DSS_VIDL1_CLUT_2_VALUE_B_SHIFT (0x00000000U)
4208 #define CSL_DSS_VIDL1_CLUT_2_VALUE_B_MAX (0x000003FFU)
4209 
4210 #define CSL_DSS_VIDL1_CLUT_2_VALUE_G_MASK (0x000FFC00U)
4211 #define CSL_DSS_VIDL1_CLUT_2_VALUE_G_SHIFT (0x0000000AU)
4212 #define CSL_DSS_VIDL1_CLUT_2_VALUE_G_MAX (0x000003FFU)
4213 
4214 #define CSL_DSS_VIDL1_CLUT_2_VALUE_R_MASK (0x3FF00000U)
4215 #define CSL_DSS_VIDL1_CLUT_2_VALUE_R_SHIFT (0x00000014U)
4216 #define CSL_DSS_VIDL1_CLUT_2_VALUE_R_MAX (0x000003FFU)
4217 
4218 #define CSL_DSS_VIDL1_CLUT_2_INDEX_MASK (0x80000000U)
4219 #define CSL_DSS_VIDL1_CLUT_2_INDEX_SHIFT (0x0000001FU)
4220 #define CSL_DSS_VIDL1_CLUT_2_INDEX_MAX (0x00000001U)
4221 
4222 /* CLUT_3 */
4223 
4224 #define CSL_DSS_VIDL1_CLUT_3_VALUE_B_MASK (0x000003FFU)
4225 #define CSL_DSS_VIDL1_CLUT_3_VALUE_B_SHIFT (0x00000000U)
4226 #define CSL_DSS_VIDL1_CLUT_3_VALUE_B_MAX (0x000003FFU)
4227 
4228 #define CSL_DSS_VIDL1_CLUT_3_VALUE_G_MASK (0x000FFC00U)
4229 #define CSL_DSS_VIDL1_CLUT_3_VALUE_G_SHIFT (0x0000000AU)
4230 #define CSL_DSS_VIDL1_CLUT_3_VALUE_G_MAX (0x000003FFU)
4231 
4232 #define CSL_DSS_VIDL1_CLUT_3_VALUE_R_MASK (0x3FF00000U)
4233 #define CSL_DSS_VIDL1_CLUT_3_VALUE_R_SHIFT (0x00000014U)
4234 #define CSL_DSS_VIDL1_CLUT_3_VALUE_R_MAX (0x000003FFU)
4235 
4236 #define CSL_DSS_VIDL1_CLUT_3_INDEX_MASK (0x80000000U)
4237 #define CSL_DSS_VIDL1_CLUT_3_INDEX_SHIFT (0x0000001FU)
4238 #define CSL_DSS_VIDL1_CLUT_3_INDEX_MAX (0x00000001U)
4239 
4240 /* CLUT_4 */
4241 
4242 #define CSL_DSS_VIDL1_CLUT_4_VALUE_B_MASK (0x000003FFU)
4243 #define CSL_DSS_VIDL1_CLUT_4_VALUE_B_SHIFT (0x00000000U)
4244 #define CSL_DSS_VIDL1_CLUT_4_VALUE_B_MAX (0x000003FFU)
4245 
4246 #define CSL_DSS_VIDL1_CLUT_4_VALUE_G_MASK (0x000FFC00U)
4247 #define CSL_DSS_VIDL1_CLUT_4_VALUE_G_SHIFT (0x0000000AU)
4248 #define CSL_DSS_VIDL1_CLUT_4_VALUE_G_MAX (0x000003FFU)
4249 
4250 #define CSL_DSS_VIDL1_CLUT_4_VALUE_R_MASK (0x3FF00000U)
4251 #define CSL_DSS_VIDL1_CLUT_4_VALUE_R_SHIFT (0x00000014U)
4252 #define CSL_DSS_VIDL1_CLUT_4_VALUE_R_MAX (0x000003FFU)
4253 
4254 #define CSL_DSS_VIDL1_CLUT_4_INDEX_MASK (0x80000000U)
4255 #define CSL_DSS_VIDL1_CLUT_4_INDEX_SHIFT (0x0000001FU)
4256 #define CSL_DSS_VIDL1_CLUT_4_INDEX_MAX (0x00000001U)
4257 
4258 /* CLUT_5 */
4259 
4260 #define CSL_DSS_VIDL1_CLUT_5_VALUE_B_MASK (0x000003FFU)
4261 #define CSL_DSS_VIDL1_CLUT_5_VALUE_B_SHIFT (0x00000000U)
4262 #define CSL_DSS_VIDL1_CLUT_5_VALUE_B_MAX (0x000003FFU)
4263 
4264 #define CSL_DSS_VIDL1_CLUT_5_VALUE_G_MASK (0x000FFC00U)
4265 #define CSL_DSS_VIDL1_CLUT_5_VALUE_G_SHIFT (0x0000000AU)
4266 #define CSL_DSS_VIDL1_CLUT_5_VALUE_G_MAX (0x000003FFU)
4267 
4268 #define CSL_DSS_VIDL1_CLUT_5_VALUE_R_MASK (0x3FF00000U)
4269 #define CSL_DSS_VIDL1_CLUT_5_VALUE_R_SHIFT (0x00000014U)
4270 #define CSL_DSS_VIDL1_CLUT_5_VALUE_R_MAX (0x000003FFU)
4271 
4272 #define CSL_DSS_VIDL1_CLUT_5_INDEX_MASK (0x80000000U)
4273 #define CSL_DSS_VIDL1_CLUT_5_INDEX_SHIFT (0x0000001FU)
4274 #define CSL_DSS_VIDL1_CLUT_5_INDEX_MAX (0x00000001U)
4275 
4276 /* CLUT_6 */
4277 
4278 #define CSL_DSS_VIDL1_CLUT_6_VALUE_B_MASK (0x000003FFU)
4279 #define CSL_DSS_VIDL1_CLUT_6_VALUE_B_SHIFT (0x00000000U)
4280 #define CSL_DSS_VIDL1_CLUT_6_VALUE_B_MAX (0x000003FFU)
4281 
4282 #define CSL_DSS_VIDL1_CLUT_6_VALUE_G_MASK (0x000FFC00U)
4283 #define CSL_DSS_VIDL1_CLUT_6_VALUE_G_SHIFT (0x0000000AU)
4284 #define CSL_DSS_VIDL1_CLUT_6_VALUE_G_MAX (0x000003FFU)
4285 
4286 #define CSL_DSS_VIDL1_CLUT_6_VALUE_R_MASK (0x3FF00000U)
4287 #define CSL_DSS_VIDL1_CLUT_6_VALUE_R_SHIFT (0x00000014U)
4288 #define CSL_DSS_VIDL1_CLUT_6_VALUE_R_MAX (0x000003FFU)
4289 
4290 #define CSL_DSS_VIDL1_CLUT_6_INDEX_MASK (0x80000000U)
4291 #define CSL_DSS_VIDL1_CLUT_6_INDEX_SHIFT (0x0000001FU)
4292 #define CSL_DSS_VIDL1_CLUT_6_INDEX_MAX (0x00000001U)
4293 
4294 /* CLUT_7 */
4295 
4296 #define CSL_DSS_VIDL1_CLUT_7_VALUE_B_MASK (0x000003FFU)
4297 #define CSL_DSS_VIDL1_CLUT_7_VALUE_B_SHIFT (0x00000000U)
4298 #define CSL_DSS_VIDL1_CLUT_7_VALUE_B_MAX (0x000003FFU)
4299 
4300 #define CSL_DSS_VIDL1_CLUT_7_VALUE_G_MASK (0x000FFC00U)
4301 #define CSL_DSS_VIDL1_CLUT_7_VALUE_G_SHIFT (0x0000000AU)
4302 #define CSL_DSS_VIDL1_CLUT_7_VALUE_G_MAX (0x000003FFU)
4303 
4304 #define CSL_DSS_VIDL1_CLUT_7_VALUE_R_MASK (0x3FF00000U)
4305 #define CSL_DSS_VIDL1_CLUT_7_VALUE_R_SHIFT (0x00000014U)
4306 #define CSL_DSS_VIDL1_CLUT_7_VALUE_R_MAX (0x000003FFU)
4307 
4308 #define CSL_DSS_VIDL1_CLUT_7_INDEX_MASK (0x80000000U)
4309 #define CSL_DSS_VIDL1_CLUT_7_INDEX_SHIFT (0x0000001FU)
4310 #define CSL_DSS_VIDL1_CLUT_7_INDEX_MAX (0x00000001U)
4311 
4312 /* CLUT_8 */
4313 
4314 #define CSL_DSS_VIDL1_CLUT_8_VALUE_B_MASK (0x000003FFU)
4315 #define CSL_DSS_VIDL1_CLUT_8_VALUE_B_SHIFT (0x00000000U)
4316 #define CSL_DSS_VIDL1_CLUT_8_VALUE_B_MAX (0x000003FFU)
4317 
4318 #define CSL_DSS_VIDL1_CLUT_8_VALUE_G_MASK (0x000FFC00U)
4319 #define CSL_DSS_VIDL1_CLUT_8_VALUE_G_SHIFT (0x0000000AU)
4320 #define CSL_DSS_VIDL1_CLUT_8_VALUE_G_MAX (0x000003FFU)
4321 
4322 #define CSL_DSS_VIDL1_CLUT_8_VALUE_R_MASK (0x3FF00000U)
4323 #define CSL_DSS_VIDL1_CLUT_8_VALUE_R_SHIFT (0x00000014U)
4324 #define CSL_DSS_VIDL1_CLUT_8_VALUE_R_MAX (0x000003FFU)
4325 
4326 #define CSL_DSS_VIDL1_CLUT_8_INDEX_MASK (0x80000000U)
4327 #define CSL_DSS_VIDL1_CLUT_8_INDEX_SHIFT (0x0000001FU)
4328 #define CSL_DSS_VIDL1_CLUT_8_INDEX_MAX (0x00000001U)
4329 
4330 /* CLUT_9 */
4331 
4332 #define CSL_DSS_VIDL1_CLUT_9_VALUE_B_MASK (0x000003FFU)
4333 #define CSL_DSS_VIDL1_CLUT_9_VALUE_B_SHIFT (0x00000000U)
4334 #define CSL_DSS_VIDL1_CLUT_9_VALUE_B_MAX (0x000003FFU)
4335 
4336 #define CSL_DSS_VIDL1_CLUT_9_VALUE_G_MASK (0x000FFC00U)
4337 #define CSL_DSS_VIDL1_CLUT_9_VALUE_G_SHIFT (0x0000000AU)
4338 #define CSL_DSS_VIDL1_CLUT_9_VALUE_G_MAX (0x000003FFU)
4339 
4340 #define CSL_DSS_VIDL1_CLUT_9_VALUE_R_MASK (0x3FF00000U)
4341 #define CSL_DSS_VIDL1_CLUT_9_VALUE_R_SHIFT (0x00000014U)
4342 #define CSL_DSS_VIDL1_CLUT_9_VALUE_R_MAX (0x000003FFU)
4343 
4344 #define CSL_DSS_VIDL1_CLUT_9_INDEX_MASK (0x80000000U)
4345 #define CSL_DSS_VIDL1_CLUT_9_INDEX_SHIFT (0x0000001FU)
4346 #define CSL_DSS_VIDL1_CLUT_9_INDEX_MAX (0x00000001U)
4347 
4348 /* CLUT_10 */
4349 
4350 #define CSL_DSS_VIDL1_CLUT_10_VALUE_B_MASK (0x000003FFU)
4351 #define CSL_DSS_VIDL1_CLUT_10_VALUE_B_SHIFT (0x00000000U)
4352 #define CSL_DSS_VIDL1_CLUT_10_VALUE_B_MAX (0x000003FFU)
4353 
4354 #define CSL_DSS_VIDL1_CLUT_10_VALUE_G_MASK (0x000FFC00U)
4355 #define CSL_DSS_VIDL1_CLUT_10_VALUE_G_SHIFT (0x0000000AU)
4356 #define CSL_DSS_VIDL1_CLUT_10_VALUE_G_MAX (0x000003FFU)
4357 
4358 #define CSL_DSS_VIDL1_CLUT_10_VALUE_R_MASK (0x3FF00000U)
4359 #define CSL_DSS_VIDL1_CLUT_10_VALUE_R_SHIFT (0x00000014U)
4360 #define CSL_DSS_VIDL1_CLUT_10_VALUE_R_MAX (0x000003FFU)
4361 
4362 #define CSL_DSS_VIDL1_CLUT_10_INDEX_MASK (0x80000000U)
4363 #define CSL_DSS_VIDL1_CLUT_10_INDEX_SHIFT (0x0000001FU)
4364 #define CSL_DSS_VIDL1_CLUT_10_INDEX_MAX (0x00000001U)
4365 
4366 /* CLUT_11 */
4367 
4368 #define CSL_DSS_VIDL1_CLUT_11_VALUE_B_MASK (0x000003FFU)
4369 #define CSL_DSS_VIDL1_CLUT_11_VALUE_B_SHIFT (0x00000000U)
4370 #define CSL_DSS_VIDL1_CLUT_11_VALUE_B_MAX (0x000003FFU)
4371 
4372 #define CSL_DSS_VIDL1_CLUT_11_VALUE_G_MASK (0x000FFC00U)
4373 #define CSL_DSS_VIDL1_CLUT_11_VALUE_G_SHIFT (0x0000000AU)
4374 #define CSL_DSS_VIDL1_CLUT_11_VALUE_G_MAX (0x000003FFU)
4375 
4376 #define CSL_DSS_VIDL1_CLUT_11_VALUE_R_MASK (0x3FF00000U)
4377 #define CSL_DSS_VIDL1_CLUT_11_VALUE_R_SHIFT (0x00000014U)
4378 #define CSL_DSS_VIDL1_CLUT_11_VALUE_R_MAX (0x000003FFU)
4379 
4380 #define CSL_DSS_VIDL1_CLUT_11_INDEX_MASK (0x80000000U)
4381 #define CSL_DSS_VIDL1_CLUT_11_INDEX_SHIFT (0x0000001FU)
4382 #define CSL_DSS_VIDL1_CLUT_11_INDEX_MAX (0x00000001U)
4383 
4384 /* CLUT_12 */
4385 
4386 #define CSL_DSS_VIDL1_CLUT_12_VALUE_B_MASK (0x000003FFU)
4387 #define CSL_DSS_VIDL1_CLUT_12_VALUE_B_SHIFT (0x00000000U)
4388 #define CSL_DSS_VIDL1_CLUT_12_VALUE_B_MAX (0x000003FFU)
4389 
4390 #define CSL_DSS_VIDL1_CLUT_12_VALUE_G_MASK (0x000FFC00U)
4391 #define CSL_DSS_VIDL1_CLUT_12_VALUE_G_SHIFT (0x0000000AU)
4392 #define CSL_DSS_VIDL1_CLUT_12_VALUE_G_MAX (0x000003FFU)
4393 
4394 #define CSL_DSS_VIDL1_CLUT_12_VALUE_R_MASK (0x3FF00000U)
4395 #define CSL_DSS_VIDL1_CLUT_12_VALUE_R_SHIFT (0x00000014U)
4396 #define CSL_DSS_VIDL1_CLUT_12_VALUE_R_MAX (0x000003FFU)
4397 
4398 #define CSL_DSS_VIDL1_CLUT_12_INDEX_MASK (0x80000000U)
4399 #define CSL_DSS_VIDL1_CLUT_12_INDEX_SHIFT (0x0000001FU)
4400 #define CSL_DSS_VIDL1_CLUT_12_INDEX_MAX (0x00000001U)
4401 
4402 /* CLUT_13 */
4403 
4404 #define CSL_DSS_VIDL1_CLUT_13_VALUE_B_MASK (0x000003FFU)
4405 #define CSL_DSS_VIDL1_CLUT_13_VALUE_B_SHIFT (0x00000000U)
4406 #define CSL_DSS_VIDL1_CLUT_13_VALUE_B_MAX (0x000003FFU)
4407 
4408 #define CSL_DSS_VIDL1_CLUT_13_VALUE_G_MASK (0x000FFC00U)
4409 #define CSL_DSS_VIDL1_CLUT_13_VALUE_G_SHIFT (0x0000000AU)
4410 #define CSL_DSS_VIDL1_CLUT_13_VALUE_G_MAX (0x000003FFU)
4411 
4412 #define CSL_DSS_VIDL1_CLUT_13_VALUE_R_MASK (0x3FF00000U)
4413 #define CSL_DSS_VIDL1_CLUT_13_VALUE_R_SHIFT (0x00000014U)
4414 #define CSL_DSS_VIDL1_CLUT_13_VALUE_R_MAX (0x000003FFU)
4415 
4416 #define CSL_DSS_VIDL1_CLUT_13_INDEX_MASK (0x80000000U)
4417 #define CSL_DSS_VIDL1_CLUT_13_INDEX_SHIFT (0x0000001FU)
4418 #define CSL_DSS_VIDL1_CLUT_13_INDEX_MAX (0x00000001U)
4419 
4420 /* CLUT_14 */
4421 
4422 #define CSL_DSS_VIDL1_CLUT_14_VALUE_B_MASK (0x000003FFU)
4423 #define CSL_DSS_VIDL1_CLUT_14_VALUE_B_SHIFT (0x00000000U)
4424 #define CSL_DSS_VIDL1_CLUT_14_VALUE_B_MAX (0x000003FFU)
4425 
4426 #define CSL_DSS_VIDL1_CLUT_14_VALUE_G_MASK (0x000FFC00U)
4427 #define CSL_DSS_VIDL1_CLUT_14_VALUE_G_SHIFT (0x0000000AU)
4428 #define CSL_DSS_VIDL1_CLUT_14_VALUE_G_MAX (0x000003FFU)
4429 
4430 #define CSL_DSS_VIDL1_CLUT_14_VALUE_R_MASK (0x3FF00000U)
4431 #define CSL_DSS_VIDL1_CLUT_14_VALUE_R_SHIFT (0x00000014U)
4432 #define CSL_DSS_VIDL1_CLUT_14_VALUE_R_MAX (0x000003FFU)
4433 
4434 #define CSL_DSS_VIDL1_CLUT_14_INDEX_MASK (0x80000000U)
4435 #define CSL_DSS_VIDL1_CLUT_14_INDEX_SHIFT (0x0000001FU)
4436 #define CSL_DSS_VIDL1_CLUT_14_INDEX_MAX (0x00000001U)
4437 
4438 /* CLUT_15 */
4439 
4440 #define CSL_DSS_VIDL1_CLUT_15_VALUE_B_MASK (0x000003FFU)
4441 #define CSL_DSS_VIDL1_CLUT_15_VALUE_B_SHIFT (0x00000000U)
4442 #define CSL_DSS_VIDL1_CLUT_15_VALUE_B_MAX (0x000003FFU)
4443 
4444 #define CSL_DSS_VIDL1_CLUT_15_VALUE_G_MASK (0x000FFC00U)
4445 #define CSL_DSS_VIDL1_CLUT_15_VALUE_G_SHIFT (0x0000000AU)
4446 #define CSL_DSS_VIDL1_CLUT_15_VALUE_G_MAX (0x000003FFU)
4447 
4448 #define CSL_DSS_VIDL1_CLUT_15_VALUE_R_MASK (0x3FF00000U)
4449 #define CSL_DSS_VIDL1_CLUT_15_VALUE_R_SHIFT (0x00000014U)
4450 #define CSL_DSS_VIDL1_CLUT_15_VALUE_R_MAX (0x000003FFU)
4451 
4452 #define CSL_DSS_VIDL1_CLUT_15_INDEX_MASK (0x80000000U)
4453 #define CSL_DSS_VIDL1_CLUT_15_INDEX_SHIFT (0x0000001FU)
4454 #define CSL_DSS_VIDL1_CLUT_15_INDEX_MAX (0x00000001U)
4455 
4456 /* SAFETY_ATTRIBUTES */
4457 
4458 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_ENABLE_MASK (0x00000001U)
4459 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
4460 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_ENABLE_MAX (0x00000001U)
4461 
4462 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_CAPTUREMODE_MASK (0x00000002U)
4463 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_CAPTUREMODE_SHIFT (0x00000001U)
4464 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_CAPTUREMODE_MAX (0x00000001U)
4465 
4466 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_DATACHECK (0x1U)
4467 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_FRAMEFREEZE (0x0U)
4468 
4469 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_SEEDSELECT_MASK (0x00000004U)
4470 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_SEEDSELECT_SHIFT (0x00000002U)
4471 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_SEEDSELECT_MAX (0x00000001U)
4472 
4473 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_ENABLE (0x1U)
4474 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_DISABLE (0x0U)
4475 
4476 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_THRESHOLD_MASK (0x000007F8U)
4477 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_THRESHOLD_SHIFT (0x00000003U)
4478 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_THRESHOLD_MAX (0x000000FFU)
4479 
4480 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_FRAMESKIP_MASK (0x00001800U)
4481 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_FRAMESKIP_SHIFT (0x0000000BU)
4482 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_FRAMESKIP_MAX (0x00000003U)
4483 
4484 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_DISABLE (0x0U)
4485 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_EVEN (0x1U)
4486 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_ODD (0x2U)
4487 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_RESERVED (0x3U)
4488 
4489 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_RESERVED_MASK (0xFFFFE000U)
4490 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_RESERVED_SHIFT (0x0000000DU)
4491 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_RESERVED_MAX (0x0007FFFFU)
4492 
4493 /* SAFETY_CAPT_SIGNATURE */
4494 
4495 #define CSL_DSS_VIDL1_SAFETY_CAPT_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
4496 #define CSL_DSS_VIDL1_SAFETY_CAPT_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
4497 #define CSL_DSS_VIDL1_SAFETY_CAPT_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
4498 
4499 /* SAFETY_POSITION */
4500 
4501 #define CSL_DSS_VIDL1_SAFETY_POSITION_POSX_MASK (0x00003FFFU)
4502 #define CSL_DSS_VIDL1_SAFETY_POSITION_POSX_SHIFT (0x00000000U)
4503 #define CSL_DSS_VIDL1_SAFETY_POSITION_POSX_MAX (0x00003FFFU)
4504 
4505 #define CSL_DSS_VIDL1_SAFETY_POSITION_POSY_MASK (0x3FFF0000U)
4506 #define CSL_DSS_VIDL1_SAFETY_POSITION_POSY_SHIFT (0x00000010U)
4507 #define CSL_DSS_VIDL1_SAFETY_POSITION_POSY_MAX (0x00003FFFU)
4508 
4509 /* SAFETY_REF_SIGNATURE */
4510 
4511 #define CSL_DSS_VIDL1_SAFETY_REF_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
4512 #define CSL_DSS_VIDL1_SAFETY_REF_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
4513 #define CSL_DSS_VIDL1_SAFETY_REF_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
4514 
4515 /* SAFETY_SIZE */
4516 
4517 #define CSL_DSS_VIDL1_SAFETY_SIZE_SIZEX_MASK (0x00003FFFU)
4518 #define CSL_DSS_VIDL1_SAFETY_SIZE_SIZEX_SHIFT (0x00000000U)
4519 #define CSL_DSS_VIDL1_SAFETY_SIZE_SIZEX_MAX (0x00003FFFU)
4520 
4521 #define CSL_DSS_VIDL1_SAFETY_SIZE_SIZEY_MASK (0x3FFF0000U)
4522 #define CSL_DSS_VIDL1_SAFETY_SIZE_SIZEY_SHIFT (0x00000010U)
4523 #define CSL_DSS_VIDL1_SAFETY_SIZE_SIZEY_MAX (0x00003FFFU)
4524 
4525 /* SAFETY_LFSR_SEED */
4526 
4527 #define CSL_DSS_VIDL1_SAFETY_LFSR_SEED_SEED_MASK (0xFFFFFFFFU)
4528 #define CSL_DSS_VIDL1_SAFETY_LFSR_SEED_SEED_SHIFT (0x00000000U)
4529 #define CSL_DSS_VIDL1_SAFETY_LFSR_SEED_SEED_MAX (0xFFFFFFFFU)
4530 
4531 /* LUMAKEY */
4532 
4533 #define CSL_DSS_VIDL1_LUMAKEY_LUMAKEYMIN_MASK (0x00000FFFU)
4534 #define CSL_DSS_VIDL1_LUMAKEY_LUMAKEYMIN_SHIFT (0x00000000U)
4535 #define CSL_DSS_VIDL1_LUMAKEY_LUMAKEYMIN_MAX (0x00000FFFU)
4536 
4537 #define CSL_DSS_VIDL1_LUMAKEY_RESERVED_MASK (0x0000F000U)
4538 #define CSL_DSS_VIDL1_LUMAKEY_RESERVED_SHIFT (0x0000000CU)
4539 #define CSL_DSS_VIDL1_LUMAKEY_RESERVED_MAX (0x0000000FU)
4540 
4541 #define CSL_DSS_VIDL1_LUMAKEY_LUMAKEYMAX_MASK (0x0FFF0000U)
4542 #define CSL_DSS_VIDL1_LUMAKEY_LUMAKEYMAX_SHIFT (0x00000010U)
4543 #define CSL_DSS_VIDL1_LUMAKEY_LUMAKEYMAX_MAX (0x00000FFFU)
4544 
4545 #define CSL_DSS_VIDL1_LUMAKEY_RESERVED1_MASK (0xF0000000U)
4546 #define CSL_DSS_VIDL1_LUMAKEY_RESERVED1_SHIFT (0x0000001CU)
4547 #define CSL_DSS_VIDL1_LUMAKEY_RESERVED1_MAX (0x0000000FU)
4548 
4549 /* DMA_BUFSIZE */
4550 
4551 #define CSL_DSS_VIDL1_DMA_BUFSIZE_BUFSIZE_MASK (0x0000001FU)
4552 #define CSL_DSS_VIDL1_DMA_BUFSIZE_BUFSIZE_SHIFT (0x00000000U)
4553 #define CSL_DSS_VIDL1_DMA_BUFSIZE_BUFSIZE_MAX (0x0000001FU)
4554 
4555 #define CSL_DSS_VIDL1_DMA_BUFSIZE_RESERVED_MASK (0xFFFFFFE0U)
4556 #define CSL_DSS_VIDL1_DMA_BUFSIZE_RESERVED_SHIFT (0x00000005U)
4557 #define CSL_DSS_VIDL1_DMA_BUFSIZE_RESERVED_MAX (0x07FFFFFFU)
4558 
4559 /* CROP */
4560 
4561 #define CSL_DSS_VIDL1_CROP_CROPLEFT_MASK (0x0000001FU)
4562 #define CSL_DSS_VIDL1_CROP_CROPLEFT_SHIFT (0x00000000U)
4563 #define CSL_DSS_VIDL1_CROP_CROPLEFT_MAX (0x0000001FU)
4564 
4565 #define CSL_DSS_VIDL1_CROP_CROPRIGHT_MASK (0x00001F00U)
4566 #define CSL_DSS_VIDL1_CROP_CROPRIGHT_SHIFT (0x00000008U)
4567 #define CSL_DSS_VIDL1_CROP_CROPRIGHT_MAX (0x0000001FU)
4568 
4569 #define CSL_DSS_VIDL1_CROP_CROPTOP_MASK (0x001F0000U)
4570 #define CSL_DSS_VIDL1_CROP_CROPTOP_SHIFT (0x00000010U)
4571 #define CSL_DSS_VIDL1_CROP_CROPTOP_MAX (0x0000001FU)
4572 
4573 #define CSL_DSS_VIDL1_CROP_CROPBOTTOM_MASK (0x1F000000U)
4574 #define CSL_DSS_VIDL1_CROP_CROPBOTTOM_SHIFT (0x00000018U)
4575 #define CSL_DSS_VIDL1_CROP_CROPBOTTOM_MAX (0x0000001FU)
4576 
4577 /* SECURE */
4578 
4579 #define CSL_DSS_VIDL1_SECURE_SECURE_MASK (0x00000001U)
4580 #define CSL_DSS_VIDL1_SECURE_SECURE_SHIFT (0x00000000U)
4581 #define CSL_DSS_VIDL1_SECURE_SECURE_MAX (0x00000001U)
4582 
4583 #define CSL_DSS_VIDL1_SECURE_SECURE_VAL_SECUREDIS (0x0U)
4584 #define CSL_DSS_VIDL1_SECURE_SECURE_VAL_SECUREEN (0x1U)
4585 
4586 #define CSL_DSS_VIDL1_SECURE_RESERVED_MASK (0xFFFFFFFEU)
4587 #define CSL_DSS_VIDL1_SECURE_RESERVED_SHIFT (0x00000001U)
4588 #define CSL_DSS_VIDL1_SECURE_RESERVED_MAX (0x7FFFFFFFU)
4589 
4590 /* PIPE_GO */
4591 
4592 #define CSL_DSS_VIDL1_PIPE_GO_GOBIT_MASK (0x00000001U)
4593 #define CSL_DSS_VIDL1_PIPE_GO_GOBIT_SHIFT (0x00000000U)
4594 #define CSL_DSS_VIDL1_PIPE_GO_GOBIT_MAX (0x00000001U)
4595 
4596 #define CSL_DSS_VIDL1_PIPE_GO_GOBIT_VAL_HFUISR (0x0U)
4597 #define CSL_DSS_VIDL1_PIPE_GO_GOBIT_VAL_UFPSR (0x1U)
4598 
4599 #define CSL_DSS_VIDL1_PIPE_GO_RESERVED_MASK (0xFFFFFFFEU)
4600 #define CSL_DSS_VIDL1_PIPE_GO_RESERVED_SHIFT (0x00000001U)
4601 #define CSL_DSS_VIDL1_PIPE_GO_RESERVED_MAX (0x7FFFFFFFU)
4602 
4603 /**************************************************************************
4604 * Hardware Region : VIDL2 Registers
4605 **************************************************************************/
4606 
4607 
4608 /**************************************************************************
4609 * Register Overlay Structure
4610 **************************************************************************/
4611 
4612 typedef struct {
4613  volatile uint8_t Resv_32[32];
4614  volatile uint32_t ATTRIBUTES; /* ATTRIBUTES */
4615  volatile uint32_t ATTRIBUTES2; /* ATTRIBUTES2 */
4616  volatile uint32_t BA_0; /* BA_0 */
4617  volatile uint32_t BA_1; /* BA_1 */
4618  volatile uint32_t BA_UV_0; /* BA_UV_0 */
4619  volatile uint32_t BA_UV_1; /* BA_UV_1 */
4620  volatile uint32_t BUF_SIZE_STATUS; /* BUF_SIZE_STATUS */
4621  volatile uint32_t BUF_THRESHOLD; /* BUF_THRESHOLD */
4622  volatile uint32_t CSC_COEF0; /* CSC_COEF0 */
4623  volatile uint32_t CSC_COEF1; /* CSC_COEF1 */
4624  volatile uint32_t CSC_COEF2; /* CSC_COEF2 */
4625  volatile uint32_t CSC_COEF3; /* CSC_COEF3 */
4626  volatile uint32_t CSC_COEF4; /* CSC_COEF4 */
4627  volatile uint32_t CSC_COEF5; /* CSC_COEF5 */
4628  volatile uint32_t CSC_COEF6; /* CSC_COEF6 */
4629  volatile uint8_t Resv_508[416];
4630  volatile uint32_t GLOBAL_ALPHA; /* GLOBAL_ALPHA */
4631  volatile uint8_t Resv_520[8];
4632  volatile uint32_t MFLAG_THRESHOLD; /* MFLAG_THRESHOLD */
4633  volatile uint32_t PICTURE_SIZE; /* PICTURE_SIZE */
4634  volatile uint32_t PIXEL_INC; /* PIXEL_INC */
4635  volatile uint8_t Resv_536[4];
4636  volatile uint32_t PRELOAD; /* PRELOAD */
4637  volatile uint32_t ROW_INC; /* ROW_INC */
4638  volatile uint8_t Resv_556[12];
4639  volatile uint32_t BA_EXT_0; /* BA_EXT_0 */
4640  volatile uint32_t BA_EXT_1; /* BA_EXT_1 */
4641  volatile uint32_t BA_UV_EXT_0; /* BA_UV_EXT_0 */
4642  volatile uint32_t BA_UV_EXT_1; /* BA_UV_EXT_1 */
4643  volatile uint32_t CSC_COEF7; /* CSC_COEF7 */
4644  volatile uint8_t Resv_584[8];
4645  volatile uint32_t ROW_INC_UV; /* ROW_INC_UV */
4646  volatile uint32_t TILE; /* TILE */
4647  volatile uint32_t TILE2; /* TILE2 */
4648  volatile uint32_t FBDC_ATTRIBUTES; /* FBDC_ATTRIBUTES */
4649  volatile uint32_t FBDC_CLEAR_COLOR; /* FBDC_CLEAR_COLOR */
4650  volatile uint8_t Resv_608[4];
4651  volatile uint32_t CLUT_0; /* CLUT_0 */
4652  volatile uint32_t CLUT_1; /* CLUT_1 */
4653  volatile uint32_t CLUT_2; /* CLUT_2 */
4654  volatile uint32_t CLUT_3; /* CLUT_3 */
4655  volatile uint32_t CLUT_4; /* CLUT_4 */
4656  volatile uint32_t CLUT_5; /* CLUT_5 */
4657  volatile uint32_t CLUT_6; /* CLUT_6 */
4658  volatile uint32_t CLUT_7; /* CLUT_7 */
4659  volatile uint32_t CLUT_8; /* CLUT_8 */
4660  volatile uint32_t CLUT_9; /* CLUT_9 */
4661  volatile uint32_t CLUT_10; /* CLUT_10 */
4662  volatile uint32_t CLUT_11; /* CLUT_11 */
4663  volatile uint32_t CLUT_12; /* CLUT_12 */
4664  volatile uint32_t CLUT_13; /* CLUT_13 */
4665  volatile uint32_t CLUT_14; /* CLUT_14 */
4666  volatile uint32_t CLUT_15; /* CLUT_15 */
4667  volatile uint32_t SAFETY_ATTRIBUTES; /* SAFETY_ATTRIBUTES */
4668  volatile uint32_t SAFETY_CAPT_SIGNATURE; /* SAFETY_CAPT_SIGNATURE */
4669  volatile uint32_t SAFETY_POSITION; /* SAFETY_POSITION */
4670  volatile uint32_t SAFETY_REF_SIGNATURE; /* SAFETY_REF_SIGNATURE */
4671  volatile uint32_t SAFETY_SIZE; /* SAFETY_SIZE */
4672  volatile uint32_t SAFETY_LFSR_SEED; /* SAFETY_LFSR_SEED */
4673  volatile uint32_t LUMAKEY; /* LUMAKEY */
4674  volatile uint32_t DMA_BUFSIZE; /* DMA_BUFSIZE */
4675  volatile uint32_t CROP; /* CROP */
4676  volatile uint32_t SECURE; /* SECURE */
4677  volatile uint32_t PIPE_GO; /* PIPE_GO */
4679 
4680 
4681 /**************************************************************************
4682 * Register Macros
4683 **************************************************************************/
4684 
4685 #define CSL_DSS_VIDL2_ATTRIBUTES (0x00000020U)
4686 #define CSL_DSS_VIDL2_ATTRIBUTES2 (0x00000024U)
4687 #define CSL_DSS_VIDL2_BA_0 (0x00000028U)
4688 #define CSL_DSS_VIDL2_BA_1 (0x0000002CU)
4689 #define CSL_DSS_VIDL2_BA_UV_0 (0x00000030U)
4690 #define CSL_DSS_VIDL2_BA_UV_1 (0x00000034U)
4691 #define CSL_DSS_VIDL2_BUF_SIZE_STATUS (0x00000038U)
4692 #define CSL_DSS_VIDL2_BUF_THRESHOLD (0x0000003CU)
4693 #define CSL_DSS_VIDL2_CSC_COEF0 (0x00000040U)
4694 #define CSL_DSS_VIDL2_CSC_COEF1 (0x00000044U)
4695 #define CSL_DSS_VIDL2_CSC_COEF2 (0x00000048U)
4696 #define CSL_DSS_VIDL2_CSC_COEF3 (0x0000004CU)
4697 #define CSL_DSS_VIDL2_CSC_COEF4 (0x00000050U)
4698 #define CSL_DSS_VIDL2_CSC_COEF5 (0x00000054U)
4699 #define CSL_DSS_VIDL2_CSC_COEF6 (0x00000058U)
4700 #define CSL_DSS_VIDL2_GLOBAL_ALPHA (0x000001FCU)
4701 #define CSL_DSS_VIDL2_MFLAG_THRESHOLD (0x00000208U)
4702 #define CSL_DSS_VIDL2_PICTURE_SIZE (0x0000020CU)
4703 #define CSL_DSS_VIDL2_PIXEL_INC (0x00000210U)
4704 #define CSL_DSS_VIDL2_PRELOAD (0x00000218U)
4705 #define CSL_DSS_VIDL2_ROW_INC (0x0000021CU)
4706 #define CSL_DSS_VIDL2_BA_EXT_0 (0x0000022CU)
4707 #define CSL_DSS_VIDL2_BA_EXT_1 (0x00000230U)
4708 #define CSL_DSS_VIDL2_BA_UV_EXT_0 (0x00000234U)
4709 #define CSL_DSS_VIDL2_BA_UV_EXT_1 (0x00000238U)
4710 #define CSL_DSS_VIDL2_CSC_COEF7 (0x0000023CU)
4711 #define CSL_DSS_VIDL2_ROW_INC_UV (0x00000248U)
4712 #define CSL_DSS_VIDL2_TILE (0x0000024CU)
4713 #define CSL_DSS_VIDL2_TILE2 (0x00000250U)
4714 #define CSL_DSS_VIDL2_FBDC_ATTRIBUTES (0x00000254U)
4715 #define CSL_DSS_VIDL2_FBDC_CLEAR_COLOR (0x00000258U)
4716 #define CSL_DSS_VIDL2_CLUT_0 (0x00000260U)
4717 #define CSL_DSS_VIDL2_CLUT_1 (0x00000264U)
4718 #define CSL_DSS_VIDL2_CLUT_2 (0x00000268U)
4719 #define CSL_DSS_VIDL2_CLUT_3 (0x0000026CU)
4720 #define CSL_DSS_VIDL2_CLUT_4 (0x00000270U)
4721 #define CSL_DSS_VIDL2_CLUT_5 (0x00000274U)
4722 #define CSL_DSS_VIDL2_CLUT_6 (0x00000278U)
4723 #define CSL_DSS_VIDL2_CLUT_7 (0x0000027CU)
4724 #define CSL_DSS_VIDL2_CLUT_8 (0x00000280U)
4725 #define CSL_DSS_VIDL2_CLUT_9 (0x00000284U)
4726 #define CSL_DSS_VIDL2_CLUT_10 (0x00000288U)
4727 #define CSL_DSS_VIDL2_CLUT_11 (0x0000028CU)
4728 #define CSL_DSS_VIDL2_CLUT_12 (0x00000290U)
4729 #define CSL_DSS_VIDL2_CLUT_13 (0x00000294U)
4730 #define CSL_DSS_VIDL2_CLUT_14 (0x00000298U)
4731 #define CSL_DSS_VIDL2_CLUT_15 (0x0000029CU)
4732 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES (0x000002A0U)
4733 #define CSL_DSS_VIDL2_SAFETY_CAPT_SIGNATURE (0x000002A4U)
4734 #define CSL_DSS_VIDL2_SAFETY_POSITION (0x000002A8U)
4735 #define CSL_DSS_VIDL2_SAFETY_REF_SIGNATURE (0x000002ACU)
4736 #define CSL_DSS_VIDL2_SAFETY_SIZE (0x000002B0U)
4737 #define CSL_DSS_VIDL2_SAFETY_LFSR_SEED (0x000002B4U)
4738 #define CSL_DSS_VIDL2_LUMAKEY (0x000002B8U)
4739 #define CSL_DSS_VIDL2_DMA_BUFSIZE (0x000002BCU)
4740 #define CSL_DSS_VIDL2_CROP (0x000002C0U)
4741 #define CSL_DSS_VIDL2_SECURE (0x000002C4U)
4742 #define CSL_DSS_VIDL2_PIPE_GO (0x000002C8U)
4743 
4744 /**************************************************************************
4745 * Field Definition Macros
4746 **************************************************************************/
4747 
4748 
4749 /* ATTRIBUTES */
4750 
4751 #define CSL_DSS_VIDL2_ATTRIBUTES_ENABLE_MASK (0x00000001U)
4752 #define CSL_DSS_VIDL2_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
4753 #define CSL_DSS_VIDL2_ATTRIBUTES_ENABLE_MAX (0x00000001U)
4754 
4755 #define CSL_DSS_VIDL2_ATTRIBUTES_ENABLE_VAL_VIDEOENB (0x1U)
4756 #define CSL_DSS_VIDL2_ATTRIBUTES_ENABLE_VAL_VIDEODIS (0x0U)
4757 
4758 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_MASK (0x0000007EU)
4759 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_SHIFT (0x00000001U)
4760 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_MAX (0x0000003FU)
4761 
4762 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_ARGB16_4444 (0x0U)
4763 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_ABGR16_4444 (0x1U)
4764 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_RGBA16_4444 (0x2U)
4765 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_RGB16_565 (0x3U)
4766 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_BGR16_565 (0x4U)
4767 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_ARGB16_1555 (0x5U)
4768 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_ABGR16_1555 (0x6U)
4769 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_ARGB32_8888 (0x7U)
4770 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_ABGR32_8888 (0x8U)
4771 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_RGBA32_8888 (0x9U)
4772 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_BGRA32_8888 (0xAU)
4773 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_RGB24P_888 (0xBU)
4774 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_BGR24P_888 (0xCU)
4775 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_ARGB32_2101010 (0xEU)
4776 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_ABGR32_2101010 (0xFU)
4777 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_ARGB64_16161616 (0x10U)
4778 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_RGBA64_16161616 (0x11U)
4779 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_BITMAP1 (0x12U)
4780 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_BITMAP2 (0x13U)
4781 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_BITMAP4 (0x14U)
4782 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_BITMAP8 (0x15U)
4783 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_RGB565A8 (0x16U)
4784 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_BGR565A8 (0x17U)
4785 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_XRGB16_4444 (0x20U)
4786 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_XBGR16_4444 (0x21U)
4787 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_RGBX16_4444 (0x22U)
4788 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_XRGB16_1555 (0x25U)
4789 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_XBGR16_1555 (0x26U)
4790 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_XRGB32_8888 (0x27U)
4791 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_XBGR32_8888 (0x28U)
4792 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_RGBX32_8888 (0x29U)
4793 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_BGRX32_8888 (0x2AU)
4794 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_XRGB32_2101010 (0x2EU)
4795 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_XBGR32_2101010 (0x2FU)
4796 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_XRGB64_16161616 (0x30U)
4797 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_RGBX64_16161616 (0x31U)
4798 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_YUV422_NV12 (0x3CU)
4799 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_YUV420_NV12 (0x3DU)
4800 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_YUV422_YUV2 (0x3EU)
4801 #define CSL_DSS_VIDL2_ATTRIBUTES_FORMAT_VAL_YUV422_UYVY (0x3FU)
4802 
4803 #define CSL_DSS_VIDL2_ATTRIBUTES_RESERVED8_MASK (0x00000180U)
4804 #define CSL_DSS_VIDL2_ATTRIBUTES_RESERVED8_SHIFT (0x00000007U)
4805 #define CSL_DSS_VIDL2_ATTRIBUTES_RESERVED8_MAX (0x00000003U)
4806 
4807 #define CSL_DSS_VIDL2_ATTRIBUTES_COLORCONVENABLE_MASK (0x00000200U)
4808 #define CSL_DSS_VIDL2_ATTRIBUTES_COLORCONVENABLE_SHIFT (0x00000009U)
4809 #define CSL_DSS_VIDL2_ATTRIBUTES_COLORCONVENABLE_MAX (0x00000001U)
4810 
4811 #define CSL_DSS_VIDL2_ATTRIBUTES_COLORCONVENABLE_VAL_COLSPCENB (0x1U)
4812 #define CSL_DSS_VIDL2_ATTRIBUTES_COLORCONVENABLE_VAL_COLSPCDIS (0x0U)
4813 
4814 #define CSL_DSS_VIDL2_ATTRIBUTES_NIBBLEMODE_MASK (0x00000400U)
4815 #define CSL_DSS_VIDL2_ATTRIBUTES_NIBBLEMODE_SHIFT (0x0000000AU)
4816 #define CSL_DSS_VIDL2_ATTRIBUTES_NIBBLEMODE_MAX (0x00000001U)
4817 
4818 #define CSL_DSS_VIDL2_ATTRIBUTES_NIBBLEMODE_VAL_NIBBLEMODEEN (0x1U)
4819 #define CSL_DSS_VIDL2_ATTRIBUTES_NIBBLEMODE_VAL_NIBBLEMODEDIS (0x0U)
4820 
4821 #define CSL_DSS_VIDL2_ATTRIBUTES_FULLRANGE_MASK (0x00000800U)
4822 #define CSL_DSS_VIDL2_ATTRIBUTES_FULLRANGE_SHIFT (0x0000000BU)
4823 #define CSL_DSS_VIDL2_ATTRIBUTES_FULLRANGE_MAX (0x00000001U)
4824 
4825 #define CSL_DSS_VIDL2_ATTRIBUTES_FULLRANGE_VAL_FULLRANGE (0x1U)
4826 #define CSL_DSS_VIDL2_ATTRIBUTES_FULLRANGE_VAL_LIMRANGE (0x0U)
4827 
4828 #define CSL_DSS_VIDL2_ATTRIBUTES_FLIP_MASK (0x00001000U)
4829 #define CSL_DSS_VIDL2_ATTRIBUTES_FLIP_SHIFT (0x0000000CU)
4830 #define CSL_DSS_VIDL2_ATTRIBUTES_FLIP_MAX (0x00000001U)
4831 
4832 #define CSL_DSS_VIDL2_ATTRIBUTES_FLIP_VAL_FLIP (0x1U)
4833 #define CSL_DSS_VIDL2_ATTRIBUTES_FLIP_VAL_NOFLIP (0x0U)
4834 
4835 #define CSL_DSS_VIDL2_ATTRIBUTES_CROP_MASK (0x00002000U)
4836 #define CSL_DSS_VIDL2_ATTRIBUTES_CROP_SHIFT (0x0000000DU)
4837 #define CSL_DSS_VIDL2_ATTRIBUTES_CROP_MAX (0x00000001U)
4838 
4839 #define CSL_DSS_VIDL2_ATTRIBUTES_CROP_VAL_CROPEN (0x1U)
4840 #define CSL_DSS_VIDL2_ATTRIBUTES_CROP_VAL_CROPDIS (0x0U)
4841 
4842 #define CSL_DSS_VIDL2_ATTRIBUTES_RESERVED9_MASK (0x0001C000U)
4843 #define CSL_DSS_VIDL2_ATTRIBUTES_RESERVED9_SHIFT (0x0000000EU)
4844 #define CSL_DSS_VIDL2_ATTRIBUTES_RESERVED9_MAX (0x00000007U)
4845 
4846 #define CSL_DSS_VIDL2_ATTRIBUTES_SELFREFRESHAUTO_MASK (0x00020000U)
4847 #define CSL_DSS_VIDL2_ATTRIBUTES_SELFREFRESHAUTO_SHIFT (0x00000011U)
4848 #define CSL_DSS_VIDL2_ATTRIBUTES_SELFREFRESHAUTO_MAX (0x00000001U)
4849 
4850 #define CSL_DSS_VIDL2_ATTRIBUTES_SELFREFRESHAUTO_VAL_SELFREFRESHAUTOEN (0x1U)
4851 #define CSL_DSS_VIDL2_ATTRIBUTES_SELFREFRESHAUTO_VAL_SELFREFRESHAUTODIS (0x0U)
4852 
4853 #define CSL_DSS_VIDL2_ATTRIBUTES_RESERVED7_MASK (0x00040000U)
4854 #define CSL_DSS_VIDL2_ATTRIBUTES_RESERVED7_SHIFT (0x00000012U)
4855 #define CSL_DSS_VIDL2_ATTRIBUTES_RESERVED7_MAX (0x00000001U)
4856 
4857 #define CSL_DSS_VIDL2_ATTRIBUTES_BUFPRELOAD_MASK (0x00080000U)
4858 #define CSL_DSS_VIDL2_ATTRIBUTES_BUFPRELOAD_SHIFT (0x00000013U)
4859 #define CSL_DSS_VIDL2_ATTRIBUTES_BUFPRELOAD_MAX (0x00000001U)
4860 
4861 #define CSL_DSS_VIDL2_ATTRIBUTES_BUFPRELOAD_VAL_HIGHTHRES (0x1U)
4862 #define CSL_DSS_VIDL2_ATTRIBUTES_BUFPRELOAD_VAL_DEFVAL (0x0U)
4863 
4864 #define CSL_DSS_VIDL2_ATTRIBUTES_RESERVED2_MASK (0x00100000U)
4865 #define CSL_DSS_VIDL2_ATTRIBUTES_RESERVED2_SHIFT (0x00000014U)
4866 #define CSL_DSS_VIDL2_ATTRIBUTES_RESERVED2_MAX (0x00000001U)
4867 
4868 #define CSL_DSS_VIDL2_ATTRIBUTES_RESERVED3_MASK (0x00200000U)
4869 #define CSL_DSS_VIDL2_ATTRIBUTES_RESERVED3_SHIFT (0x00000015U)
4870 #define CSL_DSS_VIDL2_ATTRIBUTES_RESERVED3_MAX (0x00000001U)
4871 
4872 #define CSL_DSS_VIDL2_ATTRIBUTES_RESERVED6_MASK (0x00400000U)
4873 #define CSL_DSS_VIDL2_ATTRIBUTES_RESERVED6_SHIFT (0x00000016U)
4874 #define CSL_DSS_VIDL2_ATTRIBUTES_RESERVED6_MAX (0x00000001U)
4875 
4876 #define CSL_DSS_VIDL2_ATTRIBUTES_ARBITRATION_MASK (0x00800000U)
4877 #define CSL_DSS_VIDL2_ATTRIBUTES_ARBITRATION_SHIFT (0x00000017U)
4878 #define CSL_DSS_VIDL2_ATTRIBUTES_ARBITRATION_MAX (0x00000001U)
4879 
4880 #define CSL_DSS_VIDL2_ATTRIBUTES_ARBITRATION_VAL_HIGHPRIO (0x1U)
4881 #define CSL_DSS_VIDL2_ATTRIBUTES_ARBITRATION_VAL_NORMALPRIO (0x0U)
4882 
4883 #define CSL_DSS_VIDL2_ATTRIBUTES_SELFREFRESH_MASK (0x01000000U)
4884 #define CSL_DSS_VIDL2_ATTRIBUTES_SELFREFRESH_SHIFT (0x00000018U)
4885 #define CSL_DSS_VIDL2_ATTRIBUTES_SELFREFRESH_MAX (0x00000001U)
4886 
4887 #define CSL_DSS_VIDL2_ATTRIBUTES_SELFREFRESH_VAL_SELFREFRESHENB (0x1U)
4888 #define CSL_DSS_VIDL2_ATTRIBUTES_SELFREFRESH_VAL_SELFREFRESHDIS (0x0U)
4889 
4890 #define CSL_DSS_VIDL2_ATTRIBUTES_RESERVED5_MASK (0x0E000000U)
4891 #define CSL_DSS_VIDL2_ATTRIBUTES_RESERVED5_SHIFT (0x00000019U)
4892 #define CSL_DSS_VIDL2_ATTRIBUTES_RESERVED5_MAX (0x00000007U)
4893 
4894 #define CSL_DSS_VIDL2_ATTRIBUTES_PREMULTIPLYALPHA_MASK (0x10000000U)
4895 #define CSL_DSS_VIDL2_ATTRIBUTES_PREMULTIPLYALPHA_SHIFT (0x0000001CU)
4896 #define CSL_DSS_VIDL2_ATTRIBUTES_PREMULTIPLYALPHA_MAX (0x00000001U)
4897 
4898 #define CSL_DSS_VIDL2_ATTRIBUTES_PREMULTIPLYALPHA_VAL_PREMULTIPLIEDALPHA (0x1U)
4899 #define CSL_DSS_VIDL2_ATTRIBUTES_PREMULTIPLYALPHA_VAL_NONPREMULTIPLIEDALPHA (0x0U)
4900 
4901 #define CSL_DSS_VIDL2_ATTRIBUTES_GAMMAINVERSIONPOS_MASK (0x20000000U)
4902 #define CSL_DSS_VIDL2_ATTRIBUTES_GAMMAINVERSIONPOS_SHIFT (0x0000001DU)
4903 #define CSL_DSS_VIDL2_ATTRIBUTES_GAMMAINVERSIONPOS_MAX (0x00000001U)
4904 
4905 #define CSL_DSS_VIDL2_ATTRIBUTES_GAMMAINVERSIONPOS_VAL_PRESCALER (0x0U)
4906 #define CSL_DSS_VIDL2_ATTRIBUTES_GAMMAINVERSIONPOS_VAL_POSTSCALER (0x1U)
4907 
4908 #define CSL_DSS_VIDL2_ATTRIBUTES_GAMMAINVERSION_MASK (0x40000000U)
4909 #define CSL_DSS_VIDL2_ATTRIBUTES_GAMMAINVERSION_SHIFT (0x0000001EU)
4910 #define CSL_DSS_VIDL2_ATTRIBUTES_GAMMAINVERSION_MAX (0x00000001U)
4911 
4912 #define CSL_DSS_VIDL2_ATTRIBUTES_GAMMAINVERSION_VAL_INVGAMMAEN (0x1U)
4913 #define CSL_DSS_VIDL2_ATTRIBUTES_GAMMAINVERSION_VAL_INVGAMMADIS (0x0U)
4914 
4915 #define CSL_DSS_VIDL2_ATTRIBUTES_LUMAKEYENABLE_MASK (0x80000000U)
4916 #define CSL_DSS_VIDL2_ATTRIBUTES_LUMAKEYENABLE_SHIFT (0x0000001FU)
4917 #define CSL_DSS_VIDL2_ATTRIBUTES_LUMAKEYENABLE_MAX (0x00000001U)
4918 
4919 #define CSL_DSS_VIDL2_ATTRIBUTES_LUMAKEYENABLE_VAL_LUMAKEYEN (0x1U)
4920 #define CSL_DSS_VIDL2_ATTRIBUTES_LUMAKEYENABLE_VAL_LUMAKEYDIS (0x0U)
4921 
4922 /* ATTRIBUTES2 */
4923 
4924 #define CSL_DSS_VIDL2_ATTRIBUTES2_VC1ENABLE_MASK (0x00000001U)
4925 #define CSL_DSS_VIDL2_ATTRIBUTES2_VC1ENABLE_SHIFT (0x00000000U)
4926 #define CSL_DSS_VIDL2_ATTRIBUTES2_VC1ENABLE_MAX (0x00000001U)
4927 
4928 #define CSL_DSS_VIDL2_ATTRIBUTES2_VC1ENABLE_VAL_VC1ENB (0x1U)
4929 #define CSL_DSS_VIDL2_ATTRIBUTES2_VC1ENABLE_VAL_VC1DIS (0x0U)
4930 
4931 #define CSL_DSS_VIDL2_ATTRIBUTES2_VC1_RANGE_Y_MASK (0x0000000EU)
4932 #define CSL_DSS_VIDL2_ATTRIBUTES2_VC1_RANGE_Y_SHIFT (0x00000001U)
4933 #define CSL_DSS_VIDL2_ATTRIBUTES2_VC1_RANGE_Y_MAX (0x00000007U)
4934 
4935 #define CSL_DSS_VIDL2_ATTRIBUTES2_VC1_RANGE_CBCR_MASK (0x00000070U)
4936 #define CSL_DSS_VIDL2_ATTRIBUTES2_VC1_RANGE_CBCR_SHIFT (0x00000004U)
4937 #define CSL_DSS_VIDL2_ATTRIBUTES2_VC1_RANGE_CBCR_MAX (0x00000007U)
4938 
4939 #define CSL_DSS_VIDL2_ATTRIBUTES2_YUV_SIZE_MASK (0x00000180U)
4940 #define CSL_DSS_VIDL2_ATTRIBUTES2_YUV_SIZE_SHIFT (0x00000007U)
4941 #define CSL_DSS_VIDL2_ATTRIBUTES2_YUV_SIZE_MAX (0x00000003U)
4942 
4943 #define CSL_DSS_VIDL2_ATTRIBUTES2_YUV_SIZE_VAL_8B (0x0U)
4944 #define CSL_DSS_VIDL2_ATTRIBUTES2_YUV_SIZE_VAL_10B (0x1U)
4945 #define CSL_DSS_VIDL2_ATTRIBUTES2_YUV_SIZE_VAL_12B (0x2U)
4946 
4947 #define CSL_DSS_VIDL2_ATTRIBUTES2_YUV_MODE_MASK (0x00000200U)
4948 #define CSL_DSS_VIDL2_ATTRIBUTES2_YUV_MODE_SHIFT (0x00000009U)
4949 #define CSL_DSS_VIDL2_ATTRIBUTES2_YUV_MODE_MAX (0x00000001U)
4950 
4951 #define CSL_DSS_VIDL2_ATTRIBUTES2_YUV_MODE_VAL_PACKED (0x0U)
4952 #define CSL_DSS_VIDL2_ATTRIBUTES2_YUV_MODE_VAL_UNPACKED (0x1U)
4953 
4954 #define CSL_DSS_VIDL2_ATTRIBUTES2_YUV_ALIGN_MASK (0x00000400U)
4955 #define CSL_DSS_VIDL2_ATTRIBUTES2_YUV_ALIGN_SHIFT (0x0000000AU)
4956 #define CSL_DSS_VIDL2_ATTRIBUTES2_YUV_ALIGN_MAX (0x00000001U)
4957 
4958 #define CSL_DSS_VIDL2_ATTRIBUTES2_YUV_ALIGN_VAL_MSB (0x1U)
4959 #define CSL_DSS_VIDL2_ATTRIBUTES2_YUV_ALIGN_VAL_LSB (0x0U)
4960 
4961 #define CSL_DSS_VIDL2_ATTRIBUTES2_RESERVED1_MASK (0x0000F800U)
4962 #define CSL_DSS_VIDL2_ATTRIBUTES2_RESERVED1_SHIFT (0x0000000BU)
4963 #define CSL_DSS_VIDL2_ATTRIBUTES2_RESERVED1_MAX (0x0000001FU)
4964 
4965 #define CSL_DSS_VIDL2_ATTRIBUTES2_RESERVED2_MASK (0x01F00000U)
4966 #define CSL_DSS_VIDL2_ATTRIBUTES2_RESERVED2_SHIFT (0x00000014U)
4967 #define CSL_DSS_VIDL2_ATTRIBUTES2_RESERVED2_MAX (0x0000001FU)
4968 
4969 #define CSL_DSS_VIDL2_ATTRIBUTES2_MPORTSEL_MASK (0x02000000U)
4970 #define CSL_DSS_VIDL2_ATTRIBUTES2_MPORTSEL_SHIFT (0x00000019U)
4971 #define CSL_DSS_VIDL2_ATTRIBUTES2_MPORTSEL_MAX (0x00000001U)
4972 
4973 #define CSL_DSS_VIDL2_ATTRIBUTES2_MPORTSEL_VAL_PRIMARY (0x0U)
4974 #define CSL_DSS_VIDL2_ATTRIBUTES2_MPORTSEL_VAL_SECONDARY (0x1U)
4975 
4976 #define CSL_DSS_VIDL2_ATTRIBUTES2_TAGS_MASK (0x7C000000U)
4977 #define CSL_DSS_VIDL2_ATTRIBUTES2_TAGS_SHIFT (0x0000001AU)
4978 #define CSL_DSS_VIDL2_ATTRIBUTES2_TAGS_MAX (0x0000001FU)
4979 
4980 #define CSL_DSS_VIDL2_ATTRIBUTES2_RESERVED3_MASK (0x80000000U)
4981 #define CSL_DSS_VIDL2_ATTRIBUTES2_RESERVED3_SHIFT (0x0000001FU)
4982 #define CSL_DSS_VIDL2_ATTRIBUTES2_RESERVED3_MAX (0x00000001U)
4983 
4984 /* BA_0 */
4985 
4986 #define CSL_DSS_VIDL2_BA_0_BA_MASK (0xFFFFFFFFU)
4987 #define CSL_DSS_VIDL2_BA_0_BA_SHIFT (0x00000000U)
4988 #define CSL_DSS_VIDL2_BA_0_BA_MAX (0xFFFFFFFFU)
4989 
4990 /* BA_1 */
4991 
4992 #define CSL_DSS_VIDL2_BA_1_BA_MASK (0xFFFFFFFFU)
4993 #define CSL_DSS_VIDL2_BA_1_BA_SHIFT (0x00000000U)
4994 #define CSL_DSS_VIDL2_BA_1_BA_MAX (0xFFFFFFFFU)
4995 
4996 /* BA_UV_0 */
4997 
4998 #define CSL_DSS_VIDL2_BA_UV_0_BA_MASK (0xFFFFFFFFU)
4999 #define CSL_DSS_VIDL2_BA_UV_0_BA_SHIFT (0x00000000U)
5000 #define CSL_DSS_VIDL2_BA_UV_0_BA_MAX (0xFFFFFFFFU)
5001 
5002 /* BA_UV_1 */
5003 
5004 #define CSL_DSS_VIDL2_BA_UV_1_BA_MASK (0xFFFFFFFFU)
5005 #define CSL_DSS_VIDL2_BA_UV_1_BA_SHIFT (0x00000000U)
5006 #define CSL_DSS_VIDL2_BA_UV_1_BA_MAX (0xFFFFFFFFU)
5007 
5008 /* BUF_SIZE_STATUS */
5009 
5010 #define CSL_DSS_VIDL2_BUF_SIZE_STATUS_BUFSIZE_MASK (0x0000FFFFU)
5011 #define CSL_DSS_VIDL2_BUF_SIZE_STATUS_BUFSIZE_SHIFT (0x00000000U)
5012 #define CSL_DSS_VIDL2_BUF_SIZE_STATUS_BUFSIZE_MAX (0x0000FFFFU)
5013 
5014 #define CSL_DSS_VIDL2_BUF_SIZE_STATUS_RESERVED_61_MASK (0xFFFF0000U)
5015 #define CSL_DSS_VIDL2_BUF_SIZE_STATUS_RESERVED_61_SHIFT (0x00000010U)
5016 #define CSL_DSS_VIDL2_BUF_SIZE_STATUS_RESERVED_61_MAX (0x0000FFFFU)
5017 
5018 /* BUF_THRESHOLD */
5019 
5020 #define CSL_DSS_VIDL2_BUF_THRESHOLD_BUFLOWTHRESHOLD_MASK (0x0000FFFFU)
5021 #define CSL_DSS_VIDL2_BUF_THRESHOLD_BUFLOWTHRESHOLD_SHIFT (0x00000000U)
5022 #define CSL_DSS_VIDL2_BUF_THRESHOLD_BUFLOWTHRESHOLD_MAX (0x0000FFFFU)
5023 
5024 #define CSL_DSS_VIDL2_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MASK (0xFFFF0000U)
5025 #define CSL_DSS_VIDL2_BUF_THRESHOLD_BUFHIGHTHRESHOLD_SHIFT (0x00000010U)
5026 #define CSL_DSS_VIDL2_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MAX (0x0000FFFFU)
5027 
5028 /* CSC_COEF0 */
5029 
5030 #define CSL_DSS_VIDL2_CSC_COEF0_C00_MASK (0x000007FFU)
5031 #define CSL_DSS_VIDL2_CSC_COEF0_C00_SHIFT (0x00000000U)
5032 #define CSL_DSS_VIDL2_CSC_COEF0_C00_MAX (0x000007FFU)
5033 
5034 #define CSL_DSS_VIDL2_CSC_COEF0_RESERVED_53_MASK (0x0000F800U)
5035 #define CSL_DSS_VIDL2_CSC_COEF0_RESERVED_53_SHIFT (0x0000000BU)
5036 #define CSL_DSS_VIDL2_CSC_COEF0_RESERVED_53_MAX (0x0000001FU)
5037 
5038 #define CSL_DSS_VIDL2_CSC_COEF0_C01_MASK (0x07FF0000U)
5039 #define CSL_DSS_VIDL2_CSC_COEF0_C01_SHIFT (0x00000010U)
5040 #define CSL_DSS_VIDL2_CSC_COEF0_C01_MAX (0x000007FFU)
5041 
5042 #define CSL_DSS_VIDL2_CSC_COEF0_RESERVED_52_MASK (0xF8000000U)
5043 #define CSL_DSS_VIDL2_CSC_COEF0_RESERVED_52_SHIFT (0x0000001BU)
5044 #define CSL_DSS_VIDL2_CSC_COEF0_RESERVED_52_MAX (0x0000001FU)
5045 
5046 /* CSC_COEF1 */
5047 
5048 #define CSL_DSS_VIDL2_CSC_COEF1_C02_MASK (0x000007FFU)
5049 #define CSL_DSS_VIDL2_CSC_COEF1_C02_SHIFT (0x00000000U)
5050 #define CSL_DSS_VIDL2_CSC_COEF1_C02_MAX (0x000007FFU)
5051 
5052 #define CSL_DSS_VIDL2_CSC_COEF1_RESERVED_55_MASK (0x0000F800U)
5053 #define CSL_DSS_VIDL2_CSC_COEF1_RESERVED_55_SHIFT (0x0000000BU)
5054 #define CSL_DSS_VIDL2_CSC_COEF1_RESERVED_55_MAX (0x0000001FU)
5055 
5056 #define CSL_DSS_VIDL2_CSC_COEF1_C10_MASK (0x07FF0000U)
5057 #define CSL_DSS_VIDL2_CSC_COEF1_C10_SHIFT (0x00000010U)
5058 #define CSL_DSS_VIDL2_CSC_COEF1_C10_MAX (0x000007FFU)
5059 
5060 #define CSL_DSS_VIDL2_CSC_COEF1_RESERVED_54_MASK (0xF8000000U)
5061 #define CSL_DSS_VIDL2_CSC_COEF1_RESERVED_54_SHIFT (0x0000001BU)
5062 #define CSL_DSS_VIDL2_CSC_COEF1_RESERVED_54_MAX (0x0000001FU)
5063 
5064 /* CSC_COEF2 */
5065 
5066 #define CSL_DSS_VIDL2_CSC_COEF2_C11_MASK (0x000007FFU)
5067 #define CSL_DSS_VIDL2_CSC_COEF2_C11_SHIFT (0x00000000U)
5068 #define CSL_DSS_VIDL2_CSC_COEF2_C11_MAX (0x000007FFU)
5069 
5070 #define CSL_DSS_VIDL2_CSC_COEF2_RESERVED_57_MASK (0x0000F800U)
5071 #define CSL_DSS_VIDL2_CSC_COEF2_RESERVED_57_SHIFT (0x0000000BU)
5072 #define CSL_DSS_VIDL2_CSC_COEF2_RESERVED_57_MAX (0x0000001FU)
5073 
5074 #define CSL_DSS_VIDL2_CSC_COEF2_C12_MASK (0x07FF0000U)
5075 #define CSL_DSS_VIDL2_CSC_COEF2_C12_SHIFT (0x00000010U)
5076 #define CSL_DSS_VIDL2_CSC_COEF2_C12_MAX (0x000007FFU)
5077 
5078 #define CSL_DSS_VIDL2_CSC_COEF2_RESERVED_56_MASK (0xF8000000U)
5079 #define CSL_DSS_VIDL2_CSC_COEF2_RESERVED_56_SHIFT (0x0000001BU)
5080 #define CSL_DSS_VIDL2_CSC_COEF2_RESERVED_56_MAX (0x0000001FU)
5081 
5082 /* CSC_COEF3 */
5083 
5084 #define CSL_DSS_VIDL2_CSC_COEF3_C20_MASK (0x000007FFU)
5085 #define CSL_DSS_VIDL2_CSC_COEF3_C20_SHIFT (0x00000000U)
5086 #define CSL_DSS_VIDL2_CSC_COEF3_C20_MAX (0x000007FFU)
5087 
5088 #define CSL_DSS_VIDL2_CSC_COEF3_RESERVED_59_MASK (0x0000F800U)
5089 #define CSL_DSS_VIDL2_CSC_COEF3_RESERVED_59_SHIFT (0x0000000BU)
5090 #define CSL_DSS_VIDL2_CSC_COEF3_RESERVED_59_MAX (0x0000001FU)
5091 
5092 #define CSL_DSS_VIDL2_CSC_COEF3_C21_MASK (0x07FF0000U)
5093 #define CSL_DSS_VIDL2_CSC_COEF3_C21_SHIFT (0x00000010U)
5094 #define CSL_DSS_VIDL2_CSC_COEF3_C21_MAX (0x000007FFU)
5095 
5096 #define CSL_DSS_VIDL2_CSC_COEF3_RESERVED_58_MASK (0xF8000000U)
5097 #define CSL_DSS_VIDL2_CSC_COEF3_RESERVED_58_SHIFT (0x0000001BU)
5098 #define CSL_DSS_VIDL2_CSC_COEF3_RESERVED_58_MAX (0x0000001FU)
5099 
5100 /* CSC_COEF4 */
5101 
5102 #define CSL_DSS_VIDL2_CSC_COEF4_C22_MASK (0x000007FFU)
5103 #define CSL_DSS_VIDL2_CSC_COEF4_C22_SHIFT (0x00000000U)
5104 #define CSL_DSS_VIDL2_CSC_COEF4_C22_MAX (0x000007FFU)
5105 
5106 #define CSL_DSS_VIDL2_CSC_COEF4_RESERVED_60_MASK (0xFFFFF800U)
5107 #define CSL_DSS_VIDL2_CSC_COEF4_RESERVED_60_SHIFT (0x0000000BU)
5108 #define CSL_DSS_VIDL2_CSC_COEF4_RESERVED_60_MAX (0x001FFFFFU)
5109 
5110 /* CSC_COEF5 */
5111 
5112 #define CSL_DSS_VIDL2_CSC_COEF5_RESERVED_MASK (0x00000007U)
5113 #define CSL_DSS_VIDL2_CSC_COEF5_RESERVED_SHIFT (0x00000000U)
5114 #define CSL_DSS_VIDL2_CSC_COEF5_RESERVED_MAX (0x00000007U)
5115 
5116 #define CSL_DSS_VIDL2_CSC_COEF5_PREOFFSET1_MASK (0x0000FFF8U)
5117 #define CSL_DSS_VIDL2_CSC_COEF5_PREOFFSET1_SHIFT (0x00000003U)
5118 #define CSL_DSS_VIDL2_CSC_COEF5_PREOFFSET1_MAX (0x00001FFFU)
5119 
5120 #define CSL_DSS_VIDL2_CSC_COEF5_RESERVED1_MASK (0x00070000U)
5121 #define CSL_DSS_VIDL2_CSC_COEF5_RESERVED1_SHIFT (0x00000010U)
5122 #define CSL_DSS_VIDL2_CSC_COEF5_RESERVED1_MAX (0x00000007U)
5123 
5124 #define CSL_DSS_VIDL2_CSC_COEF5_PREOFFSET2_MASK (0xFFF80000U)
5125 #define CSL_DSS_VIDL2_CSC_COEF5_PREOFFSET2_SHIFT (0x00000013U)
5126 #define CSL_DSS_VIDL2_CSC_COEF5_PREOFFSET2_MAX (0x00001FFFU)
5127 
5128 /* CSC_COEF6 */
5129 
5130 #define CSL_DSS_VIDL2_CSC_COEF6_RESERVED_MASK (0x00000007U)
5131 #define CSL_DSS_VIDL2_CSC_COEF6_RESERVED_SHIFT (0x00000000U)
5132 #define CSL_DSS_VIDL2_CSC_COEF6_RESERVED_MAX (0x00000007U)
5133 
5134 #define CSL_DSS_VIDL2_CSC_COEF6_PREOFFSET3_MASK (0x0000FFF8U)
5135 #define CSL_DSS_VIDL2_CSC_COEF6_PREOFFSET3_SHIFT (0x00000003U)
5136 #define CSL_DSS_VIDL2_CSC_COEF6_PREOFFSET3_MAX (0x00001FFFU)
5137 
5138 #define CSL_DSS_VIDL2_CSC_COEF6_RESERVED1_MASK (0x00070000U)
5139 #define CSL_DSS_VIDL2_CSC_COEF6_RESERVED1_SHIFT (0x00000010U)
5140 #define CSL_DSS_VIDL2_CSC_COEF6_RESERVED1_MAX (0x00000007U)
5141 
5142 #define CSL_DSS_VIDL2_CSC_COEF6_POSTOFFSET1_MASK (0xFFF80000U)
5143 #define CSL_DSS_VIDL2_CSC_COEF6_POSTOFFSET1_SHIFT (0x00000013U)
5144 #define CSL_DSS_VIDL2_CSC_COEF6_POSTOFFSET1_MAX (0x00001FFFU)
5145 
5146 /* GLOBAL_ALPHA */
5147 
5148 #define CSL_DSS_VIDL2_GLOBAL_ALPHA_GLOBALALPHA_MASK (0x000000FFU)
5149 #define CSL_DSS_VIDL2_GLOBAL_ALPHA_GLOBALALPHA_SHIFT (0x00000000U)
5150 #define CSL_DSS_VIDL2_GLOBAL_ALPHA_GLOBALALPHA_MAX (0x000000FFU)
5151 
5152 #define CSL_DSS_VIDL2_GLOBAL_ALPHA_RESERVED_MASK (0xFFFFFF00U)
5153 #define CSL_DSS_VIDL2_GLOBAL_ALPHA_RESERVED_SHIFT (0x00000008U)
5154 #define CSL_DSS_VIDL2_GLOBAL_ALPHA_RESERVED_MAX (0x00FFFFFFU)
5155 
5156 /* MFLAG_THRESHOLD */
5157 
5158 #define CSL_DSS_VIDL2_MFLAG_THRESHOLD_LT_MFLAG_MASK (0x0000FFFFU)
5159 #define CSL_DSS_VIDL2_MFLAG_THRESHOLD_LT_MFLAG_SHIFT (0x00000000U)
5160 #define CSL_DSS_VIDL2_MFLAG_THRESHOLD_LT_MFLAG_MAX (0x0000FFFFU)
5161 
5162 #define CSL_DSS_VIDL2_MFLAG_THRESHOLD_HT_MFLAG_MASK (0xFFFF0000U)
5163 #define CSL_DSS_VIDL2_MFLAG_THRESHOLD_HT_MFLAG_SHIFT (0x00000010U)
5164 #define CSL_DSS_VIDL2_MFLAG_THRESHOLD_HT_MFLAG_MAX (0x0000FFFFU)
5165 
5166 /* PICTURE_SIZE */
5167 
5168 #define CSL_DSS_VIDL2_PICTURE_SIZE_MEMSIZEX_MASK (0x00003FFFU)
5169 #define CSL_DSS_VIDL2_PICTURE_SIZE_MEMSIZEX_SHIFT (0x00000000U)
5170 #define CSL_DSS_VIDL2_PICTURE_SIZE_MEMSIZEX_MAX (0x00003FFFU)
5171 
5172 #define CSL_DSS_VIDL2_PICTURE_SIZE_MEMSIZEY_MASK (0x3FFF0000U)
5173 #define CSL_DSS_VIDL2_PICTURE_SIZE_MEMSIZEY_SHIFT (0x00000010U)
5174 #define CSL_DSS_VIDL2_PICTURE_SIZE_MEMSIZEY_MAX (0x00003FFFU)
5175 
5176 /* PIXEL_INC */
5177 
5178 #define CSL_DSS_VIDL2_PIXEL_INC_PIXELINC_MASK (0x000000FFU)
5179 #define CSL_DSS_VIDL2_PIXEL_INC_PIXELINC_SHIFT (0x00000000U)
5180 #define CSL_DSS_VIDL2_PIXEL_INC_PIXELINC_MAX (0x000000FFU)
5181 
5182 #define CSL_DSS_VIDL2_PIXEL_INC_RESERVED_68_MASK (0xFFFFFF00U)
5183 #define CSL_DSS_VIDL2_PIXEL_INC_RESERVED_68_SHIFT (0x00000008U)
5184 #define CSL_DSS_VIDL2_PIXEL_INC_RESERVED_68_MAX (0x00FFFFFFU)
5185 
5186 /* PRELOAD */
5187 
5188 #define CSL_DSS_VIDL2_PRELOAD_PRELOAD_MASK (0x00000FFFU)
5189 #define CSL_DSS_VIDL2_PRELOAD_PRELOAD_SHIFT (0x00000000U)
5190 #define CSL_DSS_VIDL2_PRELOAD_PRELOAD_MAX (0x00000FFFU)
5191 
5192 #define CSL_DSS_VIDL2_PRELOAD_RESERVED_212_MASK (0xFFFFF000U)
5193 #define CSL_DSS_VIDL2_PRELOAD_RESERVED_212_SHIFT (0x0000000CU)
5194 #define CSL_DSS_VIDL2_PRELOAD_RESERVED_212_MAX (0x000FFFFFU)
5195 
5196 /* ROW_INC */
5197 
5198 #define CSL_DSS_VIDL2_ROW_INC_ROWINC_MASK (0xFFFFFFFFU)
5199 #define CSL_DSS_VIDL2_ROW_INC_ROWINC_SHIFT (0x00000000U)
5200 #define CSL_DSS_VIDL2_ROW_INC_ROWINC_MAX (0xFFFFFFFFU)
5201 
5202 /* BA_EXT_0 */
5203 
5204 #define CSL_DSS_VIDL2_BA_EXT_0_BA_EXT_MASK (0x0000FFFFU)
5205 #define CSL_DSS_VIDL2_BA_EXT_0_BA_EXT_SHIFT (0x00000000U)
5206 #define CSL_DSS_VIDL2_BA_EXT_0_BA_EXT_MAX (0x0000FFFFU)
5207 
5208 #define CSL_DSS_VIDL2_BA_EXT_0_RESERVED_MASK (0xFFFF0000U)
5209 #define CSL_DSS_VIDL2_BA_EXT_0_RESERVED_SHIFT (0x00000010U)
5210 #define CSL_DSS_VIDL2_BA_EXT_0_RESERVED_MAX (0x0000FFFFU)
5211 
5212 /* BA_EXT_1 */
5213 
5214 #define CSL_DSS_VIDL2_BA_EXT_1_BA_EXT_MASK (0x0000FFFFU)
5215 #define CSL_DSS_VIDL2_BA_EXT_1_BA_EXT_SHIFT (0x00000000U)
5216 #define CSL_DSS_VIDL2_BA_EXT_1_BA_EXT_MAX (0x0000FFFFU)
5217 
5218 #define CSL_DSS_VIDL2_BA_EXT_1_RESERVED_MASK (0xFFFF0000U)
5219 #define CSL_DSS_VIDL2_BA_EXT_1_RESERVED_SHIFT (0x00000010U)
5220 #define CSL_DSS_VIDL2_BA_EXT_1_RESERVED_MAX (0x0000FFFFU)
5221 
5222 /* BA_UV_EXT_0 */
5223 
5224 #define CSL_DSS_VIDL2_BA_UV_EXT_0_BA_UV_EXT_MASK (0x0000FFFFU)
5225 #define CSL_DSS_VIDL2_BA_UV_EXT_0_BA_UV_EXT_SHIFT (0x00000000U)
5226 #define CSL_DSS_VIDL2_BA_UV_EXT_0_BA_UV_EXT_MAX (0x0000FFFFU)
5227 
5228 #define CSL_DSS_VIDL2_BA_UV_EXT_0_RESERVED_MASK (0xFFFF0000U)
5229 #define CSL_DSS_VIDL2_BA_UV_EXT_0_RESERVED_SHIFT (0x00000010U)
5230 #define CSL_DSS_VIDL2_BA_UV_EXT_0_RESERVED_MAX (0x0000FFFFU)
5231 
5232 /* BA_UV_EXT_1 */
5233 
5234 #define CSL_DSS_VIDL2_BA_UV_EXT_1_BA_UV_EXT_MASK (0x0000FFFFU)
5235 #define CSL_DSS_VIDL2_BA_UV_EXT_1_BA_UV_EXT_SHIFT (0x00000000U)
5236 #define CSL_DSS_VIDL2_BA_UV_EXT_1_BA_UV_EXT_MAX (0x0000FFFFU)
5237 
5238 #define CSL_DSS_VIDL2_BA_UV_EXT_1_RESERVED_MASK (0xFFFF0000U)
5239 #define CSL_DSS_VIDL2_BA_UV_EXT_1_RESERVED_SHIFT (0x00000010U)
5240 #define CSL_DSS_VIDL2_BA_UV_EXT_1_RESERVED_MAX (0x0000FFFFU)
5241 
5242 /* CSC_COEF7 */
5243 
5244 #define CSL_DSS_VIDL2_CSC_COEF7_RESERVED_MASK (0x00000007U)
5245 #define CSL_DSS_VIDL2_CSC_COEF7_RESERVED_SHIFT (0x00000000U)
5246 #define CSL_DSS_VIDL2_CSC_COEF7_RESERVED_MAX (0x00000007U)
5247 
5248 #define CSL_DSS_VIDL2_CSC_COEF7_POSTOFFSET2_MASK (0x0000FFF8U)
5249 #define CSL_DSS_VIDL2_CSC_COEF7_POSTOFFSET2_SHIFT (0x00000003U)
5250 #define CSL_DSS_VIDL2_CSC_COEF7_POSTOFFSET2_MAX (0x00001FFFU)
5251 
5252 #define CSL_DSS_VIDL2_CSC_COEF7_RESERVED1_MASK (0x00070000U)
5253 #define CSL_DSS_VIDL2_CSC_COEF7_RESERVED1_SHIFT (0x00000010U)
5254 #define CSL_DSS_VIDL2_CSC_COEF7_RESERVED1_MAX (0x00000007U)
5255 
5256 #define CSL_DSS_VIDL2_CSC_COEF7_POSTOFFSET3_MASK (0xFFF80000U)
5257 #define CSL_DSS_VIDL2_CSC_COEF7_POSTOFFSET3_SHIFT (0x00000013U)
5258 #define CSL_DSS_VIDL2_CSC_COEF7_POSTOFFSET3_MAX (0x00001FFFU)
5259 
5260 /* ROW_INC_UV */
5261 
5262 #define CSL_DSS_VIDL2_ROW_INC_UV_ROWINC_MASK (0xFFFFFFFFU)
5263 #define CSL_DSS_VIDL2_ROW_INC_UV_ROWINC_SHIFT (0x00000000U)
5264 #define CSL_DSS_VIDL2_ROW_INC_UV_ROWINC_MAX (0xFFFFFFFFU)
5265 
5266 /* TILE */
5267 
5268 #define CSL_DSS_VIDL2_TILE_TILEINDEX_MASK (0x007FFFFFU)
5269 #define CSL_DSS_VIDL2_TILE_TILEINDEX_SHIFT (0x00000000U)
5270 #define CSL_DSS_VIDL2_TILE_TILEINDEX_MAX (0x007FFFFFU)
5271 
5272 /* TILE2 */
5273 
5274 #define CSL_DSS_VIDL2_TILE2_NUM_TILES_MASK (0x007FFFFFU)
5275 #define CSL_DSS_VIDL2_TILE2_NUM_TILES_SHIFT (0x00000000U)
5276 #define CSL_DSS_VIDL2_TILE2_NUM_TILES_MAX (0x007FFFFFU)
5277 
5278 #define CSL_DSS_VIDL2_TILE2_RESERVED_MASK (0xFF800000U)
5279 #define CSL_DSS_VIDL2_TILE2_RESERVED_SHIFT (0x00000017U)
5280 #define CSL_DSS_VIDL2_TILE2_RESERVED_MAX (0x000001FFU)
5281 
5282 /* FBDC_ATTRIBUTES */
5283 
5284 #define CSL_DSS_VIDL2_FBDC_ATTRIBUTES_ENABLE_MASK (0x00000001U)
5285 #define CSL_DSS_VIDL2_FBDC_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
5286 #define CSL_DSS_VIDL2_FBDC_ATTRIBUTES_ENABLE_MAX (0x00000001U)
5287 
5288 #define CSL_DSS_VIDL2_FBDC_ATTRIBUTES_FORMAT_MASK (0x000000FEU)
5289 #define CSL_DSS_VIDL2_FBDC_ATTRIBUTES_FORMAT_SHIFT (0x00000001U)
5290 #define CSL_DSS_VIDL2_FBDC_ATTRIBUTES_FORMAT_MAX (0x0000007FU)
5291 
5292 #define CSL_DSS_VIDL2_FBDC_ATTRIBUTES_FORMAT_VAL_U8U8U8U8 (0xCU)
5293 #define CSL_DSS_VIDL2_FBDC_ATTRIBUTES_FORMAT_VAL_A2R10B10G10 (0xEU)
5294 
5295 #define CSL_DSS_VIDL2_FBDC_ATTRIBUTES_TILETYPE_MASK (0x00000300U)
5296 #define CSL_DSS_VIDL2_FBDC_ATTRIBUTES_TILETYPE_SHIFT (0x00000008U)
5297 #define CSL_DSS_VIDL2_FBDC_ATTRIBUTES_TILETYPE_MAX (0x00000003U)
5298 
5299 #define CSL_DSS_VIDL2_FBDC_ATTRIBUTES_TILETYPE_VAL_TILE16BY4 (0x2U)
5300 #define CSL_DSS_VIDL2_FBDC_ATTRIBUTES_TILETYPE_VAL_TILE32BY2 (0x3U)
5301 
5302 /* FBDC_CLEAR_COLOR */
5303 
5304 #define CSL_DSS_VIDL2_FBDC_CLEAR_COLOR_CLEARCOLOR_MASK (0xFFFFFFFFU)
5305 #define CSL_DSS_VIDL2_FBDC_CLEAR_COLOR_CLEARCOLOR_SHIFT (0x00000000U)
5306 #define CSL_DSS_VIDL2_FBDC_CLEAR_COLOR_CLEARCOLOR_MAX (0xFFFFFFFFU)
5307 
5308 /* CLUT_0 */
5309 
5310 #define CSL_DSS_VIDL2_CLUT_0_VALUE_B_MASK (0x000003FFU)
5311 #define CSL_DSS_VIDL2_CLUT_0_VALUE_B_SHIFT (0x00000000U)
5312 #define CSL_DSS_VIDL2_CLUT_0_VALUE_B_MAX (0x000003FFU)
5313 
5314 #define CSL_DSS_VIDL2_CLUT_0_VALUE_G_MASK (0x000FFC00U)
5315 #define CSL_DSS_VIDL2_CLUT_0_VALUE_G_SHIFT (0x0000000AU)
5316 #define CSL_DSS_VIDL2_CLUT_0_VALUE_G_MAX (0x000003FFU)
5317 
5318 #define CSL_DSS_VIDL2_CLUT_0_VALUE_R_MASK (0x3FF00000U)
5319 #define CSL_DSS_VIDL2_CLUT_0_VALUE_R_SHIFT (0x00000014U)
5320 #define CSL_DSS_VIDL2_CLUT_0_VALUE_R_MAX (0x000003FFU)
5321 
5322 #define CSL_DSS_VIDL2_CLUT_0_INDEX_MASK (0x80000000U)
5323 #define CSL_DSS_VIDL2_CLUT_0_INDEX_SHIFT (0x0000001FU)
5324 #define CSL_DSS_VIDL2_CLUT_0_INDEX_MAX (0x00000001U)
5325 
5326 /* CLUT_1 */
5327 
5328 #define CSL_DSS_VIDL2_CLUT_1_VALUE_B_MASK (0x000003FFU)
5329 #define CSL_DSS_VIDL2_CLUT_1_VALUE_B_SHIFT (0x00000000U)
5330 #define CSL_DSS_VIDL2_CLUT_1_VALUE_B_MAX (0x000003FFU)
5331 
5332 #define CSL_DSS_VIDL2_CLUT_1_VALUE_G_MASK (0x000FFC00U)
5333 #define CSL_DSS_VIDL2_CLUT_1_VALUE_G_SHIFT (0x0000000AU)
5334 #define CSL_DSS_VIDL2_CLUT_1_VALUE_G_MAX (0x000003FFU)
5335 
5336 #define CSL_DSS_VIDL2_CLUT_1_VALUE_R_MASK (0x3FF00000U)
5337 #define CSL_DSS_VIDL2_CLUT_1_VALUE_R_SHIFT (0x00000014U)
5338 #define CSL_DSS_VIDL2_CLUT_1_VALUE_R_MAX (0x000003FFU)
5339 
5340 #define CSL_DSS_VIDL2_CLUT_1_INDEX_MASK (0x80000000U)
5341 #define CSL_DSS_VIDL2_CLUT_1_INDEX_SHIFT (0x0000001FU)
5342 #define CSL_DSS_VIDL2_CLUT_1_INDEX_MAX (0x00000001U)
5343 
5344 /* CLUT_2 */
5345 
5346 #define CSL_DSS_VIDL2_CLUT_2_VALUE_B_MASK (0x000003FFU)
5347 #define CSL_DSS_VIDL2_CLUT_2_VALUE_B_SHIFT (0x00000000U)
5348 #define CSL_DSS_VIDL2_CLUT_2_VALUE_B_MAX (0x000003FFU)
5349 
5350 #define CSL_DSS_VIDL2_CLUT_2_VALUE_G_MASK (0x000FFC00U)
5351 #define CSL_DSS_VIDL2_CLUT_2_VALUE_G_SHIFT (0x0000000AU)
5352 #define CSL_DSS_VIDL2_CLUT_2_VALUE_G_MAX (0x000003FFU)
5353 
5354 #define CSL_DSS_VIDL2_CLUT_2_VALUE_R_MASK (0x3FF00000U)
5355 #define CSL_DSS_VIDL2_CLUT_2_VALUE_R_SHIFT (0x00000014U)
5356 #define CSL_DSS_VIDL2_CLUT_2_VALUE_R_MAX (0x000003FFU)
5357 
5358 #define CSL_DSS_VIDL2_CLUT_2_INDEX_MASK (0x80000000U)
5359 #define CSL_DSS_VIDL2_CLUT_2_INDEX_SHIFT (0x0000001FU)
5360 #define CSL_DSS_VIDL2_CLUT_2_INDEX_MAX (0x00000001U)
5361 
5362 /* CLUT_3 */
5363 
5364 #define CSL_DSS_VIDL2_CLUT_3_VALUE_B_MASK (0x000003FFU)
5365 #define CSL_DSS_VIDL2_CLUT_3_VALUE_B_SHIFT (0x00000000U)
5366 #define CSL_DSS_VIDL2_CLUT_3_VALUE_B_MAX (0x000003FFU)
5367 
5368 #define CSL_DSS_VIDL2_CLUT_3_VALUE_G_MASK (0x000FFC00U)
5369 #define CSL_DSS_VIDL2_CLUT_3_VALUE_G_SHIFT (0x0000000AU)
5370 #define CSL_DSS_VIDL2_CLUT_3_VALUE_G_MAX (0x000003FFU)
5371 
5372 #define CSL_DSS_VIDL2_CLUT_3_VALUE_R_MASK (0x3FF00000U)
5373 #define CSL_DSS_VIDL2_CLUT_3_VALUE_R_SHIFT (0x00000014U)
5374 #define CSL_DSS_VIDL2_CLUT_3_VALUE_R_MAX (0x000003FFU)
5375 
5376 #define CSL_DSS_VIDL2_CLUT_3_INDEX_MASK (0x80000000U)
5377 #define CSL_DSS_VIDL2_CLUT_3_INDEX_SHIFT (0x0000001FU)
5378 #define CSL_DSS_VIDL2_CLUT_3_INDEX_MAX (0x00000001U)
5379 
5380 /* CLUT_4 */
5381 
5382 #define CSL_DSS_VIDL2_CLUT_4_VALUE_B_MASK (0x000003FFU)
5383 #define CSL_DSS_VIDL2_CLUT_4_VALUE_B_SHIFT (0x00000000U)
5384 #define CSL_DSS_VIDL2_CLUT_4_VALUE_B_MAX (0x000003FFU)
5385 
5386 #define CSL_DSS_VIDL2_CLUT_4_VALUE_G_MASK (0x000FFC00U)
5387 #define CSL_DSS_VIDL2_CLUT_4_VALUE_G_SHIFT (0x0000000AU)
5388 #define CSL_DSS_VIDL2_CLUT_4_VALUE_G_MAX (0x000003FFU)
5389 
5390 #define CSL_DSS_VIDL2_CLUT_4_VALUE_R_MASK (0x3FF00000U)
5391 #define CSL_DSS_VIDL2_CLUT_4_VALUE_R_SHIFT (0x00000014U)
5392 #define CSL_DSS_VIDL2_CLUT_4_VALUE_R_MAX (0x000003FFU)
5393 
5394 #define CSL_DSS_VIDL2_CLUT_4_INDEX_MASK (0x80000000U)
5395 #define CSL_DSS_VIDL2_CLUT_4_INDEX_SHIFT (0x0000001FU)
5396 #define CSL_DSS_VIDL2_CLUT_4_INDEX_MAX (0x00000001U)
5397 
5398 /* CLUT_5 */
5399 
5400 #define CSL_DSS_VIDL2_CLUT_5_VALUE_B_MASK (0x000003FFU)
5401 #define CSL_DSS_VIDL2_CLUT_5_VALUE_B_SHIFT (0x00000000U)
5402 #define CSL_DSS_VIDL2_CLUT_5_VALUE_B_MAX (0x000003FFU)
5403 
5404 #define CSL_DSS_VIDL2_CLUT_5_VALUE_G_MASK (0x000FFC00U)
5405 #define CSL_DSS_VIDL2_CLUT_5_VALUE_G_SHIFT (0x0000000AU)
5406 #define CSL_DSS_VIDL2_CLUT_5_VALUE_G_MAX (0x000003FFU)
5407 
5408 #define CSL_DSS_VIDL2_CLUT_5_VALUE_R_MASK (0x3FF00000U)
5409 #define CSL_DSS_VIDL2_CLUT_5_VALUE_R_SHIFT (0x00000014U)
5410 #define CSL_DSS_VIDL2_CLUT_5_VALUE_R_MAX (0x000003FFU)
5411 
5412 #define CSL_DSS_VIDL2_CLUT_5_INDEX_MASK (0x80000000U)
5413 #define CSL_DSS_VIDL2_CLUT_5_INDEX_SHIFT (0x0000001FU)
5414 #define CSL_DSS_VIDL2_CLUT_5_INDEX_MAX (0x00000001U)
5415 
5416 /* CLUT_6 */
5417 
5418 #define CSL_DSS_VIDL2_CLUT_6_VALUE_B_MASK (0x000003FFU)
5419 #define CSL_DSS_VIDL2_CLUT_6_VALUE_B_SHIFT (0x00000000U)
5420 #define CSL_DSS_VIDL2_CLUT_6_VALUE_B_MAX (0x000003FFU)
5421 
5422 #define CSL_DSS_VIDL2_CLUT_6_VALUE_G_MASK (0x000FFC00U)
5423 #define CSL_DSS_VIDL2_CLUT_6_VALUE_G_SHIFT (0x0000000AU)
5424 #define CSL_DSS_VIDL2_CLUT_6_VALUE_G_MAX (0x000003FFU)
5425 
5426 #define CSL_DSS_VIDL2_CLUT_6_VALUE_R_MASK (0x3FF00000U)
5427 #define CSL_DSS_VIDL2_CLUT_6_VALUE_R_SHIFT (0x00000014U)
5428 #define CSL_DSS_VIDL2_CLUT_6_VALUE_R_MAX (0x000003FFU)
5429 
5430 #define CSL_DSS_VIDL2_CLUT_6_INDEX_MASK (0x80000000U)
5431 #define CSL_DSS_VIDL2_CLUT_6_INDEX_SHIFT (0x0000001FU)
5432 #define CSL_DSS_VIDL2_CLUT_6_INDEX_MAX (0x00000001U)
5433 
5434 /* CLUT_7 */
5435 
5436 #define CSL_DSS_VIDL2_CLUT_7_VALUE_B_MASK (0x000003FFU)
5437 #define CSL_DSS_VIDL2_CLUT_7_VALUE_B_SHIFT (0x00000000U)
5438 #define CSL_DSS_VIDL2_CLUT_7_VALUE_B_MAX (0x000003FFU)
5439 
5440 #define CSL_DSS_VIDL2_CLUT_7_VALUE_G_MASK (0x000FFC00U)
5441 #define CSL_DSS_VIDL2_CLUT_7_VALUE_G_SHIFT (0x0000000AU)
5442 #define CSL_DSS_VIDL2_CLUT_7_VALUE_G_MAX (0x000003FFU)
5443 
5444 #define CSL_DSS_VIDL2_CLUT_7_VALUE_R_MASK (0x3FF00000U)
5445 #define CSL_DSS_VIDL2_CLUT_7_VALUE_R_SHIFT (0x00000014U)
5446 #define CSL_DSS_VIDL2_CLUT_7_VALUE_R_MAX (0x000003FFU)
5447 
5448 #define CSL_DSS_VIDL2_CLUT_7_INDEX_MASK (0x80000000U)
5449 #define CSL_DSS_VIDL2_CLUT_7_INDEX_SHIFT (0x0000001FU)
5450 #define CSL_DSS_VIDL2_CLUT_7_INDEX_MAX (0x00000001U)
5451 
5452 /* CLUT_8 */
5453 
5454 #define CSL_DSS_VIDL2_CLUT_8_VALUE_B_MASK (0x000003FFU)
5455 #define CSL_DSS_VIDL2_CLUT_8_VALUE_B_SHIFT (0x00000000U)
5456 #define CSL_DSS_VIDL2_CLUT_8_VALUE_B_MAX (0x000003FFU)
5457 
5458 #define CSL_DSS_VIDL2_CLUT_8_VALUE_G_MASK (0x000FFC00U)
5459 #define CSL_DSS_VIDL2_CLUT_8_VALUE_G_SHIFT (0x0000000AU)
5460 #define CSL_DSS_VIDL2_CLUT_8_VALUE_G_MAX (0x000003FFU)
5461 
5462 #define CSL_DSS_VIDL2_CLUT_8_VALUE_R_MASK (0x3FF00000U)
5463 #define CSL_DSS_VIDL2_CLUT_8_VALUE_R_SHIFT (0x00000014U)
5464 #define CSL_DSS_VIDL2_CLUT_8_VALUE_R_MAX (0x000003FFU)
5465 
5466 #define CSL_DSS_VIDL2_CLUT_8_INDEX_MASK (0x80000000U)
5467 #define CSL_DSS_VIDL2_CLUT_8_INDEX_SHIFT (0x0000001FU)
5468 #define CSL_DSS_VIDL2_CLUT_8_INDEX_MAX (0x00000001U)
5469 
5470 /* CLUT_9 */
5471 
5472 #define CSL_DSS_VIDL2_CLUT_9_VALUE_B_MASK (0x000003FFU)
5473 #define CSL_DSS_VIDL2_CLUT_9_VALUE_B_SHIFT (0x00000000U)
5474 #define CSL_DSS_VIDL2_CLUT_9_VALUE_B_MAX (0x000003FFU)
5475 
5476 #define CSL_DSS_VIDL2_CLUT_9_VALUE_G_MASK (0x000FFC00U)
5477 #define CSL_DSS_VIDL2_CLUT_9_VALUE_G_SHIFT (0x0000000AU)
5478 #define CSL_DSS_VIDL2_CLUT_9_VALUE_G_MAX (0x000003FFU)
5479 
5480 #define CSL_DSS_VIDL2_CLUT_9_VALUE_R_MASK (0x3FF00000U)
5481 #define CSL_DSS_VIDL2_CLUT_9_VALUE_R_SHIFT (0x00000014U)
5482 #define CSL_DSS_VIDL2_CLUT_9_VALUE_R_MAX (0x000003FFU)
5483 
5484 #define CSL_DSS_VIDL2_CLUT_9_INDEX_MASK (0x80000000U)
5485 #define CSL_DSS_VIDL2_CLUT_9_INDEX_SHIFT (0x0000001FU)
5486 #define CSL_DSS_VIDL2_CLUT_9_INDEX_MAX (0x00000001U)
5487 
5488 /* CLUT_10 */
5489 
5490 #define CSL_DSS_VIDL2_CLUT_10_VALUE_B_MASK (0x000003FFU)
5491 #define CSL_DSS_VIDL2_CLUT_10_VALUE_B_SHIFT (0x00000000U)
5492 #define CSL_DSS_VIDL2_CLUT_10_VALUE_B_MAX (0x000003FFU)
5493 
5494 #define CSL_DSS_VIDL2_CLUT_10_VALUE_G_MASK (0x000FFC00U)
5495 #define CSL_DSS_VIDL2_CLUT_10_VALUE_G_SHIFT (0x0000000AU)
5496 #define CSL_DSS_VIDL2_CLUT_10_VALUE_G_MAX (0x000003FFU)
5497 
5498 #define CSL_DSS_VIDL2_CLUT_10_VALUE_R_MASK (0x3FF00000U)
5499 #define CSL_DSS_VIDL2_CLUT_10_VALUE_R_SHIFT (0x00000014U)
5500 #define CSL_DSS_VIDL2_CLUT_10_VALUE_R_MAX (0x000003FFU)
5501 
5502 #define CSL_DSS_VIDL2_CLUT_10_INDEX_MASK (0x80000000U)
5503 #define CSL_DSS_VIDL2_CLUT_10_INDEX_SHIFT (0x0000001FU)
5504 #define CSL_DSS_VIDL2_CLUT_10_INDEX_MAX (0x00000001U)
5505 
5506 /* CLUT_11 */
5507 
5508 #define CSL_DSS_VIDL2_CLUT_11_VALUE_B_MASK (0x000003FFU)
5509 #define CSL_DSS_VIDL2_CLUT_11_VALUE_B_SHIFT (0x00000000U)
5510 #define CSL_DSS_VIDL2_CLUT_11_VALUE_B_MAX (0x000003FFU)
5511 
5512 #define CSL_DSS_VIDL2_CLUT_11_VALUE_G_MASK (0x000FFC00U)
5513 #define CSL_DSS_VIDL2_CLUT_11_VALUE_G_SHIFT (0x0000000AU)
5514 #define CSL_DSS_VIDL2_CLUT_11_VALUE_G_MAX (0x000003FFU)
5515 
5516 #define CSL_DSS_VIDL2_CLUT_11_VALUE_R_MASK (0x3FF00000U)
5517 #define CSL_DSS_VIDL2_CLUT_11_VALUE_R_SHIFT (0x00000014U)
5518 #define CSL_DSS_VIDL2_CLUT_11_VALUE_R_MAX (0x000003FFU)
5519 
5520 #define CSL_DSS_VIDL2_CLUT_11_INDEX_MASK (0x80000000U)
5521 #define CSL_DSS_VIDL2_CLUT_11_INDEX_SHIFT (0x0000001FU)
5522 #define CSL_DSS_VIDL2_CLUT_11_INDEX_MAX (0x00000001U)
5523 
5524 /* CLUT_12 */
5525 
5526 #define CSL_DSS_VIDL2_CLUT_12_VALUE_B_MASK (0x000003FFU)
5527 #define CSL_DSS_VIDL2_CLUT_12_VALUE_B_SHIFT (0x00000000U)
5528 #define CSL_DSS_VIDL2_CLUT_12_VALUE_B_MAX (0x000003FFU)
5529 
5530 #define CSL_DSS_VIDL2_CLUT_12_VALUE_G_MASK (0x000FFC00U)
5531 #define CSL_DSS_VIDL2_CLUT_12_VALUE_G_SHIFT (0x0000000AU)
5532 #define CSL_DSS_VIDL2_CLUT_12_VALUE_G_MAX (0x000003FFU)
5533 
5534 #define CSL_DSS_VIDL2_CLUT_12_VALUE_R_MASK (0x3FF00000U)
5535 #define CSL_DSS_VIDL2_CLUT_12_VALUE_R_SHIFT (0x00000014U)
5536 #define CSL_DSS_VIDL2_CLUT_12_VALUE_R_MAX (0x000003FFU)
5537 
5538 #define CSL_DSS_VIDL2_CLUT_12_INDEX_MASK (0x80000000U)
5539 #define CSL_DSS_VIDL2_CLUT_12_INDEX_SHIFT (0x0000001FU)
5540 #define CSL_DSS_VIDL2_CLUT_12_INDEX_MAX (0x00000001U)
5541 
5542 /* CLUT_13 */
5543 
5544 #define CSL_DSS_VIDL2_CLUT_13_VALUE_B_MASK (0x000003FFU)
5545 #define CSL_DSS_VIDL2_CLUT_13_VALUE_B_SHIFT (0x00000000U)
5546 #define CSL_DSS_VIDL2_CLUT_13_VALUE_B_MAX (0x000003FFU)
5547 
5548 #define CSL_DSS_VIDL2_CLUT_13_VALUE_G_MASK (0x000FFC00U)
5549 #define CSL_DSS_VIDL2_CLUT_13_VALUE_G_SHIFT (0x0000000AU)
5550 #define CSL_DSS_VIDL2_CLUT_13_VALUE_G_MAX (0x000003FFU)
5551 
5552 #define CSL_DSS_VIDL2_CLUT_13_VALUE_R_MASK (0x3FF00000U)
5553 #define CSL_DSS_VIDL2_CLUT_13_VALUE_R_SHIFT (0x00000014U)
5554 #define CSL_DSS_VIDL2_CLUT_13_VALUE_R_MAX (0x000003FFU)
5555 
5556 #define CSL_DSS_VIDL2_CLUT_13_INDEX_MASK (0x80000000U)
5557 #define CSL_DSS_VIDL2_CLUT_13_INDEX_SHIFT (0x0000001FU)
5558 #define CSL_DSS_VIDL2_CLUT_13_INDEX_MAX (0x00000001U)
5559 
5560 /* CLUT_14 */
5561 
5562 #define CSL_DSS_VIDL2_CLUT_14_VALUE_B_MASK (0x000003FFU)
5563 #define CSL_DSS_VIDL2_CLUT_14_VALUE_B_SHIFT (0x00000000U)
5564 #define CSL_DSS_VIDL2_CLUT_14_VALUE_B_MAX (0x000003FFU)
5565 
5566 #define CSL_DSS_VIDL2_CLUT_14_VALUE_G_MASK (0x000FFC00U)
5567 #define CSL_DSS_VIDL2_CLUT_14_VALUE_G_SHIFT (0x0000000AU)
5568 #define CSL_DSS_VIDL2_CLUT_14_VALUE_G_MAX (0x000003FFU)
5569 
5570 #define CSL_DSS_VIDL2_CLUT_14_VALUE_R_MASK (0x3FF00000U)
5571 #define CSL_DSS_VIDL2_CLUT_14_VALUE_R_SHIFT (0x00000014U)
5572 #define CSL_DSS_VIDL2_CLUT_14_VALUE_R_MAX (0x000003FFU)
5573 
5574 #define CSL_DSS_VIDL2_CLUT_14_INDEX_MASK (0x80000000U)
5575 #define CSL_DSS_VIDL2_CLUT_14_INDEX_SHIFT (0x0000001FU)
5576 #define CSL_DSS_VIDL2_CLUT_14_INDEX_MAX (0x00000001U)
5577 
5578 /* CLUT_15 */
5579 
5580 #define CSL_DSS_VIDL2_CLUT_15_VALUE_B_MASK (0x000003FFU)
5581 #define CSL_DSS_VIDL2_CLUT_15_VALUE_B_SHIFT (0x00000000U)
5582 #define CSL_DSS_VIDL2_CLUT_15_VALUE_B_MAX (0x000003FFU)
5583 
5584 #define CSL_DSS_VIDL2_CLUT_15_VALUE_G_MASK (0x000FFC00U)
5585 #define CSL_DSS_VIDL2_CLUT_15_VALUE_G_SHIFT (0x0000000AU)
5586 #define CSL_DSS_VIDL2_CLUT_15_VALUE_G_MAX (0x000003FFU)
5587 
5588 #define CSL_DSS_VIDL2_CLUT_15_VALUE_R_MASK (0x3FF00000U)
5589 #define CSL_DSS_VIDL2_CLUT_15_VALUE_R_SHIFT (0x00000014U)
5590 #define CSL_DSS_VIDL2_CLUT_15_VALUE_R_MAX (0x000003FFU)
5591 
5592 #define CSL_DSS_VIDL2_CLUT_15_INDEX_MASK (0x80000000U)
5593 #define CSL_DSS_VIDL2_CLUT_15_INDEX_SHIFT (0x0000001FU)
5594 #define CSL_DSS_VIDL2_CLUT_15_INDEX_MAX (0x00000001U)
5595 
5596 /* SAFETY_ATTRIBUTES */
5597 
5598 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_ENABLE_MASK (0x00000001U)
5599 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
5600 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_ENABLE_MAX (0x00000001U)
5601 
5602 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_CAPTUREMODE_MASK (0x00000002U)
5603 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_CAPTUREMODE_SHIFT (0x00000001U)
5604 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_CAPTUREMODE_MAX (0x00000001U)
5605 
5606 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_DATACHECK (0x1U)
5607 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_FRAMEFREEZE (0x0U)
5608 
5609 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_SEEDSELECT_MASK (0x00000004U)
5610 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_SEEDSELECT_SHIFT (0x00000002U)
5611 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_SEEDSELECT_MAX (0x00000001U)
5612 
5613 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_ENABLE (0x1U)
5614 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_DISABLE (0x0U)
5615 
5616 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_THRESHOLD_MASK (0x000007F8U)
5617 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_THRESHOLD_SHIFT (0x00000003U)
5618 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_THRESHOLD_MAX (0x000000FFU)
5619 
5620 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_FRAMESKIP_MASK (0x00001800U)
5621 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_FRAMESKIP_SHIFT (0x0000000BU)
5622 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_FRAMESKIP_MAX (0x00000003U)
5623 
5624 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_DISABLE (0x0U)
5625 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_EVEN (0x1U)
5626 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_ODD (0x2U)
5627 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_RESERVED (0x3U)
5628 
5629 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_RESERVED_MASK (0xFFFFE000U)
5630 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_RESERVED_SHIFT (0x0000000DU)
5631 #define CSL_DSS_VIDL2_SAFETY_ATTRIBUTES_RESERVED_MAX (0x0007FFFFU)
5632 
5633 /* SAFETY_CAPT_SIGNATURE */
5634 
5635 #define CSL_DSS_VIDL2_SAFETY_CAPT_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
5636 #define CSL_DSS_VIDL2_SAFETY_CAPT_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
5637 #define CSL_DSS_VIDL2_SAFETY_CAPT_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
5638 
5639 /* SAFETY_POSITION */
5640 
5641 #define CSL_DSS_VIDL2_SAFETY_POSITION_POSX_MASK (0x00003FFFU)
5642 #define CSL_DSS_VIDL2_SAFETY_POSITION_POSX_SHIFT (0x00000000U)
5643 #define CSL_DSS_VIDL2_SAFETY_POSITION_POSX_MAX (0x00003FFFU)
5644 
5645 #define CSL_DSS_VIDL2_SAFETY_POSITION_POSY_MASK (0x3FFF0000U)
5646 #define CSL_DSS_VIDL2_SAFETY_POSITION_POSY_SHIFT (0x00000010U)
5647 #define CSL_DSS_VIDL2_SAFETY_POSITION_POSY_MAX (0x00003FFFU)
5648 
5649 /* SAFETY_REF_SIGNATURE */
5650 
5651 #define CSL_DSS_VIDL2_SAFETY_REF_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
5652 #define CSL_DSS_VIDL2_SAFETY_REF_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
5653 #define CSL_DSS_VIDL2_SAFETY_REF_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
5654 
5655 /* SAFETY_SIZE */
5656 
5657 #define CSL_DSS_VIDL2_SAFETY_SIZE_SIZEX_MASK (0x00003FFFU)
5658 #define CSL_DSS_VIDL2_SAFETY_SIZE_SIZEX_SHIFT (0x00000000U)
5659 #define CSL_DSS_VIDL2_SAFETY_SIZE_SIZEX_MAX (0x00003FFFU)
5660 
5661 #define CSL_DSS_VIDL2_SAFETY_SIZE_SIZEY_MASK (0x3FFF0000U)
5662 #define CSL_DSS_VIDL2_SAFETY_SIZE_SIZEY_SHIFT (0x00000010U)
5663 #define CSL_DSS_VIDL2_SAFETY_SIZE_SIZEY_MAX (0x00003FFFU)
5664 
5665 /* SAFETY_LFSR_SEED */
5666 
5667 #define CSL_DSS_VIDL2_SAFETY_LFSR_SEED_SEED_MASK (0xFFFFFFFFU)
5668 #define CSL_DSS_VIDL2_SAFETY_LFSR_SEED_SEED_SHIFT (0x00000000U)
5669 #define CSL_DSS_VIDL2_SAFETY_LFSR_SEED_SEED_MAX (0xFFFFFFFFU)
5670 
5671 /* LUMAKEY */
5672 
5673 #define CSL_DSS_VIDL2_LUMAKEY_LUMAKEYMIN_MASK (0x00000FFFU)
5674 #define CSL_DSS_VIDL2_LUMAKEY_LUMAKEYMIN_SHIFT (0x00000000U)
5675 #define CSL_DSS_VIDL2_LUMAKEY_LUMAKEYMIN_MAX (0x00000FFFU)
5676 
5677 #define CSL_DSS_VIDL2_LUMAKEY_RESERVED_MASK (0x0000F000U)
5678 #define CSL_DSS_VIDL2_LUMAKEY_RESERVED_SHIFT (0x0000000CU)
5679 #define CSL_DSS_VIDL2_LUMAKEY_RESERVED_MAX (0x0000000FU)
5680 
5681 #define CSL_DSS_VIDL2_LUMAKEY_LUMAKEYMAX_MASK (0x0FFF0000U)
5682 #define CSL_DSS_VIDL2_LUMAKEY_LUMAKEYMAX_SHIFT (0x00000010U)
5683 #define CSL_DSS_VIDL2_LUMAKEY_LUMAKEYMAX_MAX (0x00000FFFU)
5684 
5685 #define CSL_DSS_VIDL2_LUMAKEY_RESERVED1_MASK (0xF0000000U)
5686 #define CSL_DSS_VIDL2_LUMAKEY_RESERVED1_SHIFT (0x0000001CU)
5687 #define CSL_DSS_VIDL2_LUMAKEY_RESERVED1_MAX (0x0000000FU)
5688 
5689 /* DMA_BUFSIZE */
5690 
5691 #define CSL_DSS_VIDL2_DMA_BUFSIZE_BUFSIZE_MASK (0x0000001FU)
5692 #define CSL_DSS_VIDL2_DMA_BUFSIZE_BUFSIZE_SHIFT (0x00000000U)
5693 #define CSL_DSS_VIDL2_DMA_BUFSIZE_BUFSIZE_MAX (0x0000001FU)
5694 
5695 #define CSL_DSS_VIDL2_DMA_BUFSIZE_RESERVED_MASK (0xFFFFFFE0U)
5696 #define CSL_DSS_VIDL2_DMA_BUFSIZE_RESERVED_SHIFT (0x00000005U)
5697 #define CSL_DSS_VIDL2_DMA_BUFSIZE_RESERVED_MAX (0x07FFFFFFU)
5698 
5699 /* CROP */
5700 
5701 #define CSL_DSS_VIDL2_CROP_CROPLEFT_MASK (0x0000001FU)
5702 #define CSL_DSS_VIDL2_CROP_CROPLEFT_SHIFT (0x00000000U)
5703 #define CSL_DSS_VIDL2_CROP_CROPLEFT_MAX (0x0000001FU)
5704 
5705 #define CSL_DSS_VIDL2_CROP_CROPRIGHT_MASK (0x00001F00U)
5706 #define CSL_DSS_VIDL2_CROP_CROPRIGHT_SHIFT (0x00000008U)
5707 #define CSL_DSS_VIDL2_CROP_CROPRIGHT_MAX (0x0000001FU)
5708 
5709 #define CSL_DSS_VIDL2_CROP_CROPTOP_MASK (0x001F0000U)
5710 #define CSL_DSS_VIDL2_CROP_CROPTOP_SHIFT (0x00000010U)
5711 #define CSL_DSS_VIDL2_CROP_CROPTOP_MAX (0x0000001FU)
5712 
5713 #define CSL_DSS_VIDL2_CROP_CROPBOTTOM_MASK (0x1F000000U)
5714 #define CSL_DSS_VIDL2_CROP_CROPBOTTOM_SHIFT (0x00000018U)
5715 #define CSL_DSS_VIDL2_CROP_CROPBOTTOM_MAX (0x0000001FU)
5716 
5717 /* SECURE */
5718 
5719 #define CSL_DSS_VIDL2_SECURE_SECURE_MASK (0x00000001U)
5720 #define CSL_DSS_VIDL2_SECURE_SECURE_SHIFT (0x00000000U)
5721 #define CSL_DSS_VIDL2_SECURE_SECURE_MAX (0x00000001U)
5722 
5723 #define CSL_DSS_VIDL2_SECURE_SECURE_VAL_SECUREDIS (0x0U)
5724 #define CSL_DSS_VIDL2_SECURE_SECURE_VAL_SECUREEN (0x1U)
5725 
5726 #define CSL_DSS_VIDL2_SECURE_RESERVED_MASK (0xFFFFFFFEU)
5727 #define CSL_DSS_VIDL2_SECURE_RESERVED_SHIFT (0x00000001U)
5728 #define CSL_DSS_VIDL2_SECURE_RESERVED_MAX (0x7FFFFFFFU)
5729 
5730 /* PIPE_GO */
5731 
5732 #define CSL_DSS_VIDL2_PIPE_GO_GOBIT_MASK (0x00000001U)
5733 #define CSL_DSS_VIDL2_PIPE_GO_GOBIT_SHIFT (0x00000000U)
5734 #define CSL_DSS_VIDL2_PIPE_GO_GOBIT_MAX (0x00000001U)
5735 
5736 #define CSL_DSS_VIDL2_PIPE_GO_GOBIT_VAL_HFUISR (0x0U)
5737 #define CSL_DSS_VIDL2_PIPE_GO_GOBIT_VAL_UFPSR (0x1U)
5738 
5739 #define CSL_DSS_VIDL2_PIPE_GO_RESERVED_MASK (0xFFFFFFFEU)
5740 #define CSL_DSS_VIDL2_PIPE_GO_RESERVED_SHIFT (0x00000001U)
5741 #define CSL_DSS_VIDL2_PIPE_GO_RESERVED_MAX (0x7FFFFFFFU)
5742 
5743 /**************************************************************************
5744 * Hardware Region : VID1 Registers
5745 **************************************************************************/
5746 
5747 
5748 /**************************************************************************
5749 * Register Overlay Structure
5750 **************************************************************************/
5751 
5752 typedef struct {
5753  volatile uint32_t ACCUH_0; /* ACCUH_0 */
5754  volatile uint32_t ACCUH_1; /* ACCUH_1 */
5755  volatile uint32_t ACCUH2_0; /* ACCUH2_0 */
5756  volatile uint32_t ACCUH2_1; /* ACCUH2_1 */
5757  volatile uint32_t ACCUV_0; /* ACCUV_0 */
5758  volatile uint32_t ACCUV_1; /* ACCUV_1 */
5759  volatile uint32_t ACCUV2_0; /* ACCUV2_0 */
5760  volatile uint32_t ACCUV2_1; /* ACCUV2_1 */
5761  volatile uint32_t ATTRIBUTES; /* ATTRIBUTES */
5762  volatile uint32_t ATTRIBUTES2; /* ATTRIBUTES2 */
5763  volatile uint32_t BA_0; /* BA_0 */
5764  volatile uint32_t BA_1; /* BA_1 */
5765  volatile uint32_t BA_UV_0; /* BA_UV_0 */
5766  volatile uint32_t BA_UV_1; /* BA_UV_1 */
5767  volatile uint32_t BUF_SIZE_STATUS; /* BUF_SIZE_STATUS */
5768  volatile uint32_t BUF_THRESHOLD; /* BUF_THRESHOLD */
5769  volatile uint32_t CSC_COEF0; /* CSC_COEF0 */
5770  volatile uint32_t CSC_COEF1; /* CSC_COEF1 */
5771  volatile uint32_t CSC_COEF2; /* CSC_COEF2 */
5772  volatile uint32_t CSC_COEF3; /* CSC_COEF3 */
5773  volatile uint32_t CSC_COEF4; /* CSC_COEF4 */
5774  volatile uint32_t CSC_COEF5; /* CSC_COEF5 */
5775  volatile uint32_t CSC_COEF6; /* CSC_COEF6 */
5776  volatile uint32_t FIRH; /* FIRH */
5777  volatile uint32_t FIRH2; /* FIRH2 */
5778  volatile uint32_t FIRV; /* FIRV */
5779  volatile uint32_t FIRV2; /* FIRV2 */
5780  volatile uint32_t FIR_COEF_H0[9U]; /* FIR_COEF_H0 0..8 */
5781  volatile uint32_t FIR_COEF_H0_C[9U]; /* FIR_COEF_H0_C 0..8 */
5782  volatile uint32_t FIR_COEF_H12[16U]; /* FIR_COEF_H12 0..15 */
5783  volatile uint32_t FIR_COEF_H12_C[16U]; /* FIR_COEF_H12_C 0..15 */
5784  volatile uint32_t FIR_COEF_V0[9U]; /* FIR_COEF_V0 0..8 */
5785  volatile uint32_t FIR_COEF_V0_C[9U]; /* FIR_COEF_V0_C 0..8 */
5786  volatile uint32_t FIR_COEF_V12[16U]; /* FIR_COEF_V12 0..15 */
5787  volatile uint32_t FIR_COEF_V12_C[16U]; /* FIR_COEF_V12_C 0..15 */
5788  volatile uint32_t GLOBAL_ALPHA; /* GLOBAL_ALPHA */
5789  volatile uint8_t Resv_520[8];
5790  volatile uint32_t MFLAG_THRESHOLD; /* MFLAG_THRESHOLD */
5791  volatile uint32_t PICTURE_SIZE; /* PICTURE_SIZE */
5792  volatile uint32_t PIXEL_INC; /* PIXEL_INC */
5793  volatile uint8_t Resv_536[4];
5794  volatile uint32_t PRELOAD; /* PRELOAD */
5795  volatile uint32_t ROW_INC; /* ROW_INC */
5796  volatile uint32_t SIZE; /* SIZE */
5797  volatile uint8_t Resv_556[8];
5798  volatile uint32_t BA_EXT_0; /* BA_EXT_0 */
5799  volatile uint32_t BA_EXT_1; /* BA_EXT_1 */
5800  volatile uint32_t BA_UV_EXT_0; /* BA_UV_EXT_0 */
5801  volatile uint32_t BA_UV_EXT_1; /* BA_UV_EXT_1 */
5802  volatile uint32_t CSC_COEF7; /* CSC_COEF7 */
5803  volatile uint8_t Resv_584[8];
5804  volatile uint32_t ROW_INC_UV; /* ROW_INC_UV */
5805  volatile uint32_t TILE; /* TILE */
5806  volatile uint32_t TILE2; /* TILE2 */
5807  volatile uint32_t FBDC_ATTRIBUTES; /* FBDC_ATTRIBUTES */
5808  volatile uint32_t FBDC_CLEAR_COLOR; /* FBDC_CLEAR_COLOR */
5809  volatile uint8_t Resv_608[4];
5810  volatile uint32_t CLUT_0; /* CLUT_0 */
5811  volatile uint32_t CLUT_1; /* CLUT_1 */
5812  volatile uint32_t CLUT_2; /* CLUT_2 */
5813  volatile uint32_t CLUT_3; /* CLUT_3 */
5814  volatile uint32_t CLUT_4; /* CLUT_4 */
5815  volatile uint32_t CLUT_5; /* CLUT_5 */
5816  volatile uint32_t CLUT_6; /* CLUT_6 */
5817  volatile uint32_t CLUT_7; /* CLUT_7 */
5818  volatile uint32_t CLUT_8; /* CLUT_8 */
5819  volatile uint32_t CLUT_9; /* CLUT_9 */
5820  volatile uint32_t CLUT_10; /* CLUT_10 */
5821  volatile uint32_t CLUT_11; /* CLUT_11 */
5822  volatile uint32_t CLUT_12; /* CLUT_12 */
5823  volatile uint32_t CLUT_13; /* CLUT_13 */
5824  volatile uint32_t CLUT_14; /* CLUT_14 */
5825  volatile uint32_t CLUT_15; /* CLUT_15 */
5826  volatile uint32_t SAFETY_ATTRIBUTES; /* SAFETY_ATTRIBUTES */
5827  volatile uint32_t SAFETY_CAPT_SIGNATURE; /* SAFETY_CAPT_SIGNATURE */
5828  volatile uint32_t SAFETY_POSITION; /* SAFETY_POSITION */
5829  volatile uint32_t SAFETY_REF_SIGNATURE; /* SAFETY_REF_SIGNATURE */
5830  volatile uint32_t SAFETY_SIZE; /* SAFETY_SIZE */
5831  volatile uint32_t SAFETY_LFSR_SEED; /* SAFETY_LFSR_SEED */
5832  volatile uint32_t LUMAKEY; /* LUMAKEY */
5833  volatile uint32_t DMA_BUFSIZE; /* DMA_BUFSIZE */
5834  volatile uint32_t CROP; /* CROP */
5835  volatile uint32_t SECURE; /* SECURE */
5836  volatile uint32_t PIPE_GO; /* PIPE_GO */
5838 
5839 
5840 /**************************************************************************
5841 * Register Macros
5842 **************************************************************************/
5843 
5844 #define CSL_DSS_VID1_ACCUH_0 (0x00000000U)
5845 #define CSL_DSS_VID1_ACCUH_1 (0x00000004U)
5846 #define CSL_DSS_VID1_ACCUH2_0 (0x00000008U)
5847 #define CSL_DSS_VID1_ACCUH2_1 (0x0000000CU)
5848 #define CSL_DSS_VID1_ACCUV_0 (0x00000010U)
5849 #define CSL_DSS_VID1_ACCUV_1 (0x00000014U)
5850 #define CSL_DSS_VID1_ACCUV2_0 (0x00000018U)
5851 #define CSL_DSS_VID1_ACCUV2_1 (0x0000001CU)
5852 #define CSL_DSS_VID1_ATTRIBUTES (0x00000020U)
5853 #define CSL_DSS_VID1_ATTRIBUTES2 (0x00000024U)
5854 #define CSL_DSS_VID1_BA_0 (0x00000028U)
5855 #define CSL_DSS_VID1_BA_1 (0x0000002CU)
5856 #define CSL_DSS_VID1_BA_UV_0 (0x00000030U)
5857 #define CSL_DSS_VID1_BA_UV_1 (0x00000034U)
5858 #define CSL_DSS_VID1_BUF_SIZE_STATUS (0x00000038U)
5859 #define CSL_DSS_VID1_BUF_THRESHOLD (0x0000003CU)
5860 #define CSL_DSS_VID1_CSC_COEF0 (0x00000040U)
5861 #define CSL_DSS_VID1_CSC_COEF1 (0x00000044U)
5862 #define CSL_DSS_VID1_CSC_COEF2 (0x00000048U)
5863 #define CSL_DSS_VID1_CSC_COEF3 (0x0000004CU)
5864 #define CSL_DSS_VID1_CSC_COEF4 (0x00000050U)
5865 #define CSL_DSS_VID1_CSC_COEF5 (0x00000054U)
5866 #define CSL_DSS_VID1_CSC_COEF6 (0x00000058U)
5867 #define CSL_DSS_VID1_FIRH (0x0000005CU)
5868 #define CSL_DSS_VID1_FIRH2 (0x00000060U)
5869 #define CSL_DSS_VID1_FIRV (0x00000064U)
5870 #define CSL_DSS_VID1_FIRV2 (0x00000068U)
5871 #define CSL_DSS_VID1_FIR_COEF_H0(index) (0x0000006CU+((uint32_t)(index)*0x4U))
5872 #define CSL_DSS_VID1_FIR_COEF_H0_C(index) (0x00000090U+((uint32_t)(index)*0x4U))
5873 #define CSL_DSS_VID1_FIR_COEF_H12(index) (0x000000B4U+((uint32_t)(index)*0x4U))
5874 #define CSL_DSS_VID1_FIR_COEF_H12_C(index) (0x000000F4U+((uint32_t)(index)*0x4U))
5875 #define CSL_DSS_VID1_FIR_COEF_V0(index) (0x00000134U+((uint32_t)(index)*0x4U))
5876 #define CSL_DSS_VID1_FIR_COEF_V0_C(index) (0x00000158U+((uint32_t)(index)*0x4U))
5877 #define CSL_DSS_VID1_FIR_COEF_V12(index) (0x0000017CU+((uint32_t)(index)*0x4U))
5878 #define CSL_DSS_VID1_FIR_COEF_V12_C(index) (0x000001BCU+((uint32_t)(index)*0x4U))
5879 #define CSL_DSS_VID1_GLOBAL_ALPHA (0x000001FCU)
5880 #define CSL_DSS_VID1_MFLAG_THRESHOLD (0x00000208U)
5881 #define CSL_DSS_VID1_PICTURE_SIZE (0x0000020CU)
5882 #define CSL_DSS_VID1_PIXEL_INC (0x00000210U)
5883 #define CSL_DSS_VID1_PRELOAD (0x00000218U)
5884 #define CSL_DSS_VID1_ROW_INC (0x0000021CU)
5885 #define CSL_DSS_VID1_SIZE (0x00000220U)
5886 #define CSL_DSS_VID1_BA_EXT_0 (0x0000022CU)
5887 #define CSL_DSS_VID1_BA_EXT_1 (0x00000230U)
5888 #define CSL_DSS_VID1_BA_UV_EXT_0 (0x00000234U)
5889 #define CSL_DSS_VID1_BA_UV_EXT_1 (0x00000238U)
5890 #define CSL_DSS_VID1_CSC_COEF7 (0x0000023CU)
5891 #define CSL_DSS_VID1_ROW_INC_UV (0x00000248U)
5892 #define CSL_DSS_VID1_TILE (0x0000024CU)
5893 #define CSL_DSS_VID1_TILE2 (0x00000250U)
5894 #define CSL_DSS_VID1_FBDC_ATTRIBUTES (0x00000254U)
5895 #define CSL_DSS_VID1_FBDC_CLEAR_COLOR (0x00000258U)
5896 #define CSL_DSS_VID1_CLUT_0 (0x00000260U)
5897 #define CSL_DSS_VID1_CLUT_1 (0x00000264U)
5898 #define CSL_DSS_VID1_CLUT_2 (0x00000268U)
5899 #define CSL_DSS_VID1_CLUT_3 (0x0000026CU)
5900 #define CSL_DSS_VID1_CLUT_4 (0x00000270U)
5901 #define CSL_DSS_VID1_CLUT_5 (0x00000274U)
5902 #define CSL_DSS_VID1_CLUT_6 (0x00000278U)
5903 #define CSL_DSS_VID1_CLUT_7 (0x0000027CU)
5904 #define CSL_DSS_VID1_CLUT_8 (0x00000280U)
5905 #define CSL_DSS_VID1_CLUT_9 (0x00000284U)
5906 #define CSL_DSS_VID1_CLUT_10 (0x00000288U)
5907 #define CSL_DSS_VID1_CLUT_11 (0x0000028CU)
5908 #define CSL_DSS_VID1_CLUT_12 (0x00000290U)
5909 #define CSL_DSS_VID1_CLUT_13 (0x00000294U)
5910 #define CSL_DSS_VID1_CLUT_14 (0x00000298U)
5911 #define CSL_DSS_VID1_CLUT_15 (0x0000029CU)
5912 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES (0x000002A0U)
5913 #define CSL_DSS_VID1_SAFETY_CAPT_SIGNATURE (0x000002A4U)
5914 #define CSL_DSS_VID1_SAFETY_POSITION (0x000002A8U)
5915 #define CSL_DSS_VID1_SAFETY_REF_SIGNATURE (0x000002ACU)
5916 #define CSL_DSS_VID1_SAFETY_SIZE (0x000002B0U)
5917 #define CSL_DSS_VID1_SAFETY_LFSR_SEED (0x000002B4U)
5918 #define CSL_DSS_VID1_LUMAKEY (0x000002B8U)
5919 #define CSL_DSS_VID1_DMA_BUFSIZE (0x000002BCU)
5920 #define CSL_DSS_VID1_CROP (0x000002C0U)
5921 #define CSL_DSS_VID1_SECURE (0x000002C4U)
5922 #define CSL_DSS_VID1_PIPE_GO (0x000002C8U)
5923 
5924 /**************************************************************************
5925 * Field Definition Macros
5926 **************************************************************************/
5927 
5928 
5929 /* ACCUH_0 */
5930 
5931 #define CSL_DSS_VID1_ACCUH_0_HORIZONTALACCU_MASK (0x00FFFFFFU)
5932 #define CSL_DSS_VID1_ACCUH_0_HORIZONTALACCU_SHIFT (0x00000000U)
5933 #define CSL_DSS_VID1_ACCUH_0_HORIZONTALACCU_MAX (0x00FFFFFFU)
5934 
5935 #define CSL_DSS_VID1_ACCUH_0_RESERVED_MASK (0xFF000000U)
5936 #define CSL_DSS_VID1_ACCUH_0_RESERVED_SHIFT (0x00000018U)
5937 #define CSL_DSS_VID1_ACCUH_0_RESERVED_MAX (0x000000FFU)
5938 
5939 /* ACCUH_1 */
5940 
5941 #define CSL_DSS_VID1_ACCUH_1_HORIZONTALACCU_MASK (0x00FFFFFFU)
5942 #define CSL_DSS_VID1_ACCUH_1_HORIZONTALACCU_SHIFT (0x00000000U)
5943 #define CSL_DSS_VID1_ACCUH_1_HORIZONTALACCU_MAX (0x00FFFFFFU)
5944 
5945 #define CSL_DSS_VID1_ACCUH_1_RESERVED_MASK (0xFF000000U)
5946 #define CSL_DSS_VID1_ACCUH_1_RESERVED_SHIFT (0x00000018U)
5947 #define CSL_DSS_VID1_ACCUH_1_RESERVED_MAX (0x000000FFU)
5948 
5949 /* ACCUH2_0 */
5950 
5951 #define CSL_DSS_VID1_ACCUH2_0_HORIZONTALACCU_MASK (0x00FFFFFFU)
5952 #define CSL_DSS_VID1_ACCUH2_0_HORIZONTALACCU_SHIFT (0x00000000U)
5953 #define CSL_DSS_VID1_ACCUH2_0_HORIZONTALACCU_MAX (0x00FFFFFFU)
5954 
5955 #define CSL_DSS_VID1_ACCUH2_0_RESERVED_MASK (0xFF000000U)
5956 #define CSL_DSS_VID1_ACCUH2_0_RESERVED_SHIFT (0x00000018U)
5957 #define CSL_DSS_VID1_ACCUH2_0_RESERVED_MAX (0x000000FFU)
5958 
5959 /* ACCUH2_1 */
5960 
5961 #define CSL_DSS_VID1_ACCUH2_1_HORIZONTALACCU_MASK (0x00FFFFFFU)
5962 #define CSL_DSS_VID1_ACCUH2_1_HORIZONTALACCU_SHIFT (0x00000000U)
5963 #define CSL_DSS_VID1_ACCUH2_1_HORIZONTALACCU_MAX (0x00FFFFFFU)
5964 
5965 #define CSL_DSS_VID1_ACCUH2_1_RESERVED_MASK (0xFF000000U)
5966 #define CSL_DSS_VID1_ACCUH2_1_RESERVED_SHIFT (0x00000018U)
5967 #define CSL_DSS_VID1_ACCUH2_1_RESERVED_MAX (0x000000FFU)
5968 
5969 /* ACCUV_0 */
5970 
5971 #define CSL_DSS_VID1_ACCUV_0_VERTICALACCU_MASK (0x00FFFFFFU)
5972 #define CSL_DSS_VID1_ACCUV_0_VERTICALACCU_SHIFT (0x00000000U)
5973 #define CSL_DSS_VID1_ACCUV_0_VERTICALACCU_MAX (0x00FFFFFFU)
5974 
5975 #define CSL_DSS_VID1_ACCUV_0_RESERVED_MASK (0xFF000000U)
5976 #define CSL_DSS_VID1_ACCUV_0_RESERVED_SHIFT (0x00000018U)
5977 #define CSL_DSS_VID1_ACCUV_0_RESERVED_MAX (0x000000FFU)
5978 
5979 /* ACCUV_1 */
5980 
5981 #define CSL_DSS_VID1_ACCUV_1_VERTICALACCU_MASK (0x00FFFFFFU)
5982 #define CSL_DSS_VID1_ACCUV_1_VERTICALACCU_SHIFT (0x00000000U)
5983 #define CSL_DSS_VID1_ACCUV_1_VERTICALACCU_MAX (0x00FFFFFFU)
5984 
5985 #define CSL_DSS_VID1_ACCUV_1_RESERVED_MASK (0xFF000000U)
5986 #define CSL_DSS_VID1_ACCUV_1_RESERVED_SHIFT (0x00000018U)
5987 #define CSL_DSS_VID1_ACCUV_1_RESERVED_MAX (0x000000FFU)
5988 
5989 /* ACCUV2_0 */
5990 
5991 #define CSL_DSS_VID1_ACCUV2_0_VERTICALACCU_MASK (0x00FFFFFFU)
5992 #define CSL_DSS_VID1_ACCUV2_0_VERTICALACCU_SHIFT (0x00000000U)
5993 #define CSL_DSS_VID1_ACCUV2_0_VERTICALACCU_MAX (0x00FFFFFFU)
5994 
5995 #define CSL_DSS_VID1_ACCUV2_0_RESERVED_MASK (0xFF000000U)
5996 #define CSL_DSS_VID1_ACCUV2_0_RESERVED_SHIFT (0x00000018U)
5997 #define CSL_DSS_VID1_ACCUV2_0_RESERVED_MAX (0x000000FFU)
5998 
5999 /* ACCUV2_1 */
6000 
6001 #define CSL_DSS_VID1_ACCUV2_1_VERTICALACCU_MASK (0x00FFFFFFU)
6002 #define CSL_DSS_VID1_ACCUV2_1_VERTICALACCU_SHIFT (0x00000000U)
6003 #define CSL_DSS_VID1_ACCUV2_1_VERTICALACCU_MAX (0x00FFFFFFU)
6004 
6005 #define CSL_DSS_VID1_ACCUV2_1_RESERVED_MASK (0xFF000000U)
6006 #define CSL_DSS_VID1_ACCUV2_1_RESERVED_SHIFT (0x00000018U)
6007 #define CSL_DSS_VID1_ACCUV2_1_RESERVED_MAX (0x000000FFU)
6008 
6009 /* ATTRIBUTES */
6010 
6011 #define CSL_DSS_VID1_ATTRIBUTES_ENABLE_MASK (0x00000001U)
6012 #define CSL_DSS_VID1_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
6013 #define CSL_DSS_VID1_ATTRIBUTES_ENABLE_MAX (0x00000001U)
6014 
6015 #define CSL_DSS_VID1_ATTRIBUTES_ENABLE_VAL_VIDEOENB (0x1U)
6016 #define CSL_DSS_VID1_ATTRIBUTES_ENABLE_VAL_VIDEODIS (0x0U)
6017 
6018 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_MASK (0x0000007EU)
6019 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_SHIFT (0x00000001U)
6020 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_MAX (0x0000003FU)
6021 
6022 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_ARGB16_4444 (0x0U)
6023 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_ABGR16_4444 (0x1U)
6024 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_RGBA16_4444 (0x2U)
6025 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_RGB16_565 (0x3U)
6026 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_BGR16_565 (0x4U)
6027 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_ARGB16_1555 (0x5U)
6028 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_ABGR16_1555 (0x6U)
6029 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_ARGB32_8888 (0x7U)
6030 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_ABGR32_8888 (0x8U)
6031 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_RGBA32_8888 (0x9U)
6032 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_BGRA32_8888 (0xAU)
6033 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_RGB24P_888 (0xBU)
6034 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_BGR24P_888 (0xCU)
6035 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_ARGB32_2101010 (0xEU)
6036 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_ABGR32_2101010 (0xFU)
6037 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_ARGB64_16161616 (0x10U)
6038 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_RGBA64_16161616 (0x11U)
6039 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_BITMAP1 (0x12U)
6040 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_BITMAP2 (0x13U)
6041 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_BITMAP4 (0x14U)
6042 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_BITMAP8 (0x15U)
6043 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_RGB565A8 (0x16U)
6044 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_BGR565A8 (0x17U)
6045 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_XRGB16_4444 (0x20U)
6046 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_XBGR16_4444 (0x21U)
6047 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_RGBX16_4444 (0x22U)
6048 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_XRGB16_1555 (0x25U)
6049 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_XBGR16_1555 (0x26U)
6050 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_XRGB32_8888 (0x27U)
6051 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_XBGR32_8888 (0x28U)
6052 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_RGBX32_8888 (0x29U)
6053 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_BGRX32_8888 (0x2AU)
6054 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_XRGB32_2101010 (0x2EU)
6055 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_XBGR32_2101010 (0x2FU)
6056 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_XRGB64_16161616 (0x30U)
6057 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_RGBX64_16161616 (0x31U)
6058 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_YUV422_NV12 (0x3CU)
6059 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_YUV420_NV12 (0x3DU)
6060 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_YUV422_YUV2 (0x3EU)
6061 #define CSL_DSS_VID1_ATTRIBUTES_FORMAT_VAL_YUV422_UYVY (0x3FU)
6062 
6063 #define CSL_DSS_VID1_ATTRIBUTES_RESIZEENABLE_MASK (0x00000180U)
6064 #define CSL_DSS_VID1_ATTRIBUTES_RESIZEENABLE_SHIFT (0x00000007U)
6065 #define CSL_DSS_VID1_ATTRIBUTES_RESIZEENABLE_MAX (0x00000003U)
6066 
6067 #define CSL_DSS_VID1_ATTRIBUTES_RESIZEENABLE_VAL_RESIZEPROC (0x0U)
6068 #define CSL_DSS_VID1_ATTRIBUTES_RESIZEENABLE_VAL_HRESIZE (0x1U)
6069 #define CSL_DSS_VID1_ATTRIBUTES_RESIZEENABLE_VAL_VRESIZE (0x2U)
6070 #define CSL_DSS_VID1_ATTRIBUTES_RESIZEENABLE_VAL_HVRESIZE (0x3U)
6071 
6072 #define CSL_DSS_VID1_ATTRIBUTES_COLORCONVENABLE_MASK (0x00000200U)
6073 #define CSL_DSS_VID1_ATTRIBUTES_COLORCONVENABLE_SHIFT (0x00000009U)
6074 #define CSL_DSS_VID1_ATTRIBUTES_COLORCONVENABLE_MAX (0x00000001U)
6075 
6076 #define CSL_DSS_VID1_ATTRIBUTES_COLORCONVENABLE_VAL_COLSPCENB (0x1U)
6077 #define CSL_DSS_VID1_ATTRIBUTES_COLORCONVENABLE_VAL_COLSPCDIS (0x0U)
6078 
6079 #define CSL_DSS_VID1_ATTRIBUTES_NIBBLEMODE_MASK (0x00000400U)
6080 #define CSL_DSS_VID1_ATTRIBUTES_NIBBLEMODE_SHIFT (0x0000000AU)
6081 #define CSL_DSS_VID1_ATTRIBUTES_NIBBLEMODE_MAX (0x00000001U)
6082 
6083 #define CSL_DSS_VID1_ATTRIBUTES_NIBBLEMODE_VAL_NIBBLEMODEEN (0x1U)
6084 #define CSL_DSS_VID1_ATTRIBUTES_NIBBLEMODE_VAL_NIBBLEMODEDIS (0x0U)
6085 
6086 #define CSL_DSS_VID1_ATTRIBUTES_FULLRANGE_MASK (0x00000800U)
6087 #define CSL_DSS_VID1_ATTRIBUTES_FULLRANGE_SHIFT (0x0000000BU)
6088 #define CSL_DSS_VID1_ATTRIBUTES_FULLRANGE_MAX (0x00000001U)
6089 
6090 #define CSL_DSS_VID1_ATTRIBUTES_FULLRANGE_VAL_FULLRANGE (0x1U)
6091 #define CSL_DSS_VID1_ATTRIBUTES_FULLRANGE_VAL_LIMRANGE (0x0U)
6092 
6093 #define CSL_DSS_VID1_ATTRIBUTES_FLIP_MASK (0x00001000U)
6094 #define CSL_DSS_VID1_ATTRIBUTES_FLIP_SHIFT (0x0000000CU)
6095 #define CSL_DSS_VID1_ATTRIBUTES_FLIP_MAX (0x00000001U)
6096 
6097 #define CSL_DSS_VID1_ATTRIBUTES_FLIP_VAL_FLIP (0x1U)
6098 #define CSL_DSS_VID1_ATTRIBUTES_FLIP_VAL_NOFLIP (0x0U)
6099 
6100 #define CSL_DSS_VID1_ATTRIBUTES_CROP_MASK (0x00002000U)
6101 #define CSL_DSS_VID1_ATTRIBUTES_CROP_SHIFT (0x0000000DU)
6102 #define CSL_DSS_VID1_ATTRIBUTES_CROP_MAX (0x00000001U)
6103 
6104 #define CSL_DSS_VID1_ATTRIBUTES_CROP_VAL_CROPEN (0x1U)
6105 #define CSL_DSS_VID1_ATTRIBUTES_CROP_VAL_CROPDIS (0x0U)
6106 
6107 #define CSL_DSS_VID1_ATTRIBUTES_RESERVED9_MASK (0x0001C000U)
6108 #define CSL_DSS_VID1_ATTRIBUTES_RESERVED9_SHIFT (0x0000000EU)
6109 #define CSL_DSS_VID1_ATTRIBUTES_RESERVED9_MAX (0x00000007U)
6110 
6111 #define CSL_DSS_VID1_ATTRIBUTES_SELFREFRESHAUTO_MASK (0x00020000U)
6112 #define CSL_DSS_VID1_ATTRIBUTES_SELFREFRESHAUTO_SHIFT (0x00000011U)
6113 #define CSL_DSS_VID1_ATTRIBUTES_SELFREFRESHAUTO_MAX (0x00000001U)
6114 
6115 #define CSL_DSS_VID1_ATTRIBUTES_SELFREFRESHAUTO_VAL_SELFREFRESHAUTOEN (0x1U)
6116 #define CSL_DSS_VID1_ATTRIBUTES_SELFREFRESHAUTO_VAL_SELFREFRESHAUTODIS (0x0U)
6117 
6118 #define CSL_DSS_VID1_ATTRIBUTES_RESERVED7_MASK (0x00040000U)
6119 #define CSL_DSS_VID1_ATTRIBUTES_RESERVED7_SHIFT (0x00000012U)
6120 #define CSL_DSS_VID1_ATTRIBUTES_RESERVED7_MAX (0x00000001U)
6121 
6122 #define CSL_DSS_VID1_ATTRIBUTES_BUFPRELOAD_MASK (0x00080000U)
6123 #define CSL_DSS_VID1_ATTRIBUTES_BUFPRELOAD_SHIFT (0x00000013U)
6124 #define CSL_DSS_VID1_ATTRIBUTES_BUFPRELOAD_MAX (0x00000001U)
6125 
6126 #define CSL_DSS_VID1_ATTRIBUTES_BUFPRELOAD_VAL_HIGHTHRES (0x1U)
6127 #define CSL_DSS_VID1_ATTRIBUTES_BUFPRELOAD_VAL_DEFVAL (0x0U)
6128 
6129 #define CSL_DSS_VID1_ATTRIBUTES_RESERVED2_MASK (0x00100000U)
6130 #define CSL_DSS_VID1_ATTRIBUTES_RESERVED2_SHIFT (0x00000014U)
6131 #define CSL_DSS_VID1_ATTRIBUTES_RESERVED2_MAX (0x00000001U)
6132 
6133 #define CSL_DSS_VID1_ATTRIBUTES_VERTICALTAPS_MASK (0x00200000U)
6134 #define CSL_DSS_VID1_ATTRIBUTES_VERTICALTAPS_SHIFT (0x00000015U)
6135 #define CSL_DSS_VID1_ATTRIBUTES_VERTICALTAPS_MAX (0x00000001U)
6136 
6137 #define CSL_DSS_VID1_ATTRIBUTES_VERTICALTAPS_VAL_TAPS5 (0x1U)
6138 #define CSL_DSS_VID1_ATTRIBUTES_VERTICALTAPS_VAL_TAPS3 (0x0U)
6139 
6140 #define CSL_DSS_VID1_ATTRIBUTES_RESERVED6_MASK (0x00400000U)
6141 #define CSL_DSS_VID1_ATTRIBUTES_RESERVED6_SHIFT (0x00000016U)
6142 #define CSL_DSS_VID1_ATTRIBUTES_RESERVED6_MAX (0x00000001U)
6143 
6144 #define CSL_DSS_VID1_ATTRIBUTES_ARBITRATION_MASK (0x00800000U)
6145 #define CSL_DSS_VID1_ATTRIBUTES_ARBITRATION_SHIFT (0x00000017U)
6146 #define CSL_DSS_VID1_ATTRIBUTES_ARBITRATION_MAX (0x00000001U)
6147 
6148 #define CSL_DSS_VID1_ATTRIBUTES_ARBITRATION_VAL_HIGHPRIO (0x1U)
6149 #define CSL_DSS_VID1_ATTRIBUTES_ARBITRATION_VAL_NORMALPRIO (0x0U)
6150 
6151 #define CSL_DSS_VID1_ATTRIBUTES_SELFREFRESH_MASK (0x01000000U)
6152 #define CSL_DSS_VID1_ATTRIBUTES_SELFREFRESH_SHIFT (0x00000018U)
6153 #define CSL_DSS_VID1_ATTRIBUTES_SELFREFRESH_MAX (0x00000001U)
6154 
6155 #define CSL_DSS_VID1_ATTRIBUTES_SELFREFRESH_VAL_SELFREFRESHENB (0x1U)
6156 #define CSL_DSS_VID1_ATTRIBUTES_SELFREFRESH_VAL_SELFREFRESHDIS (0x0U)
6157 
6158 #define CSL_DSS_VID1_ATTRIBUTES_RESERVED5_MASK (0x0E000000U)
6159 #define CSL_DSS_VID1_ATTRIBUTES_RESERVED5_SHIFT (0x00000019U)
6160 #define CSL_DSS_VID1_ATTRIBUTES_RESERVED5_MAX (0x00000007U)
6161 
6162 #define CSL_DSS_VID1_ATTRIBUTES_PREMULTIPLYALPHA_MASK (0x10000000U)
6163 #define CSL_DSS_VID1_ATTRIBUTES_PREMULTIPLYALPHA_SHIFT (0x0000001CU)
6164 #define CSL_DSS_VID1_ATTRIBUTES_PREMULTIPLYALPHA_MAX (0x00000001U)
6165 
6166 #define CSL_DSS_VID1_ATTRIBUTES_PREMULTIPLYALPHA_VAL_PREMULTIPLIEDALPHA (0x1U)
6167 #define CSL_DSS_VID1_ATTRIBUTES_PREMULTIPLYALPHA_VAL_NONPREMULTIPLIEDALPHA (0x0U)
6168 
6169 #define CSL_DSS_VID1_ATTRIBUTES_GAMMAINVERSIONPOS_MASK (0x20000000U)
6170 #define CSL_DSS_VID1_ATTRIBUTES_GAMMAINVERSIONPOS_SHIFT (0x0000001DU)
6171 #define CSL_DSS_VID1_ATTRIBUTES_GAMMAINVERSIONPOS_MAX (0x00000001U)
6172 
6173 #define CSL_DSS_VID1_ATTRIBUTES_GAMMAINVERSIONPOS_VAL_PRESCALER (0x0U)
6174 #define CSL_DSS_VID1_ATTRIBUTES_GAMMAINVERSIONPOS_VAL_POSTSCALER (0x1U)
6175 
6176 #define CSL_DSS_VID1_ATTRIBUTES_GAMMAINVERSION_MASK (0x40000000U)
6177 #define CSL_DSS_VID1_ATTRIBUTES_GAMMAINVERSION_SHIFT (0x0000001EU)
6178 #define CSL_DSS_VID1_ATTRIBUTES_GAMMAINVERSION_MAX (0x00000001U)
6179 
6180 #define CSL_DSS_VID1_ATTRIBUTES_GAMMAINVERSION_VAL_INVGAMMAEN (0x1U)
6181 #define CSL_DSS_VID1_ATTRIBUTES_GAMMAINVERSION_VAL_INVGAMMADIS (0x0U)
6182 
6183 #define CSL_DSS_VID1_ATTRIBUTES_LUMAKEYENABLE_MASK (0x80000000U)
6184 #define CSL_DSS_VID1_ATTRIBUTES_LUMAKEYENABLE_SHIFT (0x0000001FU)
6185 #define CSL_DSS_VID1_ATTRIBUTES_LUMAKEYENABLE_MAX (0x00000001U)
6186 
6187 #define CSL_DSS_VID1_ATTRIBUTES_LUMAKEYENABLE_VAL_LUMAKEYEN (0x1U)
6188 #define CSL_DSS_VID1_ATTRIBUTES_LUMAKEYENABLE_VAL_LUMAKEYDIS (0x0U)
6189 
6190 /* ATTRIBUTES2 */
6191 
6192 #define CSL_DSS_VID1_ATTRIBUTES2_VC1ENABLE_MASK (0x00000001U)
6193 #define CSL_DSS_VID1_ATTRIBUTES2_VC1ENABLE_SHIFT (0x00000000U)
6194 #define CSL_DSS_VID1_ATTRIBUTES2_VC1ENABLE_MAX (0x00000001U)
6195 
6196 #define CSL_DSS_VID1_ATTRIBUTES2_VC1ENABLE_VAL_VC1ENB (0x1U)
6197 #define CSL_DSS_VID1_ATTRIBUTES2_VC1ENABLE_VAL_VC1DIS (0x0U)
6198 
6199 #define CSL_DSS_VID1_ATTRIBUTES2_VC1_RANGE_Y_MASK (0x0000000EU)
6200 #define CSL_DSS_VID1_ATTRIBUTES2_VC1_RANGE_Y_SHIFT (0x00000001U)
6201 #define CSL_DSS_VID1_ATTRIBUTES2_VC1_RANGE_Y_MAX (0x00000007U)
6202 
6203 #define CSL_DSS_VID1_ATTRIBUTES2_VC1_RANGE_CBCR_MASK (0x00000070U)
6204 #define CSL_DSS_VID1_ATTRIBUTES2_VC1_RANGE_CBCR_SHIFT (0x00000004U)
6205 #define CSL_DSS_VID1_ATTRIBUTES2_VC1_RANGE_CBCR_MAX (0x00000007U)
6206 
6207 #define CSL_DSS_VID1_ATTRIBUTES2_YUV_SIZE_MASK (0x00000180U)
6208 #define CSL_DSS_VID1_ATTRIBUTES2_YUV_SIZE_SHIFT (0x00000007U)
6209 #define CSL_DSS_VID1_ATTRIBUTES2_YUV_SIZE_MAX (0x00000003U)
6210 
6211 #define CSL_DSS_VID1_ATTRIBUTES2_YUV_SIZE_VAL_8B (0x0U)
6212 #define CSL_DSS_VID1_ATTRIBUTES2_YUV_SIZE_VAL_10B (0x1U)
6213 #define CSL_DSS_VID1_ATTRIBUTES2_YUV_SIZE_VAL_12B (0x2U)
6214 
6215 #define CSL_DSS_VID1_ATTRIBUTES2_YUV_MODE_MASK (0x00000200U)
6216 #define CSL_DSS_VID1_ATTRIBUTES2_YUV_MODE_SHIFT (0x00000009U)
6217 #define CSL_DSS_VID1_ATTRIBUTES2_YUV_MODE_MAX (0x00000001U)
6218 
6219 #define CSL_DSS_VID1_ATTRIBUTES2_YUV_MODE_VAL_PACKED (0x0U)
6220 #define CSL_DSS_VID1_ATTRIBUTES2_YUV_MODE_VAL_UNPACKED (0x1U)
6221 
6222 #define CSL_DSS_VID1_ATTRIBUTES2_YUV_ALIGN_MASK (0x00000400U)
6223 #define CSL_DSS_VID1_ATTRIBUTES2_YUV_ALIGN_SHIFT (0x0000000AU)
6224 #define CSL_DSS_VID1_ATTRIBUTES2_YUV_ALIGN_MAX (0x00000001U)
6225 
6226 #define CSL_DSS_VID1_ATTRIBUTES2_YUV_ALIGN_VAL_MSB (0x1U)
6227 #define CSL_DSS_VID1_ATTRIBUTES2_YUV_ALIGN_VAL_LSB (0x0U)
6228 
6229 #define CSL_DSS_VID1_ATTRIBUTES2_RESERVED1_MASK (0x0000F800U)
6230 #define CSL_DSS_VID1_ATTRIBUTES2_RESERVED1_SHIFT (0x0000000BU)
6231 #define CSL_DSS_VID1_ATTRIBUTES2_RESERVED1_MAX (0x0000001FU)
6232 
6233 #define CSL_DSS_VID1_ATTRIBUTES2_RESERVED2_MASK (0x01F00000U)
6234 #define CSL_DSS_VID1_ATTRIBUTES2_RESERVED2_SHIFT (0x00000014U)
6235 #define CSL_DSS_VID1_ATTRIBUTES2_RESERVED2_MAX (0x0000001FU)
6236 
6237 #define CSL_DSS_VID1_ATTRIBUTES2_MPORTSEL_MASK (0x02000000U)
6238 #define CSL_DSS_VID1_ATTRIBUTES2_MPORTSEL_SHIFT (0x00000019U)
6239 #define CSL_DSS_VID1_ATTRIBUTES2_MPORTSEL_MAX (0x00000001U)
6240 
6241 #define CSL_DSS_VID1_ATTRIBUTES2_MPORTSEL_VAL_PRIMARY (0x0U)
6242 #define CSL_DSS_VID1_ATTRIBUTES2_MPORTSEL_VAL_SECONDARY (0x1U)
6243 
6244 #define CSL_DSS_VID1_ATTRIBUTES2_TAGS_MASK (0x7C000000U)
6245 #define CSL_DSS_VID1_ATTRIBUTES2_TAGS_SHIFT (0x0000001AU)
6246 #define CSL_DSS_VID1_ATTRIBUTES2_TAGS_MAX (0x0000001FU)
6247 
6248 #define CSL_DSS_VID1_ATTRIBUTES2_RESERVED3_MASK (0x80000000U)
6249 #define CSL_DSS_VID1_ATTRIBUTES2_RESERVED3_SHIFT (0x0000001FU)
6250 #define CSL_DSS_VID1_ATTRIBUTES2_RESERVED3_MAX (0x00000001U)
6251 
6252 /* BA_0 */
6253 
6254 #define CSL_DSS_VID1_BA_0_BA_MASK (0xFFFFFFFFU)
6255 #define CSL_DSS_VID1_BA_0_BA_SHIFT (0x00000000U)
6256 #define CSL_DSS_VID1_BA_0_BA_MAX (0xFFFFFFFFU)
6257 
6258 /* BA_1 */
6259 
6260 #define CSL_DSS_VID1_BA_1_BA_MASK (0xFFFFFFFFU)
6261 #define CSL_DSS_VID1_BA_1_BA_SHIFT (0x00000000U)
6262 #define CSL_DSS_VID1_BA_1_BA_MAX (0xFFFFFFFFU)
6263 
6264 /* BA_UV_0 */
6265 
6266 #define CSL_DSS_VID1_BA_UV_0_BA_MASK (0xFFFFFFFFU)
6267 #define CSL_DSS_VID1_BA_UV_0_BA_SHIFT (0x00000000U)
6268 #define CSL_DSS_VID1_BA_UV_0_BA_MAX (0xFFFFFFFFU)
6269 
6270 /* BA_UV_1 */
6271 
6272 #define CSL_DSS_VID1_BA_UV_1_BA_MASK (0xFFFFFFFFU)
6273 #define CSL_DSS_VID1_BA_UV_1_BA_SHIFT (0x00000000U)
6274 #define CSL_DSS_VID1_BA_UV_1_BA_MAX (0xFFFFFFFFU)
6275 
6276 /* BUF_SIZE_STATUS */
6277 
6278 #define CSL_DSS_VID1_BUF_SIZE_STATUS_BUFSIZE_MASK (0x0000FFFFU)
6279 #define CSL_DSS_VID1_BUF_SIZE_STATUS_BUFSIZE_SHIFT (0x00000000U)
6280 #define CSL_DSS_VID1_BUF_SIZE_STATUS_BUFSIZE_MAX (0x0000FFFFU)
6281 
6282 #define CSL_DSS_VID1_BUF_SIZE_STATUS_RESERVED_61_MASK (0xFFFF0000U)
6283 #define CSL_DSS_VID1_BUF_SIZE_STATUS_RESERVED_61_SHIFT (0x00000010U)
6284 #define CSL_DSS_VID1_BUF_SIZE_STATUS_RESERVED_61_MAX (0x0000FFFFU)
6285 
6286 /* BUF_THRESHOLD */
6287 
6288 #define CSL_DSS_VID1_BUF_THRESHOLD_BUFLOWTHRESHOLD_MASK (0x0000FFFFU)
6289 #define CSL_DSS_VID1_BUF_THRESHOLD_BUFLOWTHRESHOLD_SHIFT (0x00000000U)
6290 #define CSL_DSS_VID1_BUF_THRESHOLD_BUFLOWTHRESHOLD_MAX (0x0000FFFFU)
6291 
6292 #define CSL_DSS_VID1_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MASK (0xFFFF0000U)
6293 #define CSL_DSS_VID1_BUF_THRESHOLD_BUFHIGHTHRESHOLD_SHIFT (0x00000010U)
6294 #define CSL_DSS_VID1_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MAX (0x0000FFFFU)
6295 
6296 /* CSC_COEF0 */
6297 
6298 #define CSL_DSS_VID1_CSC_COEF0_C00_MASK (0x000007FFU)
6299 #define CSL_DSS_VID1_CSC_COEF0_C00_SHIFT (0x00000000U)
6300 #define CSL_DSS_VID1_CSC_COEF0_C00_MAX (0x000007FFU)
6301 
6302 #define CSL_DSS_VID1_CSC_COEF0_RESERVED_53_MASK (0x0000F800U)
6303 #define CSL_DSS_VID1_CSC_COEF0_RESERVED_53_SHIFT (0x0000000BU)
6304 #define CSL_DSS_VID1_CSC_COEF0_RESERVED_53_MAX (0x0000001FU)
6305 
6306 #define CSL_DSS_VID1_CSC_COEF0_C01_MASK (0x07FF0000U)
6307 #define CSL_DSS_VID1_CSC_COEF0_C01_SHIFT (0x00000010U)
6308 #define CSL_DSS_VID1_CSC_COEF0_C01_MAX (0x000007FFU)
6309 
6310 #define CSL_DSS_VID1_CSC_COEF0_RESERVED_52_MASK (0xF8000000U)
6311 #define CSL_DSS_VID1_CSC_COEF0_RESERVED_52_SHIFT (0x0000001BU)
6312 #define CSL_DSS_VID1_CSC_COEF0_RESERVED_52_MAX (0x0000001FU)
6313 
6314 /* CSC_COEF1 */
6315 
6316 #define CSL_DSS_VID1_CSC_COEF1_C02_MASK (0x000007FFU)
6317 #define CSL_DSS_VID1_CSC_COEF1_C02_SHIFT (0x00000000U)
6318 #define CSL_DSS_VID1_CSC_COEF1_C02_MAX (0x000007FFU)
6319 
6320 #define CSL_DSS_VID1_CSC_COEF1_RESERVED_55_MASK (0x0000F800U)
6321 #define CSL_DSS_VID1_CSC_COEF1_RESERVED_55_SHIFT (0x0000000BU)
6322 #define CSL_DSS_VID1_CSC_COEF1_RESERVED_55_MAX (0x0000001FU)
6323 
6324 #define CSL_DSS_VID1_CSC_COEF1_C10_MASK (0x07FF0000U)
6325 #define CSL_DSS_VID1_CSC_COEF1_C10_SHIFT (0x00000010U)
6326 #define CSL_DSS_VID1_CSC_COEF1_C10_MAX (0x000007FFU)
6327 
6328 #define CSL_DSS_VID1_CSC_COEF1_RESERVED_54_MASK (0xF8000000U)
6329 #define CSL_DSS_VID1_CSC_COEF1_RESERVED_54_SHIFT (0x0000001BU)
6330 #define CSL_DSS_VID1_CSC_COEF1_RESERVED_54_MAX (0x0000001FU)
6331 
6332 /* CSC_COEF2 */
6333 
6334 #define CSL_DSS_VID1_CSC_COEF2_C11_MASK (0x000007FFU)
6335 #define CSL_DSS_VID1_CSC_COEF2_C11_SHIFT (0x00000000U)
6336 #define CSL_DSS_VID1_CSC_COEF2_C11_MAX (0x000007FFU)
6337 
6338 #define CSL_DSS_VID1_CSC_COEF2_RESERVED_57_MASK (0x0000F800U)
6339 #define CSL_DSS_VID1_CSC_COEF2_RESERVED_57_SHIFT (0x0000000BU)
6340 #define CSL_DSS_VID1_CSC_COEF2_RESERVED_57_MAX (0x0000001FU)
6341 
6342 #define CSL_DSS_VID1_CSC_COEF2_C12_MASK (0x07FF0000U)
6343 #define CSL_DSS_VID1_CSC_COEF2_C12_SHIFT (0x00000010U)
6344 #define CSL_DSS_VID1_CSC_COEF2_C12_MAX (0x000007FFU)
6345 
6346 #define CSL_DSS_VID1_CSC_COEF2_RESERVED_56_MASK (0xF8000000U)
6347 #define CSL_DSS_VID1_CSC_COEF2_RESERVED_56_SHIFT (0x0000001BU)
6348 #define CSL_DSS_VID1_CSC_COEF2_RESERVED_56_MAX (0x0000001FU)
6349 
6350 /* CSC_COEF3 */
6351 
6352 #define CSL_DSS_VID1_CSC_COEF3_C20_MASK (0x000007FFU)
6353 #define CSL_DSS_VID1_CSC_COEF3_C20_SHIFT (0x00000000U)
6354 #define CSL_DSS_VID1_CSC_COEF3_C20_MAX (0x000007FFU)
6355 
6356 #define CSL_DSS_VID1_CSC_COEF3_RESERVED_59_MASK (0x0000F800U)
6357 #define CSL_DSS_VID1_CSC_COEF3_RESERVED_59_SHIFT (0x0000000BU)
6358 #define CSL_DSS_VID1_CSC_COEF3_RESERVED_59_MAX (0x0000001FU)
6359 
6360 #define CSL_DSS_VID1_CSC_COEF3_C21_MASK (0x07FF0000U)
6361 #define CSL_DSS_VID1_CSC_COEF3_C21_SHIFT (0x00000010U)
6362 #define CSL_DSS_VID1_CSC_COEF3_C21_MAX (0x000007FFU)
6363 
6364 #define CSL_DSS_VID1_CSC_COEF3_RESERVED_58_MASK (0xF8000000U)
6365 #define CSL_DSS_VID1_CSC_COEF3_RESERVED_58_SHIFT (0x0000001BU)
6366 #define CSL_DSS_VID1_CSC_COEF3_RESERVED_58_MAX (0x0000001FU)
6367 
6368 /* CSC_COEF4 */
6369 
6370 #define CSL_DSS_VID1_CSC_COEF4_C22_MASK (0x000007FFU)
6371 #define CSL_DSS_VID1_CSC_COEF4_C22_SHIFT (0x00000000U)
6372 #define CSL_DSS_VID1_CSC_COEF4_C22_MAX (0x000007FFU)
6373 
6374 #define CSL_DSS_VID1_CSC_COEF4_RESERVED_60_MASK (0xFFFFF800U)
6375 #define CSL_DSS_VID1_CSC_COEF4_RESERVED_60_SHIFT (0x0000000BU)
6376 #define CSL_DSS_VID1_CSC_COEF4_RESERVED_60_MAX (0x001FFFFFU)
6377 
6378 /* CSC_COEF5 */
6379 
6380 #define CSL_DSS_VID1_CSC_COEF5_RESERVED_MASK (0x00000007U)
6381 #define CSL_DSS_VID1_CSC_COEF5_RESERVED_SHIFT (0x00000000U)
6382 #define CSL_DSS_VID1_CSC_COEF5_RESERVED_MAX (0x00000007U)
6383 
6384 #define CSL_DSS_VID1_CSC_COEF5_PREOFFSET1_MASK (0x0000FFF8U)
6385 #define CSL_DSS_VID1_CSC_COEF5_PREOFFSET1_SHIFT (0x00000003U)
6386 #define CSL_DSS_VID1_CSC_COEF5_PREOFFSET1_MAX (0x00001FFFU)
6387 
6388 #define CSL_DSS_VID1_CSC_COEF5_RESERVED1_MASK (0x00070000U)
6389 #define CSL_DSS_VID1_CSC_COEF5_RESERVED1_SHIFT (0x00000010U)
6390 #define CSL_DSS_VID1_CSC_COEF5_RESERVED1_MAX (0x00000007U)
6391 
6392 #define CSL_DSS_VID1_CSC_COEF5_PREOFFSET2_MASK (0xFFF80000U)
6393 #define CSL_DSS_VID1_CSC_COEF5_PREOFFSET2_SHIFT (0x00000013U)
6394 #define CSL_DSS_VID1_CSC_COEF5_PREOFFSET2_MAX (0x00001FFFU)
6395 
6396 /* CSC_COEF6 */
6397 
6398 #define CSL_DSS_VID1_CSC_COEF6_RESERVED_MASK (0x00000007U)
6399 #define CSL_DSS_VID1_CSC_COEF6_RESERVED_SHIFT (0x00000000U)
6400 #define CSL_DSS_VID1_CSC_COEF6_RESERVED_MAX (0x00000007U)
6401 
6402 #define CSL_DSS_VID1_CSC_COEF6_PREOFFSET3_MASK (0x0000FFF8U)
6403 #define CSL_DSS_VID1_CSC_COEF6_PREOFFSET3_SHIFT (0x00000003U)
6404 #define CSL_DSS_VID1_CSC_COEF6_PREOFFSET3_MAX (0x00001FFFU)
6405 
6406 #define CSL_DSS_VID1_CSC_COEF6_RESERVED1_MASK (0x00070000U)
6407 #define CSL_DSS_VID1_CSC_COEF6_RESERVED1_SHIFT (0x00000010U)
6408 #define CSL_DSS_VID1_CSC_COEF6_RESERVED1_MAX (0x00000007U)
6409 
6410 #define CSL_DSS_VID1_CSC_COEF6_POSTOFFSET1_MASK (0xFFF80000U)
6411 #define CSL_DSS_VID1_CSC_COEF6_POSTOFFSET1_SHIFT (0x00000013U)
6412 #define CSL_DSS_VID1_CSC_COEF6_POSTOFFSET1_MAX (0x00001FFFU)
6413 
6414 /* FIRH */
6415 
6416 #define CSL_DSS_VID1_FIRH_FIRHINC_MASK (0x00FFFFFFU)
6417 #define CSL_DSS_VID1_FIRH_FIRHINC_SHIFT (0x00000000U)
6418 #define CSL_DSS_VID1_FIRH_FIRHINC_MAX (0x00FFFFFFU)
6419 
6420 #define CSL_DSS_VID1_FIRH_RESERVED_MASK (0xFF000000U)
6421 #define CSL_DSS_VID1_FIRH_RESERVED_SHIFT (0x00000018U)
6422 #define CSL_DSS_VID1_FIRH_RESERVED_MAX (0x000000FFU)
6423 
6424 /* FIRH2 */
6425 
6426 #define CSL_DSS_VID1_FIRH2_FIRHINC_MASK (0x00FFFFFFU)
6427 #define CSL_DSS_VID1_FIRH2_FIRHINC_SHIFT (0x00000000U)
6428 #define CSL_DSS_VID1_FIRH2_FIRHINC_MAX (0x00FFFFFFU)
6429 
6430 #define CSL_DSS_VID1_FIRH2_RESERVED_MASK (0xFF000000U)
6431 #define CSL_DSS_VID1_FIRH2_RESERVED_SHIFT (0x00000018U)
6432 #define CSL_DSS_VID1_FIRH2_RESERVED_MAX (0x000000FFU)
6433 
6434 /* FIRV */
6435 
6436 #define CSL_DSS_VID1_FIRV_FIRVINC_MASK (0x00FFFFFFU)
6437 #define CSL_DSS_VID1_FIRV_FIRVINC_SHIFT (0x00000000U)
6438 #define CSL_DSS_VID1_FIRV_FIRVINC_MAX (0x00FFFFFFU)
6439 
6440 #define CSL_DSS_VID1_FIRV_RESERVED_MASK (0xFF000000U)
6441 #define CSL_DSS_VID1_FIRV_RESERVED_SHIFT (0x00000018U)
6442 #define CSL_DSS_VID1_FIRV_RESERVED_MAX (0x000000FFU)
6443 
6444 /* FIRV2 */
6445 
6446 #define CSL_DSS_VID1_FIRV2_FIRVINC_MASK (0x00FFFFFFU)
6447 #define CSL_DSS_VID1_FIRV2_FIRVINC_SHIFT (0x00000000U)
6448 #define CSL_DSS_VID1_FIRV2_FIRVINC_MAX (0x00FFFFFFU)
6449 
6450 #define CSL_DSS_VID1_FIRV2_RESERVED_MASK (0xFF000000U)
6451 #define CSL_DSS_VID1_FIRV2_RESERVED_SHIFT (0x00000018U)
6452 #define CSL_DSS_VID1_FIRV2_RESERVED_MAX (0x000000FFU)
6453 
6454 /* FIR_COEF_H0 */
6455 
6456 #define CSL_DSS_VID1_FIR_COEF_H0_FIRHC0_MASK (0x000003FFU)
6457 #define CSL_DSS_VID1_FIR_COEF_H0_FIRHC0_SHIFT (0x00000000U)
6458 #define CSL_DSS_VID1_FIR_COEF_H0_FIRHC0_MAX (0x000003FFU)
6459 
6460 #define CSL_DSS_VID1_FIR_COEF_H0_RESERVED1_MASK (0x3FFFFC00U)
6461 #define CSL_DSS_VID1_FIR_COEF_H0_RESERVED1_SHIFT (0x0000000AU)
6462 #define CSL_DSS_VID1_FIR_COEF_H0_RESERVED1_MAX (0x000FFFFFU)
6463 
6464 #define CSL_DSS_VID1_FIR_COEF_H0_RESERVED_MASK (0xC0000000U)
6465 #define CSL_DSS_VID1_FIR_COEF_H0_RESERVED_SHIFT (0x0000001EU)
6466 #define CSL_DSS_VID1_FIR_COEF_H0_RESERVED_MAX (0x00000003U)
6467 
6468 /* FIR_COEF_H0_C */
6469 
6470 #define CSL_DSS_VID1_FIR_COEF_H0_C_FIRHC0_MASK (0x000003FFU)
6471 #define CSL_DSS_VID1_FIR_COEF_H0_C_FIRHC0_SHIFT (0x00000000U)
6472 #define CSL_DSS_VID1_FIR_COEF_H0_C_FIRHC0_MAX (0x000003FFU)
6473 
6474 #define CSL_DSS_VID1_FIR_COEF_H0_C_RESERVED1_MASK (0x3FFFFC00U)
6475 #define CSL_DSS_VID1_FIR_COEF_H0_C_RESERVED1_SHIFT (0x0000000AU)
6476 #define CSL_DSS_VID1_FIR_COEF_H0_C_RESERVED1_MAX (0x000FFFFFU)
6477 
6478 #define CSL_DSS_VID1_FIR_COEF_H0_C_RESERVED_MASK (0xC0000000U)
6479 #define CSL_DSS_VID1_FIR_COEF_H0_C_RESERVED_SHIFT (0x0000001EU)
6480 #define CSL_DSS_VID1_FIR_COEF_H0_C_RESERVED_MAX (0x00000003U)
6481 
6482 /* FIR_COEF_H12 */
6483 
6484 #define CSL_DSS_VID1_FIR_COEF_H12_RESERVED1_MASK (0x000003FFU)
6485 #define CSL_DSS_VID1_FIR_COEF_H12_RESERVED1_SHIFT (0x00000000U)
6486 #define CSL_DSS_VID1_FIR_COEF_H12_RESERVED1_MAX (0x000003FFU)
6487 
6488 #define CSL_DSS_VID1_FIR_COEF_H12_FIRHC1_MASK (0x000FFC00U)
6489 #define CSL_DSS_VID1_FIR_COEF_H12_FIRHC1_SHIFT (0x0000000AU)
6490 #define CSL_DSS_VID1_FIR_COEF_H12_FIRHC1_MAX (0x000003FFU)
6491 
6492 #define CSL_DSS_VID1_FIR_COEF_H12_FIRHC2_MASK (0x3FF00000U)
6493 #define CSL_DSS_VID1_FIR_COEF_H12_FIRHC2_SHIFT (0x00000014U)
6494 #define CSL_DSS_VID1_FIR_COEF_H12_FIRHC2_MAX (0x000003FFU)
6495 
6496 #define CSL_DSS_VID1_FIR_COEF_H12_RESERVED_MASK (0xC0000000U)
6497 #define CSL_DSS_VID1_FIR_COEF_H12_RESERVED_SHIFT (0x0000001EU)
6498 #define CSL_DSS_VID1_FIR_COEF_H12_RESERVED_MAX (0x00000003U)
6499 
6500 /* FIR_COEF_H12_C */
6501 
6502 #define CSL_DSS_VID1_FIR_COEF_H12_C_RESERVED1_MASK (0x000003FFU)
6503 #define CSL_DSS_VID1_FIR_COEF_H12_C_RESERVED1_SHIFT (0x00000000U)
6504 #define CSL_DSS_VID1_FIR_COEF_H12_C_RESERVED1_MAX (0x000003FFU)
6505 
6506 #define CSL_DSS_VID1_FIR_COEF_H12_C_FIRHC1_MASK (0x000FFC00U)
6507 #define CSL_DSS_VID1_FIR_COEF_H12_C_FIRHC1_SHIFT (0x0000000AU)
6508 #define CSL_DSS_VID1_FIR_COEF_H12_C_FIRHC1_MAX (0x000003FFU)
6509 
6510 #define CSL_DSS_VID1_FIR_COEF_H12_C_FIRHC2_MASK (0x3FF00000U)
6511 #define CSL_DSS_VID1_FIR_COEF_H12_C_FIRHC2_SHIFT (0x00000014U)
6512 #define CSL_DSS_VID1_FIR_COEF_H12_C_FIRHC2_MAX (0x000003FFU)
6513 
6514 #define CSL_DSS_VID1_FIR_COEF_H12_C_RESERVED_MASK (0xC0000000U)
6515 #define CSL_DSS_VID1_FIR_COEF_H12_C_RESERVED_SHIFT (0x0000001EU)
6516 #define CSL_DSS_VID1_FIR_COEF_H12_C_RESERVED_MAX (0x00000003U)
6517 
6518 /* FIR_COEF_V0 */
6519 
6520 #define CSL_DSS_VID1_FIR_COEF_V0_FIRVC0_MASK (0x000003FFU)
6521 #define CSL_DSS_VID1_FIR_COEF_V0_FIRVC0_SHIFT (0x00000000U)
6522 #define CSL_DSS_VID1_FIR_COEF_V0_FIRVC0_MAX (0x000003FFU)
6523 
6524 #define CSL_DSS_VID1_FIR_COEF_V0_RESERVED1_MASK (0x3FFFFC00U)
6525 #define CSL_DSS_VID1_FIR_COEF_V0_RESERVED1_SHIFT (0x0000000AU)
6526 #define CSL_DSS_VID1_FIR_COEF_V0_RESERVED1_MAX (0x000FFFFFU)
6527 
6528 #define CSL_DSS_VID1_FIR_COEF_V0_RESERVED_MASK (0xC0000000U)
6529 #define CSL_DSS_VID1_FIR_COEF_V0_RESERVED_SHIFT (0x0000001EU)
6530 #define CSL_DSS_VID1_FIR_COEF_V0_RESERVED_MAX (0x00000003U)
6531 
6532 /* FIR_COEF_V0_C */
6533 
6534 #define CSL_DSS_VID1_FIR_COEF_V0_C_FIRVC0_MASK (0x000003FFU)
6535 #define CSL_DSS_VID1_FIR_COEF_V0_C_FIRVC0_SHIFT (0x00000000U)
6536 #define CSL_DSS_VID1_FIR_COEF_V0_C_FIRVC0_MAX (0x000003FFU)
6537 
6538 #define CSL_DSS_VID1_FIR_COEF_V0_C_RESERVED1_MASK (0x3FFFFC00U)
6539 #define CSL_DSS_VID1_FIR_COEF_V0_C_RESERVED1_SHIFT (0x0000000AU)
6540 #define CSL_DSS_VID1_FIR_COEF_V0_C_RESERVED1_MAX (0x000FFFFFU)
6541 
6542 #define CSL_DSS_VID1_FIR_COEF_V0_C_RESERVED_MASK (0xC0000000U)
6543 #define CSL_DSS_VID1_FIR_COEF_V0_C_RESERVED_SHIFT (0x0000001EU)
6544 #define CSL_DSS_VID1_FIR_COEF_V0_C_RESERVED_MAX (0x00000003U)
6545 
6546 /* FIR_COEF_V12 */
6547 
6548 #define CSL_DSS_VID1_FIR_COEF_V12_RESERVED1_MASK (0x000003FFU)
6549 #define CSL_DSS_VID1_FIR_COEF_V12_RESERVED1_SHIFT (0x00000000U)
6550 #define CSL_DSS_VID1_FIR_COEF_V12_RESERVED1_MAX (0x000003FFU)
6551 
6552 #define CSL_DSS_VID1_FIR_COEF_V12_FIRVC1_MASK (0x000FFC00U)
6553 #define CSL_DSS_VID1_FIR_COEF_V12_FIRVC1_SHIFT (0x0000000AU)
6554 #define CSL_DSS_VID1_FIR_COEF_V12_FIRVC1_MAX (0x000003FFU)
6555 
6556 #define CSL_DSS_VID1_FIR_COEF_V12_FIRVC2_MASK (0x3FF00000U)
6557 #define CSL_DSS_VID1_FIR_COEF_V12_FIRVC2_SHIFT (0x00000014U)
6558 #define CSL_DSS_VID1_FIR_COEF_V12_FIRVC2_MAX (0x000003FFU)
6559 
6560 #define CSL_DSS_VID1_FIR_COEF_V12_RESERVED_MASK (0xC0000000U)
6561 #define CSL_DSS_VID1_FIR_COEF_V12_RESERVED_SHIFT (0x0000001EU)
6562 #define CSL_DSS_VID1_FIR_COEF_V12_RESERVED_MAX (0x00000003U)
6563 
6564 /* FIR_COEF_V12_C */
6565 
6566 #define CSL_DSS_VID1_FIR_COEF_V12_C_RESERVED1_MASK (0x000003FFU)
6567 #define CSL_DSS_VID1_FIR_COEF_V12_C_RESERVED1_SHIFT (0x00000000U)
6568 #define CSL_DSS_VID1_FIR_COEF_V12_C_RESERVED1_MAX (0x000003FFU)
6569 
6570 #define CSL_DSS_VID1_FIR_COEF_V12_C_FIRVC1_MASK (0x000FFC00U)
6571 #define CSL_DSS_VID1_FIR_COEF_V12_C_FIRVC1_SHIFT (0x0000000AU)
6572 #define CSL_DSS_VID1_FIR_COEF_V12_C_FIRVC1_MAX (0x000003FFU)
6573 
6574 #define CSL_DSS_VID1_FIR_COEF_V12_C_FIRVC2_MASK (0x3FF00000U)
6575 #define CSL_DSS_VID1_FIR_COEF_V12_C_FIRVC2_SHIFT (0x00000014U)
6576 #define CSL_DSS_VID1_FIR_COEF_V12_C_FIRVC2_MAX (0x000003FFU)
6577 
6578 #define CSL_DSS_VID1_FIR_COEF_V12_C_RESERVED_MASK (0xC0000000U)
6579 #define CSL_DSS_VID1_FIR_COEF_V12_C_RESERVED_SHIFT (0x0000001EU)
6580 #define CSL_DSS_VID1_FIR_COEF_V12_C_RESERVED_MAX (0x00000003U)
6581 
6582 /* GLOBAL_ALPHA */
6583 
6584 #define CSL_DSS_VID1_GLOBAL_ALPHA_GLOBALALPHA_MASK (0x000000FFU)
6585 #define CSL_DSS_VID1_GLOBAL_ALPHA_GLOBALALPHA_SHIFT (0x00000000U)
6586 #define CSL_DSS_VID1_GLOBAL_ALPHA_GLOBALALPHA_MAX (0x000000FFU)
6587 
6588 #define CSL_DSS_VID1_GLOBAL_ALPHA_RESERVED_MASK (0xFFFFFF00U)
6589 #define CSL_DSS_VID1_GLOBAL_ALPHA_RESERVED_SHIFT (0x00000008U)
6590 #define CSL_DSS_VID1_GLOBAL_ALPHA_RESERVED_MAX (0x00FFFFFFU)
6591 
6592 /* MFLAG_THRESHOLD */
6593 
6594 #define CSL_DSS_VID1_MFLAG_THRESHOLD_LT_MFLAG_MASK (0x0000FFFFU)
6595 #define CSL_DSS_VID1_MFLAG_THRESHOLD_LT_MFLAG_SHIFT (0x00000000U)
6596 #define CSL_DSS_VID1_MFLAG_THRESHOLD_LT_MFLAG_MAX (0x0000FFFFU)
6597 
6598 #define CSL_DSS_VID1_MFLAG_THRESHOLD_HT_MFLAG_MASK (0xFFFF0000U)
6599 #define CSL_DSS_VID1_MFLAG_THRESHOLD_HT_MFLAG_SHIFT (0x00000010U)
6600 #define CSL_DSS_VID1_MFLAG_THRESHOLD_HT_MFLAG_MAX (0x0000FFFFU)
6601 
6602 /* PICTURE_SIZE */
6603 
6604 #define CSL_DSS_VID1_PICTURE_SIZE_MEMSIZEX_MASK (0x00003FFFU)
6605 #define CSL_DSS_VID1_PICTURE_SIZE_MEMSIZEX_SHIFT (0x00000000U)
6606 #define CSL_DSS_VID1_PICTURE_SIZE_MEMSIZEX_MAX (0x00003FFFU)
6607 
6608 #define CSL_DSS_VID1_PICTURE_SIZE_MEMSIZEY_MASK (0x3FFF0000U)
6609 #define CSL_DSS_VID1_PICTURE_SIZE_MEMSIZEY_SHIFT (0x00000010U)
6610 #define CSL_DSS_VID1_PICTURE_SIZE_MEMSIZEY_MAX (0x00003FFFU)
6611 
6612 /* PIXEL_INC */
6613 
6614 #define CSL_DSS_VID1_PIXEL_INC_PIXELINC_MASK (0x000000FFU)
6615 #define CSL_DSS_VID1_PIXEL_INC_PIXELINC_SHIFT (0x00000000U)
6616 #define CSL_DSS_VID1_PIXEL_INC_PIXELINC_MAX (0x000000FFU)
6617 
6618 #define CSL_DSS_VID1_PIXEL_INC_RESERVED_68_MASK (0xFFFFFF00U)
6619 #define CSL_DSS_VID1_PIXEL_INC_RESERVED_68_SHIFT (0x00000008U)
6620 #define CSL_DSS_VID1_PIXEL_INC_RESERVED_68_MAX (0x00FFFFFFU)
6621 
6622 /* PRELOAD */
6623 
6624 #define CSL_DSS_VID1_PRELOAD_PRELOAD_MASK (0x00000FFFU)
6625 #define CSL_DSS_VID1_PRELOAD_PRELOAD_SHIFT (0x00000000U)
6626 #define CSL_DSS_VID1_PRELOAD_PRELOAD_MAX (0x00000FFFU)
6627 
6628 #define CSL_DSS_VID1_PRELOAD_RESERVED_212_MASK (0xFFFFF000U)
6629 #define CSL_DSS_VID1_PRELOAD_RESERVED_212_SHIFT (0x0000000CU)
6630 #define CSL_DSS_VID1_PRELOAD_RESERVED_212_MAX (0x000FFFFFU)
6631 
6632 /* ROW_INC */
6633 
6634 #define CSL_DSS_VID1_ROW_INC_ROWINC_MASK (0xFFFFFFFFU)
6635 #define CSL_DSS_VID1_ROW_INC_ROWINC_SHIFT (0x00000000U)
6636 #define CSL_DSS_VID1_ROW_INC_ROWINC_MAX (0xFFFFFFFFU)
6637 
6638 /* SIZE */
6639 
6640 #define CSL_DSS_VID1_SIZE_SIZEX_MASK (0x00003FFFU)
6641 #define CSL_DSS_VID1_SIZE_SIZEX_SHIFT (0x00000000U)
6642 #define CSL_DSS_VID1_SIZE_SIZEX_MAX (0x00003FFFU)
6643 
6644 #define CSL_DSS_VID1_SIZE_SIZEY_MASK (0x3FFF0000U)
6645 #define CSL_DSS_VID1_SIZE_SIZEY_SHIFT (0x00000010U)
6646 #define CSL_DSS_VID1_SIZE_SIZEY_MAX (0x00003FFFU)
6647 
6648 /* BA_EXT_0 */
6649 
6650 #define CSL_DSS_VID1_BA_EXT_0_BA_EXT_MASK (0x0000FFFFU)
6651 #define CSL_DSS_VID1_BA_EXT_0_BA_EXT_SHIFT (0x00000000U)
6652 #define CSL_DSS_VID1_BA_EXT_0_BA_EXT_MAX (0x0000FFFFU)
6653 
6654 #define CSL_DSS_VID1_BA_EXT_0_RESERVED_MASK (0xFFFF0000U)
6655 #define CSL_DSS_VID1_BA_EXT_0_RESERVED_SHIFT (0x00000010U)
6656 #define CSL_DSS_VID1_BA_EXT_0_RESERVED_MAX (0x0000FFFFU)
6657 
6658 /* BA_EXT_1 */
6659 
6660 #define CSL_DSS_VID1_BA_EXT_1_BA_EXT_MASK (0x0000FFFFU)
6661 #define CSL_DSS_VID1_BA_EXT_1_BA_EXT_SHIFT (0x00000000U)
6662 #define CSL_DSS_VID1_BA_EXT_1_BA_EXT_MAX (0x0000FFFFU)
6663 
6664 #define CSL_DSS_VID1_BA_EXT_1_RESERVED_MASK (0xFFFF0000U)
6665 #define CSL_DSS_VID1_BA_EXT_1_RESERVED_SHIFT (0x00000010U)
6666 #define CSL_DSS_VID1_BA_EXT_1_RESERVED_MAX (0x0000FFFFU)
6667 
6668 /* BA_UV_EXT_0 */
6669 
6670 #define CSL_DSS_VID1_BA_UV_EXT_0_BA_UV_EXT_MASK (0x0000FFFFU)
6671 #define CSL_DSS_VID1_BA_UV_EXT_0_BA_UV_EXT_SHIFT (0x00000000U)
6672 #define CSL_DSS_VID1_BA_UV_EXT_0_BA_UV_EXT_MAX (0x0000FFFFU)
6673 
6674 #define CSL_DSS_VID1_BA_UV_EXT_0_RESERVED_MASK (0xFFFF0000U)
6675 #define CSL_DSS_VID1_BA_UV_EXT_0_RESERVED_SHIFT (0x00000010U)
6676 #define CSL_DSS_VID1_BA_UV_EXT_0_RESERVED_MAX (0x0000FFFFU)
6677 
6678 /* BA_UV_EXT_1 */
6679 
6680 #define CSL_DSS_VID1_BA_UV_EXT_1_BA_UV_EXT_MASK (0x0000FFFFU)
6681 #define CSL_DSS_VID1_BA_UV_EXT_1_BA_UV_EXT_SHIFT (0x00000000U)
6682 #define CSL_DSS_VID1_BA_UV_EXT_1_BA_UV_EXT_MAX (0x0000FFFFU)
6683 
6684 #define CSL_DSS_VID1_BA_UV_EXT_1_RESERVED_MASK (0xFFFF0000U)
6685 #define CSL_DSS_VID1_BA_UV_EXT_1_RESERVED_SHIFT (0x00000010U)
6686 #define CSL_DSS_VID1_BA_UV_EXT_1_RESERVED_MAX (0x0000FFFFU)
6687 
6688 /* CSC_COEF7 */
6689 
6690 #define CSL_DSS_VID1_CSC_COEF7_RESERVED_MASK (0x00000007U)
6691 #define CSL_DSS_VID1_CSC_COEF7_RESERVED_SHIFT (0x00000000U)
6692 #define CSL_DSS_VID1_CSC_COEF7_RESERVED_MAX (0x00000007U)
6693 
6694 #define CSL_DSS_VID1_CSC_COEF7_POSTOFFSET2_MASK (0x0000FFF8U)
6695 #define CSL_DSS_VID1_CSC_COEF7_POSTOFFSET2_SHIFT (0x00000003U)
6696 #define CSL_DSS_VID1_CSC_COEF7_POSTOFFSET2_MAX (0x00001FFFU)
6697 
6698 #define CSL_DSS_VID1_CSC_COEF7_RESERVED1_MASK (0x00070000U)
6699 #define CSL_DSS_VID1_CSC_COEF7_RESERVED1_SHIFT (0x00000010U)
6700 #define CSL_DSS_VID1_CSC_COEF7_RESERVED1_MAX (0x00000007U)
6701 
6702 #define CSL_DSS_VID1_CSC_COEF7_POSTOFFSET3_MASK (0xFFF80000U)
6703 #define CSL_DSS_VID1_CSC_COEF7_POSTOFFSET3_SHIFT (0x00000013U)
6704 #define CSL_DSS_VID1_CSC_COEF7_POSTOFFSET3_MAX (0x00001FFFU)
6705 
6706 /* ROW_INC_UV */
6707 
6708 #define CSL_DSS_VID1_ROW_INC_UV_ROWINC_MASK (0xFFFFFFFFU)
6709 #define CSL_DSS_VID1_ROW_INC_UV_ROWINC_SHIFT (0x00000000U)
6710 #define CSL_DSS_VID1_ROW_INC_UV_ROWINC_MAX (0xFFFFFFFFU)
6711 
6712 /* TILE */
6713 
6714 #define CSL_DSS_VID1_TILE_TILEINDEX_MASK (0x007FFFFFU)
6715 #define CSL_DSS_VID1_TILE_TILEINDEX_SHIFT (0x00000000U)
6716 #define CSL_DSS_VID1_TILE_TILEINDEX_MAX (0x007FFFFFU)
6717 
6718 /* TILE2 */
6719 
6720 #define CSL_DSS_VID1_TILE2_NUM_TILES_MASK (0x007FFFFFU)
6721 #define CSL_DSS_VID1_TILE2_NUM_TILES_SHIFT (0x00000000U)
6722 #define CSL_DSS_VID1_TILE2_NUM_TILES_MAX (0x007FFFFFU)
6723 
6724 #define CSL_DSS_VID1_TILE2_RESERVED_MASK (0xFF800000U)
6725 #define CSL_DSS_VID1_TILE2_RESERVED_SHIFT (0x00000017U)
6726 #define CSL_DSS_VID1_TILE2_RESERVED_MAX (0x000001FFU)
6727 
6728 /* FBDC_ATTRIBUTES */
6729 
6730 #define CSL_DSS_VID1_FBDC_ATTRIBUTES_ENABLE_MASK (0x00000001U)
6731 #define CSL_DSS_VID1_FBDC_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
6732 #define CSL_DSS_VID1_FBDC_ATTRIBUTES_ENABLE_MAX (0x00000001U)
6733 
6734 #define CSL_DSS_VID1_FBDC_ATTRIBUTES_FORMAT_MASK (0x000000FEU)
6735 #define CSL_DSS_VID1_FBDC_ATTRIBUTES_FORMAT_SHIFT (0x00000001U)
6736 #define CSL_DSS_VID1_FBDC_ATTRIBUTES_FORMAT_MAX (0x0000007FU)
6737 
6738 #define CSL_DSS_VID1_FBDC_ATTRIBUTES_FORMAT_VAL_U8U8U8U8 (0xCU)
6739 #define CSL_DSS_VID1_FBDC_ATTRIBUTES_FORMAT_VAL_A2R10B10G10 (0xEU)
6740 
6741 #define CSL_DSS_VID1_FBDC_ATTRIBUTES_TILETYPE_MASK (0x00000300U)
6742 #define CSL_DSS_VID1_FBDC_ATTRIBUTES_TILETYPE_SHIFT (0x00000008U)
6743 #define CSL_DSS_VID1_FBDC_ATTRIBUTES_TILETYPE_MAX (0x00000003U)
6744 
6745 #define CSL_DSS_VID1_FBDC_ATTRIBUTES_TILETYPE_VAL_TILE16BY4 (0x2U)
6746 #define CSL_DSS_VID1_FBDC_ATTRIBUTES_TILETYPE_VAL_TILE32BY2 (0x3U)
6747 
6748 /* FBDC_CLEAR_COLOR */
6749 
6750 #define CSL_DSS_VID1_FBDC_CLEAR_COLOR_CLEARCOLOR_MASK (0xFFFFFFFFU)
6751 #define CSL_DSS_VID1_FBDC_CLEAR_COLOR_CLEARCOLOR_SHIFT (0x00000000U)
6752 #define CSL_DSS_VID1_FBDC_CLEAR_COLOR_CLEARCOLOR_MAX (0xFFFFFFFFU)
6753 
6754 /* CLUT_0 */
6755 
6756 #define CSL_DSS_VID1_CLUT_0_VALUE_B_MASK (0x000003FFU)
6757 #define CSL_DSS_VID1_CLUT_0_VALUE_B_SHIFT (0x00000000U)
6758 #define CSL_DSS_VID1_CLUT_0_VALUE_B_MAX (0x000003FFU)
6759 
6760 #define CSL_DSS_VID1_CLUT_0_VALUE_G_MASK (0x000FFC00U)
6761 #define CSL_DSS_VID1_CLUT_0_VALUE_G_SHIFT (0x0000000AU)
6762 #define CSL_DSS_VID1_CLUT_0_VALUE_G_MAX (0x000003FFU)
6763 
6764 #define CSL_DSS_VID1_CLUT_0_VALUE_R_MASK (0x3FF00000U)
6765 #define CSL_DSS_VID1_CLUT_0_VALUE_R_SHIFT (0x00000014U)
6766 #define CSL_DSS_VID1_CLUT_0_VALUE_R_MAX (0x000003FFU)
6767 
6768 #define CSL_DSS_VID1_CLUT_0_INDEX_MASK (0x80000000U)
6769 #define CSL_DSS_VID1_CLUT_0_INDEX_SHIFT (0x0000001FU)
6770 #define CSL_DSS_VID1_CLUT_0_INDEX_MAX (0x00000001U)
6771 
6772 /* CLUT_1 */
6773 
6774 #define CSL_DSS_VID1_CLUT_1_VALUE_B_MASK (0x000003FFU)
6775 #define CSL_DSS_VID1_CLUT_1_VALUE_B_SHIFT (0x00000000U)
6776 #define CSL_DSS_VID1_CLUT_1_VALUE_B_MAX (0x000003FFU)
6777 
6778 #define CSL_DSS_VID1_CLUT_1_VALUE_G_MASK (0x000FFC00U)
6779 #define CSL_DSS_VID1_CLUT_1_VALUE_G_SHIFT (0x0000000AU)
6780 #define CSL_DSS_VID1_CLUT_1_VALUE_G_MAX (0x000003FFU)
6781 
6782 #define CSL_DSS_VID1_CLUT_1_VALUE_R_MASK (0x3FF00000U)
6783 #define CSL_DSS_VID1_CLUT_1_VALUE_R_SHIFT (0x00000014U)
6784 #define CSL_DSS_VID1_CLUT_1_VALUE_R_MAX (0x000003FFU)
6785 
6786 #define CSL_DSS_VID1_CLUT_1_INDEX_MASK (0x80000000U)
6787 #define CSL_DSS_VID1_CLUT_1_INDEX_SHIFT (0x0000001FU)
6788 #define CSL_DSS_VID1_CLUT_1_INDEX_MAX (0x00000001U)
6789 
6790 /* CLUT_2 */
6791 
6792 #define CSL_DSS_VID1_CLUT_2_VALUE_B_MASK (0x000003FFU)
6793 #define CSL_DSS_VID1_CLUT_2_VALUE_B_SHIFT (0x00000000U)
6794 #define CSL_DSS_VID1_CLUT_2_VALUE_B_MAX (0x000003FFU)
6795 
6796 #define CSL_DSS_VID1_CLUT_2_VALUE_G_MASK (0x000FFC00U)
6797 #define CSL_DSS_VID1_CLUT_2_VALUE_G_SHIFT (0x0000000AU)
6798 #define CSL_DSS_VID1_CLUT_2_VALUE_G_MAX (0x000003FFU)
6799 
6800 #define CSL_DSS_VID1_CLUT_2_VALUE_R_MASK (0x3FF00000U)
6801 #define CSL_DSS_VID1_CLUT_2_VALUE_R_SHIFT (0x00000014U)
6802 #define CSL_DSS_VID1_CLUT_2_VALUE_R_MAX (0x000003FFU)
6803 
6804 #define CSL_DSS_VID1_CLUT_2_INDEX_MASK (0x80000000U)
6805 #define CSL_DSS_VID1_CLUT_2_INDEX_SHIFT (0x0000001FU)
6806 #define CSL_DSS_VID1_CLUT_2_INDEX_MAX (0x00000001U)
6807 
6808 /* CLUT_3 */
6809 
6810 #define CSL_DSS_VID1_CLUT_3_VALUE_B_MASK (0x000003FFU)
6811 #define CSL_DSS_VID1_CLUT_3_VALUE_B_SHIFT (0x00000000U)
6812 #define CSL_DSS_VID1_CLUT_3_VALUE_B_MAX (0x000003FFU)
6813 
6814 #define CSL_DSS_VID1_CLUT_3_VALUE_G_MASK (0x000FFC00U)
6815 #define CSL_DSS_VID1_CLUT_3_VALUE_G_SHIFT (0x0000000AU)
6816 #define CSL_DSS_VID1_CLUT_3_VALUE_G_MAX (0x000003FFU)
6817 
6818 #define CSL_DSS_VID1_CLUT_3_VALUE_R_MASK (0x3FF00000U)
6819 #define CSL_DSS_VID1_CLUT_3_VALUE_R_SHIFT (0x00000014U)
6820 #define CSL_DSS_VID1_CLUT_3_VALUE_R_MAX (0x000003FFU)
6821 
6822 #define CSL_DSS_VID1_CLUT_3_INDEX_MASK (0x80000000U)
6823 #define CSL_DSS_VID1_CLUT_3_INDEX_SHIFT (0x0000001FU)
6824 #define CSL_DSS_VID1_CLUT_3_INDEX_MAX (0x00000001U)
6825 
6826 /* CLUT_4 */
6827 
6828 #define CSL_DSS_VID1_CLUT_4_VALUE_B_MASK (0x000003FFU)
6829 #define CSL_DSS_VID1_CLUT_4_VALUE_B_SHIFT (0x00000000U)
6830 #define CSL_DSS_VID1_CLUT_4_VALUE_B_MAX (0x000003FFU)
6831 
6832 #define CSL_DSS_VID1_CLUT_4_VALUE_G_MASK (0x000FFC00U)
6833 #define CSL_DSS_VID1_CLUT_4_VALUE_G_SHIFT (0x0000000AU)
6834 #define CSL_DSS_VID1_CLUT_4_VALUE_G_MAX (0x000003FFU)
6835 
6836 #define CSL_DSS_VID1_CLUT_4_VALUE_R_MASK (0x3FF00000U)
6837 #define CSL_DSS_VID1_CLUT_4_VALUE_R_SHIFT (0x00000014U)
6838 #define CSL_DSS_VID1_CLUT_4_VALUE_R_MAX (0x000003FFU)
6839 
6840 #define CSL_DSS_VID1_CLUT_4_INDEX_MASK (0x80000000U)
6841 #define CSL_DSS_VID1_CLUT_4_INDEX_SHIFT (0x0000001FU)
6842 #define CSL_DSS_VID1_CLUT_4_INDEX_MAX (0x00000001U)
6843 
6844 /* CLUT_5 */
6845 
6846 #define CSL_DSS_VID1_CLUT_5_VALUE_B_MASK (0x000003FFU)
6847 #define CSL_DSS_VID1_CLUT_5_VALUE_B_SHIFT (0x00000000U)
6848 #define CSL_DSS_VID1_CLUT_5_VALUE_B_MAX (0x000003FFU)
6849 
6850 #define CSL_DSS_VID1_CLUT_5_VALUE_G_MASK (0x000FFC00U)
6851 #define CSL_DSS_VID1_CLUT_5_VALUE_G_SHIFT (0x0000000AU)
6852 #define CSL_DSS_VID1_CLUT_5_VALUE_G_MAX (0x000003FFU)
6853 
6854 #define CSL_DSS_VID1_CLUT_5_VALUE_R_MASK (0x3FF00000U)
6855 #define CSL_DSS_VID1_CLUT_5_VALUE_R_SHIFT (0x00000014U)
6856 #define CSL_DSS_VID1_CLUT_5_VALUE_R_MAX (0x000003FFU)
6857 
6858 #define CSL_DSS_VID1_CLUT_5_INDEX_MASK (0x80000000U)
6859 #define CSL_DSS_VID1_CLUT_5_INDEX_SHIFT (0x0000001FU)
6860 #define CSL_DSS_VID1_CLUT_5_INDEX_MAX (0x00000001U)
6861 
6862 /* CLUT_6 */
6863 
6864 #define CSL_DSS_VID1_CLUT_6_VALUE_B_MASK (0x000003FFU)
6865 #define CSL_DSS_VID1_CLUT_6_VALUE_B_SHIFT (0x00000000U)
6866 #define CSL_DSS_VID1_CLUT_6_VALUE_B_MAX (0x000003FFU)
6867 
6868 #define CSL_DSS_VID1_CLUT_6_VALUE_G_MASK (0x000FFC00U)
6869 #define CSL_DSS_VID1_CLUT_6_VALUE_G_SHIFT (0x0000000AU)
6870 #define CSL_DSS_VID1_CLUT_6_VALUE_G_MAX (0x000003FFU)
6871 
6872 #define CSL_DSS_VID1_CLUT_6_VALUE_R_MASK (0x3FF00000U)
6873 #define CSL_DSS_VID1_CLUT_6_VALUE_R_SHIFT (0x00000014U)
6874 #define CSL_DSS_VID1_CLUT_6_VALUE_R_MAX (0x000003FFU)
6875 
6876 #define CSL_DSS_VID1_CLUT_6_INDEX_MASK (0x80000000U)
6877 #define CSL_DSS_VID1_CLUT_6_INDEX_SHIFT (0x0000001FU)
6878 #define CSL_DSS_VID1_CLUT_6_INDEX_MAX (0x00000001U)
6879 
6880 /* CLUT_7 */
6881 
6882 #define CSL_DSS_VID1_CLUT_7_VALUE_B_MASK (0x000003FFU)
6883 #define CSL_DSS_VID1_CLUT_7_VALUE_B_SHIFT (0x00000000U)
6884 #define CSL_DSS_VID1_CLUT_7_VALUE_B_MAX (0x000003FFU)
6885 
6886 #define CSL_DSS_VID1_CLUT_7_VALUE_G_MASK (0x000FFC00U)
6887 #define CSL_DSS_VID1_CLUT_7_VALUE_G_SHIFT (0x0000000AU)
6888 #define CSL_DSS_VID1_CLUT_7_VALUE_G_MAX (0x000003FFU)
6889 
6890 #define CSL_DSS_VID1_CLUT_7_VALUE_R_MASK (0x3FF00000U)
6891 #define CSL_DSS_VID1_CLUT_7_VALUE_R_SHIFT (0x00000014U)
6892 #define CSL_DSS_VID1_CLUT_7_VALUE_R_MAX (0x000003FFU)
6893 
6894 #define CSL_DSS_VID1_CLUT_7_INDEX_MASK (0x80000000U)
6895 #define CSL_DSS_VID1_CLUT_7_INDEX_SHIFT (0x0000001FU)
6896 #define CSL_DSS_VID1_CLUT_7_INDEX_MAX (0x00000001U)
6897 
6898 /* CLUT_8 */
6899 
6900 #define CSL_DSS_VID1_CLUT_8_VALUE_B_MASK (0x000003FFU)
6901 #define CSL_DSS_VID1_CLUT_8_VALUE_B_SHIFT (0x00000000U)
6902 #define CSL_DSS_VID1_CLUT_8_VALUE_B_MAX (0x000003FFU)
6903 
6904 #define CSL_DSS_VID1_CLUT_8_VALUE_G_MASK (0x000FFC00U)
6905 #define CSL_DSS_VID1_CLUT_8_VALUE_G_SHIFT (0x0000000AU)
6906 #define CSL_DSS_VID1_CLUT_8_VALUE_G_MAX (0x000003FFU)
6907 
6908 #define CSL_DSS_VID1_CLUT_8_VALUE_R_MASK (0x3FF00000U)
6909 #define CSL_DSS_VID1_CLUT_8_VALUE_R_SHIFT (0x00000014U)
6910 #define CSL_DSS_VID1_CLUT_8_VALUE_R_MAX (0x000003FFU)
6911 
6912 #define CSL_DSS_VID1_CLUT_8_INDEX_MASK (0x80000000U)
6913 #define CSL_DSS_VID1_CLUT_8_INDEX_SHIFT (0x0000001FU)
6914 #define CSL_DSS_VID1_CLUT_8_INDEX_MAX (0x00000001U)
6915 
6916 /* CLUT_9 */
6917 
6918 #define CSL_DSS_VID1_CLUT_9_VALUE_B_MASK (0x000003FFU)
6919 #define CSL_DSS_VID1_CLUT_9_VALUE_B_SHIFT (0x00000000U)
6920 #define CSL_DSS_VID1_CLUT_9_VALUE_B_MAX (0x000003FFU)
6921 
6922 #define CSL_DSS_VID1_CLUT_9_VALUE_G_MASK (0x000FFC00U)
6923 #define CSL_DSS_VID1_CLUT_9_VALUE_G_SHIFT (0x0000000AU)
6924 #define CSL_DSS_VID1_CLUT_9_VALUE_G_MAX (0x000003FFU)
6925 
6926 #define CSL_DSS_VID1_CLUT_9_VALUE_R_MASK (0x3FF00000U)
6927 #define CSL_DSS_VID1_CLUT_9_VALUE_R_SHIFT (0x00000014U)
6928 #define CSL_DSS_VID1_CLUT_9_VALUE_R_MAX (0x000003FFU)
6929 
6930 #define CSL_DSS_VID1_CLUT_9_INDEX_MASK (0x80000000U)
6931 #define CSL_DSS_VID1_CLUT_9_INDEX_SHIFT (0x0000001FU)
6932 #define CSL_DSS_VID1_CLUT_9_INDEX_MAX (0x00000001U)
6933 
6934 /* CLUT_10 */
6935 
6936 #define CSL_DSS_VID1_CLUT_10_VALUE_B_MASK (0x000003FFU)
6937 #define CSL_DSS_VID1_CLUT_10_VALUE_B_SHIFT (0x00000000U)
6938 #define CSL_DSS_VID1_CLUT_10_VALUE_B_MAX (0x000003FFU)
6939 
6940 #define CSL_DSS_VID1_CLUT_10_VALUE_G_MASK (0x000FFC00U)
6941 #define CSL_DSS_VID1_CLUT_10_VALUE_G_SHIFT (0x0000000AU)
6942 #define CSL_DSS_VID1_CLUT_10_VALUE_G_MAX (0x000003FFU)
6943 
6944 #define CSL_DSS_VID1_CLUT_10_VALUE_R_MASK (0x3FF00000U)
6945 #define CSL_DSS_VID1_CLUT_10_VALUE_R_SHIFT (0x00000014U)
6946 #define CSL_DSS_VID1_CLUT_10_VALUE_R_MAX (0x000003FFU)
6947 
6948 #define CSL_DSS_VID1_CLUT_10_INDEX_MASK (0x80000000U)
6949 #define CSL_DSS_VID1_CLUT_10_INDEX_SHIFT (0x0000001FU)
6950 #define CSL_DSS_VID1_CLUT_10_INDEX_MAX (0x00000001U)
6951 
6952 /* CLUT_11 */
6953 
6954 #define CSL_DSS_VID1_CLUT_11_VALUE_B_MASK (0x000003FFU)
6955 #define CSL_DSS_VID1_CLUT_11_VALUE_B_SHIFT (0x00000000U)
6956 #define CSL_DSS_VID1_CLUT_11_VALUE_B_MAX (0x000003FFU)
6957 
6958 #define CSL_DSS_VID1_CLUT_11_VALUE_G_MASK (0x000FFC00U)
6959 #define CSL_DSS_VID1_CLUT_11_VALUE_G_SHIFT (0x0000000AU)
6960 #define CSL_DSS_VID1_CLUT_11_VALUE_G_MAX (0x000003FFU)
6961 
6962 #define CSL_DSS_VID1_CLUT_11_VALUE_R_MASK (0x3FF00000U)
6963 #define CSL_DSS_VID1_CLUT_11_VALUE_R_SHIFT (0x00000014U)
6964 #define CSL_DSS_VID1_CLUT_11_VALUE_R_MAX (0x000003FFU)
6965 
6966 #define CSL_DSS_VID1_CLUT_11_INDEX_MASK (0x80000000U)
6967 #define CSL_DSS_VID1_CLUT_11_INDEX_SHIFT (0x0000001FU)
6968 #define CSL_DSS_VID1_CLUT_11_INDEX_MAX (0x00000001U)
6969 
6970 /* CLUT_12 */
6971 
6972 #define CSL_DSS_VID1_CLUT_12_VALUE_B_MASK (0x000003FFU)
6973 #define CSL_DSS_VID1_CLUT_12_VALUE_B_SHIFT (0x00000000U)
6974 #define CSL_DSS_VID1_CLUT_12_VALUE_B_MAX (0x000003FFU)
6975 
6976 #define CSL_DSS_VID1_CLUT_12_VALUE_G_MASK (0x000FFC00U)
6977 #define CSL_DSS_VID1_CLUT_12_VALUE_G_SHIFT (0x0000000AU)
6978 #define CSL_DSS_VID1_CLUT_12_VALUE_G_MAX (0x000003FFU)
6979 
6980 #define CSL_DSS_VID1_CLUT_12_VALUE_R_MASK (0x3FF00000U)
6981 #define CSL_DSS_VID1_CLUT_12_VALUE_R_SHIFT (0x00000014U)
6982 #define CSL_DSS_VID1_CLUT_12_VALUE_R_MAX (0x000003FFU)
6983 
6984 #define CSL_DSS_VID1_CLUT_12_INDEX_MASK (0x80000000U)
6985 #define CSL_DSS_VID1_CLUT_12_INDEX_SHIFT (0x0000001FU)
6986 #define CSL_DSS_VID1_CLUT_12_INDEX_MAX (0x00000001U)
6987 
6988 /* CLUT_13 */
6989 
6990 #define CSL_DSS_VID1_CLUT_13_VALUE_B_MASK (0x000003FFU)
6991 #define CSL_DSS_VID1_CLUT_13_VALUE_B_SHIFT (0x00000000U)
6992 #define CSL_DSS_VID1_CLUT_13_VALUE_B_MAX (0x000003FFU)
6993 
6994 #define CSL_DSS_VID1_CLUT_13_VALUE_G_MASK (0x000FFC00U)
6995 #define CSL_DSS_VID1_CLUT_13_VALUE_G_SHIFT (0x0000000AU)
6996 #define CSL_DSS_VID1_CLUT_13_VALUE_G_MAX (0x000003FFU)
6997 
6998 #define CSL_DSS_VID1_CLUT_13_VALUE_R_MASK (0x3FF00000U)
6999 #define CSL_DSS_VID1_CLUT_13_VALUE_R_SHIFT (0x00000014U)
7000 #define CSL_DSS_VID1_CLUT_13_VALUE_R_MAX (0x000003FFU)
7001 
7002 #define CSL_DSS_VID1_CLUT_13_INDEX_MASK (0x80000000U)
7003 #define CSL_DSS_VID1_CLUT_13_INDEX_SHIFT (0x0000001FU)
7004 #define CSL_DSS_VID1_CLUT_13_INDEX_MAX (0x00000001U)
7005 
7006 /* CLUT_14 */
7007 
7008 #define CSL_DSS_VID1_CLUT_14_VALUE_B_MASK (0x000003FFU)
7009 #define CSL_DSS_VID1_CLUT_14_VALUE_B_SHIFT (0x00000000U)
7010 #define CSL_DSS_VID1_CLUT_14_VALUE_B_MAX (0x000003FFU)
7011 
7012 #define CSL_DSS_VID1_CLUT_14_VALUE_G_MASK (0x000FFC00U)
7013 #define CSL_DSS_VID1_CLUT_14_VALUE_G_SHIFT (0x0000000AU)
7014 #define CSL_DSS_VID1_CLUT_14_VALUE_G_MAX (0x000003FFU)
7015 
7016 #define CSL_DSS_VID1_CLUT_14_VALUE_R_MASK (0x3FF00000U)
7017 #define CSL_DSS_VID1_CLUT_14_VALUE_R_SHIFT (0x00000014U)
7018 #define CSL_DSS_VID1_CLUT_14_VALUE_R_MAX (0x000003FFU)
7019 
7020 #define CSL_DSS_VID1_CLUT_14_INDEX_MASK (0x80000000U)
7021 #define CSL_DSS_VID1_CLUT_14_INDEX_SHIFT (0x0000001FU)
7022 #define CSL_DSS_VID1_CLUT_14_INDEX_MAX (0x00000001U)
7023 
7024 /* CLUT_15 */
7025 
7026 #define CSL_DSS_VID1_CLUT_15_VALUE_B_MASK (0x000003FFU)
7027 #define CSL_DSS_VID1_CLUT_15_VALUE_B_SHIFT (0x00000000U)
7028 #define CSL_DSS_VID1_CLUT_15_VALUE_B_MAX (0x000003FFU)
7029 
7030 #define CSL_DSS_VID1_CLUT_15_VALUE_G_MASK (0x000FFC00U)
7031 #define CSL_DSS_VID1_CLUT_15_VALUE_G_SHIFT (0x0000000AU)
7032 #define CSL_DSS_VID1_CLUT_15_VALUE_G_MAX (0x000003FFU)
7033 
7034 #define CSL_DSS_VID1_CLUT_15_VALUE_R_MASK (0x3FF00000U)
7035 #define CSL_DSS_VID1_CLUT_15_VALUE_R_SHIFT (0x00000014U)
7036 #define CSL_DSS_VID1_CLUT_15_VALUE_R_MAX (0x000003FFU)
7037 
7038 #define CSL_DSS_VID1_CLUT_15_INDEX_MASK (0x80000000U)
7039 #define CSL_DSS_VID1_CLUT_15_INDEX_SHIFT (0x0000001FU)
7040 #define CSL_DSS_VID1_CLUT_15_INDEX_MAX (0x00000001U)
7041 
7042 /* SAFETY_ATTRIBUTES */
7043 
7044 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_ENABLE_MASK (0x00000001U)
7045 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
7046 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_ENABLE_MAX (0x00000001U)
7047 
7048 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_CAPTUREMODE_MASK (0x00000002U)
7049 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_CAPTUREMODE_SHIFT (0x00000001U)
7050 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_CAPTUREMODE_MAX (0x00000001U)
7051 
7052 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_DATACHECK (0x1U)
7053 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_FRAMEFREEZE (0x0U)
7054 
7055 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_SEEDSELECT_MASK (0x00000004U)
7056 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_SEEDSELECT_SHIFT (0x00000002U)
7057 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_SEEDSELECT_MAX (0x00000001U)
7058 
7059 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_ENABLE (0x1U)
7060 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_DISABLE (0x0U)
7061 
7062 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_THRESHOLD_MASK (0x000007F8U)
7063 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_THRESHOLD_SHIFT (0x00000003U)
7064 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_THRESHOLD_MAX (0x000000FFU)
7065 
7066 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_FRAMESKIP_MASK (0x00001800U)
7067 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_FRAMESKIP_SHIFT (0x0000000BU)
7068 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_FRAMESKIP_MAX (0x00000003U)
7069 
7070 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_DISABLE (0x0U)
7071 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_EVEN (0x1U)
7072 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_ODD (0x2U)
7073 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_RESERVED (0x3U)
7074 
7075 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_RESERVED_MASK (0xFFFFE000U)
7076 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_RESERVED_SHIFT (0x0000000DU)
7077 #define CSL_DSS_VID1_SAFETY_ATTRIBUTES_RESERVED_MAX (0x0007FFFFU)
7078 
7079 /* SAFETY_CAPT_SIGNATURE */
7080 
7081 #define CSL_DSS_VID1_SAFETY_CAPT_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
7082 #define CSL_DSS_VID1_SAFETY_CAPT_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
7083 #define CSL_DSS_VID1_SAFETY_CAPT_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
7084 
7085 /* SAFETY_POSITION */
7086 
7087 #define CSL_DSS_VID1_SAFETY_POSITION_POSX_MASK (0x00003FFFU)
7088 #define CSL_DSS_VID1_SAFETY_POSITION_POSX_SHIFT (0x00000000U)
7089 #define CSL_DSS_VID1_SAFETY_POSITION_POSX_MAX (0x00003FFFU)
7090 
7091 #define CSL_DSS_VID1_SAFETY_POSITION_POSY_MASK (0x3FFF0000U)
7092 #define CSL_DSS_VID1_SAFETY_POSITION_POSY_SHIFT (0x00000010U)
7093 #define CSL_DSS_VID1_SAFETY_POSITION_POSY_MAX (0x00003FFFU)
7094 
7095 /* SAFETY_REF_SIGNATURE */
7096 
7097 #define CSL_DSS_VID1_SAFETY_REF_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
7098 #define CSL_DSS_VID1_SAFETY_REF_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
7099 #define CSL_DSS_VID1_SAFETY_REF_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
7100 
7101 /* SAFETY_SIZE */
7102 
7103 #define CSL_DSS_VID1_SAFETY_SIZE_SIZEX_MASK (0x00003FFFU)
7104 #define CSL_DSS_VID1_SAFETY_SIZE_SIZEX_SHIFT (0x00000000U)
7105 #define CSL_DSS_VID1_SAFETY_SIZE_SIZEX_MAX (0x00003FFFU)
7106 
7107 #define CSL_DSS_VID1_SAFETY_SIZE_SIZEY_MASK (0x3FFF0000U)
7108 #define CSL_DSS_VID1_SAFETY_SIZE_SIZEY_SHIFT (0x00000010U)
7109 #define CSL_DSS_VID1_SAFETY_SIZE_SIZEY_MAX (0x00003FFFU)
7110 
7111 /* SAFETY_LFSR_SEED */
7112 
7113 #define CSL_DSS_VID1_SAFETY_LFSR_SEED_SEED_MASK (0xFFFFFFFFU)
7114 #define CSL_DSS_VID1_SAFETY_LFSR_SEED_SEED_SHIFT (0x00000000U)
7115 #define CSL_DSS_VID1_SAFETY_LFSR_SEED_SEED_MAX (0xFFFFFFFFU)
7116 
7117 /* LUMAKEY */
7118 
7119 #define CSL_DSS_VID1_LUMAKEY_LUMAKEYMIN_MASK (0x00000FFFU)
7120 #define CSL_DSS_VID1_LUMAKEY_LUMAKEYMIN_SHIFT (0x00000000U)
7121 #define CSL_DSS_VID1_LUMAKEY_LUMAKEYMIN_MAX (0x00000FFFU)
7122 
7123 #define CSL_DSS_VID1_LUMAKEY_RESERVED_MASK (0x0000F000U)
7124 #define CSL_DSS_VID1_LUMAKEY_RESERVED_SHIFT (0x0000000CU)
7125 #define CSL_DSS_VID1_LUMAKEY_RESERVED_MAX (0x0000000FU)
7126 
7127 #define CSL_DSS_VID1_LUMAKEY_LUMAKEYMAX_MASK (0x0FFF0000U)
7128 #define CSL_DSS_VID1_LUMAKEY_LUMAKEYMAX_SHIFT (0x00000010U)
7129 #define CSL_DSS_VID1_LUMAKEY_LUMAKEYMAX_MAX (0x00000FFFU)
7130 
7131 #define CSL_DSS_VID1_LUMAKEY_RESERVED1_MASK (0xF0000000U)
7132 #define CSL_DSS_VID1_LUMAKEY_RESERVED1_SHIFT (0x0000001CU)
7133 #define CSL_DSS_VID1_LUMAKEY_RESERVED1_MAX (0x0000000FU)
7134 
7135 /* DMA_BUFSIZE */
7136 
7137 #define CSL_DSS_VID1_DMA_BUFSIZE_BUFSIZE_MASK (0x0000001FU)
7138 #define CSL_DSS_VID1_DMA_BUFSIZE_BUFSIZE_SHIFT (0x00000000U)
7139 #define CSL_DSS_VID1_DMA_BUFSIZE_BUFSIZE_MAX (0x0000001FU)
7140 
7141 #define CSL_DSS_VID1_DMA_BUFSIZE_RESERVED_MASK (0xFFFFFFE0U)
7142 #define CSL_DSS_VID1_DMA_BUFSIZE_RESERVED_SHIFT (0x00000005U)
7143 #define CSL_DSS_VID1_DMA_BUFSIZE_RESERVED_MAX (0x07FFFFFFU)
7144 
7145 /* CROP */
7146 
7147 #define CSL_DSS_VID1_CROP_CROPLEFT_MASK (0x0000001FU)
7148 #define CSL_DSS_VID1_CROP_CROPLEFT_SHIFT (0x00000000U)
7149 #define CSL_DSS_VID1_CROP_CROPLEFT_MAX (0x0000001FU)
7150 
7151 #define CSL_DSS_VID1_CROP_CROPRIGHT_MASK (0x00001F00U)
7152 #define CSL_DSS_VID1_CROP_CROPRIGHT_SHIFT (0x00000008U)
7153 #define CSL_DSS_VID1_CROP_CROPRIGHT_MAX (0x0000001FU)
7154 
7155 #define CSL_DSS_VID1_CROP_CROPTOP_MASK (0x001F0000U)
7156 #define CSL_DSS_VID1_CROP_CROPTOP_SHIFT (0x00000010U)
7157 #define CSL_DSS_VID1_CROP_CROPTOP_MAX (0x0000001FU)
7158 
7159 #define CSL_DSS_VID1_CROP_CROPBOTTOM_MASK (0x1F000000U)
7160 #define CSL_DSS_VID1_CROP_CROPBOTTOM_SHIFT (0x00000018U)
7161 #define CSL_DSS_VID1_CROP_CROPBOTTOM_MAX (0x0000001FU)
7162 
7163 /* SECURE */
7164 
7165 #define CSL_DSS_VID1_SECURE_SECURE_MASK (0x00000001U)
7166 #define CSL_DSS_VID1_SECURE_SECURE_SHIFT (0x00000000U)
7167 #define CSL_DSS_VID1_SECURE_SECURE_MAX (0x00000001U)
7168 
7169 #define CSL_DSS_VID1_SECURE_SECURE_VAL_SECUREDIS (0x0U)
7170 #define CSL_DSS_VID1_SECURE_SECURE_VAL_SECUREEN (0x1U)
7171 
7172 #define CSL_DSS_VID1_SECURE_RESERVED_MASK (0xFFFFFFFEU)
7173 #define CSL_DSS_VID1_SECURE_RESERVED_SHIFT (0x00000001U)
7174 #define CSL_DSS_VID1_SECURE_RESERVED_MAX (0x7FFFFFFFU)
7175 
7176 /* PIPE_GO */
7177 
7178 #define CSL_DSS_VID1_PIPE_GO_GOBIT_MASK (0x00000001U)
7179 #define CSL_DSS_VID1_PIPE_GO_GOBIT_SHIFT (0x00000000U)
7180 #define CSL_DSS_VID1_PIPE_GO_GOBIT_MAX (0x00000001U)
7181 
7182 #define CSL_DSS_VID1_PIPE_GO_GOBIT_VAL_HFUISR (0x0U)
7183 #define CSL_DSS_VID1_PIPE_GO_GOBIT_VAL_UFPSR (0x1U)
7184 
7185 #define CSL_DSS_VID1_PIPE_GO_RESERVED_MASK (0xFFFFFFFEU)
7186 #define CSL_DSS_VID1_PIPE_GO_RESERVED_SHIFT (0x00000001U)
7187 #define CSL_DSS_VID1_PIPE_GO_RESERVED_MAX (0x7FFFFFFFU)
7188 
7189 /**************************************************************************
7190 * Hardware Region : VID2 Registers
7191 **************************************************************************/
7192 
7193 
7194 /**************************************************************************
7195 * Register Overlay Structure
7196 **************************************************************************/
7197 
7198 typedef struct {
7199  volatile uint32_t ACCUH_0; /* ACCUH_0 */
7200  volatile uint32_t ACCUH_1; /* ACCUH_1 */
7201  volatile uint32_t ACCUH2_0; /* ACCUH2_0 */
7202  volatile uint32_t ACCUH2_1; /* ACCUH2_1 */
7203  volatile uint32_t ACCUV_0; /* ACCUV_0 */
7204  volatile uint32_t ACCUV_1; /* ACCUV_1 */
7205  volatile uint32_t ACCUV2_0; /* ACCUV2_0 */
7206  volatile uint32_t ACCUV2_1; /* ACCUV2_1 */
7207  volatile uint32_t ATTRIBUTES; /* ATTRIBUTES */
7208  volatile uint32_t ATTRIBUTES2; /* ATTRIBUTES2 */
7209  volatile uint32_t BA_0; /* BA_0 */
7210  volatile uint32_t BA_1; /* BA_1 */
7211  volatile uint32_t BA_UV_0; /* BA_UV_0 */
7212  volatile uint32_t BA_UV_1; /* BA_UV_1 */
7213  volatile uint32_t BUF_SIZE_STATUS; /* BUF_SIZE_STATUS */
7214  volatile uint32_t BUF_THRESHOLD; /* BUF_THRESHOLD */
7215  volatile uint32_t CSC_COEF0; /* CSC_COEF0 */
7216  volatile uint32_t CSC_COEF1; /* CSC_COEF1 */
7217  volatile uint32_t CSC_COEF2; /* CSC_COEF2 */
7218  volatile uint32_t CSC_COEF3; /* CSC_COEF3 */
7219  volatile uint32_t CSC_COEF4; /* CSC_COEF4 */
7220  volatile uint32_t CSC_COEF5; /* CSC_COEF5 */
7221  volatile uint32_t CSC_COEF6; /* CSC_COEF6 */
7222  volatile uint32_t FIRH; /* FIRH */
7223  volatile uint32_t FIRH2; /* FIRH2 */
7224  volatile uint32_t FIRV; /* FIRV */
7225  volatile uint32_t FIRV2; /* FIRV2 */
7226  volatile uint32_t FIR_COEF_H0[9U]; /* FIR_COEF_H0 0..8 */
7227  volatile uint32_t FIR_COEF_H0_C[9U]; /* FIR_COEF_H0_C 0..8 */
7228  volatile uint32_t FIR_COEF_H12[16U]; /* FIR_COEF_H12 0..15 */
7229  volatile uint32_t FIR_COEF_H12_C[16U]; /* FIR_COEF_H12_C 0..15 */
7230  volatile uint32_t FIR_COEF_V0[9U]; /* FIR_COEF_V0 0..8 */
7231  volatile uint32_t FIR_COEF_V0_C[9U]; /* FIR_COEF_V0_C 0..8 */
7232  volatile uint32_t FIR_COEF_V12[16U]; /* FIR_COEF_V12 0..15 */
7233  volatile uint32_t FIR_COEF_V12_C[16U]; /* FIR_COEF_V12_C 0..15 */
7234  volatile uint32_t GLOBAL_ALPHA; /* GLOBAL_ALPHA */
7235  volatile uint8_t Resv_520[8];
7236  volatile uint32_t MFLAG_THRESHOLD; /* MFLAG_THRESHOLD */
7237  volatile uint32_t PICTURE_SIZE; /* PICTURE_SIZE */
7238  volatile uint32_t PIXEL_INC; /* PIXEL_INC */
7239  volatile uint8_t Resv_536[4];
7240  volatile uint32_t PRELOAD; /* PRELOAD */
7241  volatile uint32_t ROW_INC; /* ROW_INC */
7242  volatile uint32_t SIZE; /* SIZE */
7243  volatile uint8_t Resv_556[8];
7244  volatile uint32_t BA_EXT_0; /* BA_EXT_0 */
7245  volatile uint32_t BA_EXT_1; /* BA_EXT_1 */
7246  volatile uint32_t BA_UV_EXT_0; /* BA_UV_EXT_0 */
7247  volatile uint32_t BA_UV_EXT_1; /* BA_UV_EXT_1 */
7248  volatile uint32_t CSC_COEF7; /* CSC_COEF7 */
7249  volatile uint8_t Resv_584[8];
7250  volatile uint32_t ROW_INC_UV; /* ROW_INC_UV */
7251  volatile uint32_t TILE; /* TILE */
7252  volatile uint32_t TILE2; /* TILE2 */
7253  volatile uint32_t FBDC_ATTRIBUTES; /* FBDC_ATTRIBUTES */
7254  volatile uint32_t FBDC_CLEAR_COLOR; /* FBDC_CLEAR_COLOR */
7255  volatile uint8_t Resv_608[4];
7256  volatile uint32_t CLUT_0; /* CLUT_0 */
7257  volatile uint32_t CLUT_1; /* CLUT_1 */
7258  volatile uint32_t CLUT_2; /* CLUT_2 */
7259  volatile uint32_t CLUT_3; /* CLUT_3 */
7260  volatile uint32_t CLUT_4; /* CLUT_4 */
7261  volatile uint32_t CLUT_5; /* CLUT_5 */
7262  volatile uint32_t CLUT_6; /* CLUT_6 */
7263  volatile uint32_t CLUT_7; /* CLUT_7 */
7264  volatile uint32_t CLUT_8; /* CLUT_8 */
7265  volatile uint32_t CLUT_9; /* CLUT_9 */
7266  volatile uint32_t CLUT_10; /* CLUT_10 */
7267  volatile uint32_t CLUT_11; /* CLUT_11 */
7268  volatile uint32_t CLUT_12; /* CLUT_12 */
7269  volatile uint32_t CLUT_13; /* CLUT_13 */
7270  volatile uint32_t CLUT_14; /* CLUT_14 */
7271  volatile uint32_t CLUT_15; /* CLUT_15 */
7272  volatile uint32_t SAFETY_ATTRIBUTES; /* SAFETY_ATTRIBUTES */
7273  volatile uint32_t SAFETY_CAPT_SIGNATURE; /* SAFETY_CAPT_SIGNATURE */
7274  volatile uint32_t SAFETY_POSITION; /* SAFETY_POSITION */
7275  volatile uint32_t SAFETY_REF_SIGNATURE; /* SAFETY_REF_SIGNATURE */
7276  volatile uint32_t SAFETY_SIZE; /* SAFETY_SIZE */
7277  volatile uint32_t SAFETY_LFSR_SEED; /* SAFETY_LFSR_SEED */
7278  volatile uint32_t LUMAKEY; /* LUMAKEY */
7279  volatile uint32_t DMA_BUFSIZE; /* DMA_BUFSIZE */
7280  volatile uint32_t CROP; /* CROP */
7281  volatile uint32_t SECURE; /* SECURE */
7282  volatile uint32_t PIPE_GO; /* PIPE_GO */
7284 
7285 
7286 /**************************************************************************
7287 * Register Macros
7288 **************************************************************************/
7289 
7290 #define CSL_DSS_VID2_ACCUH_0 (0x00000000U)
7291 #define CSL_DSS_VID2_ACCUH_1 (0x00000004U)
7292 #define CSL_DSS_VID2_ACCUH2_0 (0x00000008U)
7293 #define CSL_DSS_VID2_ACCUH2_1 (0x0000000CU)
7294 #define CSL_DSS_VID2_ACCUV_0 (0x00000010U)
7295 #define CSL_DSS_VID2_ACCUV_1 (0x00000014U)
7296 #define CSL_DSS_VID2_ACCUV2_0 (0x00000018U)
7297 #define CSL_DSS_VID2_ACCUV2_1 (0x0000001CU)
7298 #define CSL_DSS_VID2_ATTRIBUTES (0x00000020U)
7299 #define CSL_DSS_VID2_ATTRIBUTES2 (0x00000024U)
7300 #define CSL_DSS_VID2_BA_0 (0x00000028U)
7301 #define CSL_DSS_VID2_BA_1 (0x0000002CU)
7302 #define CSL_DSS_VID2_BA_UV_0 (0x00000030U)
7303 #define CSL_DSS_VID2_BA_UV_1 (0x00000034U)
7304 #define CSL_DSS_VID2_BUF_SIZE_STATUS (0x00000038U)
7305 #define CSL_DSS_VID2_BUF_THRESHOLD (0x0000003CU)
7306 #define CSL_DSS_VID2_CSC_COEF0 (0x00000040U)
7307 #define CSL_DSS_VID2_CSC_COEF1 (0x00000044U)
7308 #define CSL_DSS_VID2_CSC_COEF2 (0x00000048U)
7309 #define CSL_DSS_VID2_CSC_COEF3 (0x0000004CU)
7310 #define CSL_DSS_VID2_CSC_COEF4 (0x00000050U)
7311 #define CSL_DSS_VID2_CSC_COEF5 (0x00000054U)
7312 #define CSL_DSS_VID2_CSC_COEF6 (0x00000058U)
7313 #define CSL_DSS_VID2_FIRH (0x0000005CU)
7314 #define CSL_DSS_VID2_FIRH2 (0x00000060U)
7315 #define CSL_DSS_VID2_FIRV (0x00000064U)
7316 #define CSL_DSS_VID2_FIRV2 (0x00000068U)
7317 #define CSL_DSS_VID2_FIR_COEF_H0(index) (0x0000006CU+((uint32_t)(index)*0x4U))
7318 #define CSL_DSS_VID2_FIR_COEF_H0_C(index) (0x00000090U+((uint32_t)(index)*0x4U))
7319 #define CSL_DSS_VID2_FIR_COEF_H12(index) (0x000000B4U+((uint32_t)(index)*0x4U))
7320 #define CSL_DSS_VID2_FIR_COEF_H12_C(index) (0x000000F4U+((uint32_t)(index)*0x4U))
7321 #define CSL_DSS_VID2_FIR_COEF_V0(index) (0x00000134U+((uint32_t)(index)*0x4U))
7322 #define CSL_DSS_VID2_FIR_COEF_V0_C(index) (0x00000158U+((uint32_t)(index)*0x4U))
7323 #define CSL_DSS_VID2_FIR_COEF_V12(index) (0x0000017CU+((uint32_t)(index)*0x4U))
7324 #define CSL_DSS_VID2_FIR_COEF_V12_C(index) (0x000001BCU+((uint32_t)(index)*0x4U))
7325 #define CSL_DSS_VID2_GLOBAL_ALPHA (0x000001FCU)
7326 #define CSL_DSS_VID2_MFLAG_THRESHOLD (0x00000208U)
7327 #define CSL_DSS_VID2_PICTURE_SIZE (0x0000020CU)
7328 #define CSL_DSS_VID2_PIXEL_INC (0x00000210U)
7329 #define CSL_DSS_VID2_PRELOAD (0x00000218U)
7330 #define CSL_DSS_VID2_ROW_INC (0x0000021CU)
7331 #define CSL_DSS_VID2_SIZE (0x00000220U)
7332 #define CSL_DSS_VID2_BA_EXT_0 (0x0000022CU)
7333 #define CSL_DSS_VID2_BA_EXT_1 (0x00000230U)
7334 #define CSL_DSS_VID2_BA_UV_EXT_0 (0x00000234U)
7335 #define CSL_DSS_VID2_BA_UV_EXT_1 (0x00000238U)
7336 #define CSL_DSS_VID2_CSC_COEF7 (0x0000023CU)
7337 #define CSL_DSS_VID2_ROW_INC_UV (0x00000248U)
7338 #define CSL_DSS_VID2_TILE (0x0000024CU)
7339 #define CSL_DSS_VID2_TILE2 (0x00000250U)
7340 #define CSL_DSS_VID2_FBDC_ATTRIBUTES (0x00000254U)
7341 #define CSL_DSS_VID2_FBDC_CLEAR_COLOR (0x00000258U)
7342 #define CSL_DSS_VID2_CLUT_0 (0x00000260U)
7343 #define CSL_DSS_VID2_CLUT_1 (0x00000264U)
7344 #define CSL_DSS_VID2_CLUT_2 (0x00000268U)
7345 #define CSL_DSS_VID2_CLUT_3 (0x0000026CU)
7346 #define CSL_DSS_VID2_CLUT_4 (0x00000270U)
7347 #define CSL_DSS_VID2_CLUT_5 (0x00000274U)
7348 #define CSL_DSS_VID2_CLUT_6 (0x00000278U)
7349 #define CSL_DSS_VID2_CLUT_7 (0x0000027CU)
7350 #define CSL_DSS_VID2_CLUT_8 (0x00000280U)
7351 #define CSL_DSS_VID2_CLUT_9 (0x00000284U)
7352 #define CSL_DSS_VID2_CLUT_10 (0x00000288U)
7353 #define CSL_DSS_VID2_CLUT_11 (0x0000028CU)
7354 #define CSL_DSS_VID2_CLUT_12 (0x00000290U)
7355 #define CSL_DSS_VID2_CLUT_13 (0x00000294U)
7356 #define CSL_DSS_VID2_CLUT_14 (0x00000298U)
7357 #define CSL_DSS_VID2_CLUT_15 (0x0000029CU)
7358 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES (0x000002A0U)
7359 #define CSL_DSS_VID2_SAFETY_CAPT_SIGNATURE (0x000002A4U)
7360 #define CSL_DSS_VID2_SAFETY_POSITION (0x000002A8U)
7361 #define CSL_DSS_VID2_SAFETY_REF_SIGNATURE (0x000002ACU)
7362 #define CSL_DSS_VID2_SAFETY_SIZE (0x000002B0U)
7363 #define CSL_DSS_VID2_SAFETY_LFSR_SEED (0x000002B4U)
7364 #define CSL_DSS_VID2_LUMAKEY (0x000002B8U)
7365 #define CSL_DSS_VID2_DMA_BUFSIZE (0x000002BCU)
7366 #define CSL_DSS_VID2_CROP (0x000002C0U)
7367 #define CSL_DSS_VID2_SECURE (0x000002C4U)
7368 #define CSL_DSS_VID2_PIPE_GO (0x000002C8U)
7369 
7370 /**************************************************************************
7371 * Field Definition Macros
7372 **************************************************************************/
7373 
7374 
7375 /* ACCUH_0 */
7376 
7377 #define CSL_DSS_VID2_ACCUH_0_HORIZONTALACCU_MASK (0x00FFFFFFU)
7378 #define CSL_DSS_VID2_ACCUH_0_HORIZONTALACCU_SHIFT (0x00000000U)
7379 #define CSL_DSS_VID2_ACCUH_0_HORIZONTALACCU_MAX (0x00FFFFFFU)
7380 
7381 #define CSL_DSS_VID2_ACCUH_0_RESERVED_MASK (0xFF000000U)
7382 #define CSL_DSS_VID2_ACCUH_0_RESERVED_SHIFT (0x00000018U)
7383 #define CSL_DSS_VID2_ACCUH_0_RESERVED_MAX (0x000000FFU)
7384 
7385 /* ACCUH_1 */
7386 
7387 #define CSL_DSS_VID2_ACCUH_1_HORIZONTALACCU_MASK (0x00FFFFFFU)
7388 #define CSL_DSS_VID2_ACCUH_1_HORIZONTALACCU_SHIFT (0x00000000U)
7389 #define CSL_DSS_VID2_ACCUH_1_HORIZONTALACCU_MAX (0x00FFFFFFU)
7390 
7391 #define CSL_DSS_VID2_ACCUH_1_RESERVED_MASK (0xFF000000U)
7392 #define CSL_DSS_VID2_ACCUH_1_RESERVED_SHIFT (0x00000018U)
7393 #define CSL_DSS_VID2_ACCUH_1_RESERVED_MAX (0x000000FFU)
7394 
7395 /* ACCUH2_0 */
7396 
7397 #define CSL_DSS_VID2_ACCUH2_0_HORIZONTALACCU_MASK (0x00FFFFFFU)
7398 #define CSL_DSS_VID2_ACCUH2_0_HORIZONTALACCU_SHIFT (0x00000000U)
7399 #define CSL_DSS_VID2_ACCUH2_0_HORIZONTALACCU_MAX (0x00FFFFFFU)
7400 
7401 #define CSL_DSS_VID2_ACCUH2_0_RESERVED_MASK (0xFF000000U)
7402 #define CSL_DSS_VID2_ACCUH2_0_RESERVED_SHIFT (0x00000018U)
7403 #define CSL_DSS_VID2_ACCUH2_0_RESERVED_MAX (0x000000FFU)
7404 
7405 /* ACCUH2_1 */
7406 
7407 #define CSL_DSS_VID2_ACCUH2_1_HORIZONTALACCU_MASK (0x00FFFFFFU)
7408 #define CSL_DSS_VID2_ACCUH2_1_HORIZONTALACCU_SHIFT (0x00000000U)
7409 #define CSL_DSS_VID2_ACCUH2_1_HORIZONTALACCU_MAX (0x00FFFFFFU)
7410 
7411 #define CSL_DSS_VID2_ACCUH2_1_RESERVED_MASK (0xFF000000U)
7412 #define CSL_DSS_VID2_ACCUH2_1_RESERVED_SHIFT (0x00000018U)
7413 #define CSL_DSS_VID2_ACCUH2_1_RESERVED_MAX (0x000000FFU)
7414 
7415 /* ACCUV_0 */
7416 
7417 #define CSL_DSS_VID2_ACCUV_0_VERTICALACCU_MASK (0x00FFFFFFU)
7418 #define CSL_DSS_VID2_ACCUV_0_VERTICALACCU_SHIFT (0x00000000U)
7419 #define CSL_DSS_VID2_ACCUV_0_VERTICALACCU_MAX (0x00FFFFFFU)
7420 
7421 #define CSL_DSS_VID2_ACCUV_0_RESERVED_MASK (0xFF000000U)
7422 #define CSL_DSS_VID2_ACCUV_0_RESERVED_SHIFT (0x00000018U)
7423 #define CSL_DSS_VID2_ACCUV_0_RESERVED_MAX (0x000000FFU)
7424 
7425 /* ACCUV_1 */
7426 
7427 #define CSL_DSS_VID2_ACCUV_1_VERTICALACCU_MASK (0x00FFFFFFU)
7428 #define CSL_DSS_VID2_ACCUV_1_VERTICALACCU_SHIFT (0x00000000U)
7429 #define CSL_DSS_VID2_ACCUV_1_VERTICALACCU_MAX (0x00FFFFFFU)
7430 
7431 #define CSL_DSS_VID2_ACCUV_1_RESERVED_MASK (0xFF000000U)
7432 #define CSL_DSS_VID2_ACCUV_1_RESERVED_SHIFT (0x00000018U)
7433 #define CSL_DSS_VID2_ACCUV_1_RESERVED_MAX (0x000000FFU)
7434 
7435 /* ACCUV2_0 */
7436 
7437 #define CSL_DSS_VID2_ACCUV2_0_VERTICALACCU_MASK (0x00FFFFFFU)
7438 #define CSL_DSS_VID2_ACCUV2_0_VERTICALACCU_SHIFT (0x00000000U)
7439 #define CSL_DSS_VID2_ACCUV2_0_VERTICALACCU_MAX (0x00FFFFFFU)
7440 
7441 #define CSL_DSS_VID2_ACCUV2_0_RESERVED_MASK (0xFF000000U)
7442 #define CSL_DSS_VID2_ACCUV2_0_RESERVED_SHIFT (0x00000018U)
7443 #define CSL_DSS_VID2_ACCUV2_0_RESERVED_MAX (0x000000FFU)
7444 
7445 /* ACCUV2_1 */
7446 
7447 #define CSL_DSS_VID2_ACCUV2_1_VERTICALACCU_MASK (0x00FFFFFFU)
7448 #define CSL_DSS_VID2_ACCUV2_1_VERTICALACCU_SHIFT (0x00000000U)
7449 #define CSL_DSS_VID2_ACCUV2_1_VERTICALACCU_MAX (0x00FFFFFFU)
7450 
7451 #define CSL_DSS_VID2_ACCUV2_1_RESERVED_MASK (0xFF000000U)
7452 #define CSL_DSS_VID2_ACCUV2_1_RESERVED_SHIFT (0x00000018U)
7453 #define CSL_DSS_VID2_ACCUV2_1_RESERVED_MAX (0x000000FFU)
7454 
7455 /* ATTRIBUTES */
7456 
7457 #define CSL_DSS_VID2_ATTRIBUTES_ENABLE_MASK (0x00000001U)
7458 #define CSL_DSS_VID2_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
7459 #define CSL_DSS_VID2_ATTRIBUTES_ENABLE_MAX (0x00000001U)
7460 
7461 #define CSL_DSS_VID2_ATTRIBUTES_ENABLE_VAL_VIDEOENB (0x1U)
7462 #define CSL_DSS_VID2_ATTRIBUTES_ENABLE_VAL_VIDEODIS (0x0U)
7463 
7464 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_MASK (0x0000007EU)
7465 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_SHIFT (0x00000001U)
7466 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_MAX (0x0000003FU)
7467 
7468 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_ARGB16_4444 (0x0U)
7469 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_ABGR16_4444 (0x1U)
7470 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_RGBA16_4444 (0x2U)
7471 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_RGB16_565 (0x3U)
7472 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_BGR16_565 (0x4U)
7473 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_ARGB16_1555 (0x5U)
7474 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_ABGR16_1555 (0x6U)
7475 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_ARGB32_8888 (0x7U)
7476 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_ABGR32_8888 (0x8U)
7477 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_RGBA32_8888 (0x9U)
7478 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_BGRA32_8888 (0xAU)
7479 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_RGB24P_888 (0xBU)
7480 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_BGR24P_888 (0xCU)
7481 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_ARGB32_2101010 (0xEU)
7482 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_ABGR32_2101010 (0xFU)
7483 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_ARGB64_16161616 (0x10U)
7484 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_RGBA64_16161616 (0x11U)
7485 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_BITMAP1 (0x12U)
7486 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_BITMAP2 (0x13U)
7487 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_BITMAP4 (0x14U)
7488 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_BITMAP8 (0x15U)
7489 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_RGB565A8 (0x16U)
7490 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_BGR565A8 (0x17U)
7491 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_XRGB16_4444 (0x20U)
7492 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_XBGR16_4444 (0x21U)
7493 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_RGBX16_4444 (0x22U)
7494 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_XRGB16_1555 (0x25U)
7495 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_XBGR16_1555 (0x26U)
7496 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_XRGB32_8888 (0x27U)
7497 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_XBGR32_8888 (0x28U)
7498 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_RGBX32_8888 (0x29U)
7499 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_BGRX32_8888 (0x2AU)
7500 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_XRGB32_2101010 (0x2EU)
7501 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_XBGR32_2101010 (0x2FU)
7502 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_XRGB64_16161616 (0x30U)
7503 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_RGBX64_16161616 (0x31U)
7504 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_YUV422_NV12 (0x3CU)
7505 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_YUV420_NV12 (0x3DU)
7506 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_YUV422_YUV2 (0x3EU)
7507 #define CSL_DSS_VID2_ATTRIBUTES_FORMAT_VAL_YUV422_UYVY (0x3FU)
7508 
7509 #define CSL_DSS_VID2_ATTRIBUTES_RESIZEENABLE_MASK (0x00000180U)
7510 #define CSL_DSS_VID2_ATTRIBUTES_RESIZEENABLE_SHIFT (0x00000007U)
7511 #define CSL_DSS_VID2_ATTRIBUTES_RESIZEENABLE_MAX (0x00000003U)
7512 
7513 #define CSL_DSS_VID2_ATTRIBUTES_RESIZEENABLE_VAL_RESIZEPROC (0x0U)
7514 #define CSL_DSS_VID2_ATTRIBUTES_RESIZEENABLE_VAL_HRESIZE (0x1U)
7515 #define CSL_DSS_VID2_ATTRIBUTES_RESIZEENABLE_VAL_VRESIZE (0x2U)
7516 #define CSL_DSS_VID2_ATTRIBUTES_RESIZEENABLE_VAL_HVRESIZE (0x3U)
7517 
7518 #define CSL_DSS_VID2_ATTRIBUTES_COLORCONVENABLE_MASK (0x00000200U)
7519 #define CSL_DSS_VID2_ATTRIBUTES_COLORCONVENABLE_SHIFT (0x00000009U)
7520 #define CSL_DSS_VID2_ATTRIBUTES_COLORCONVENABLE_MAX (0x00000001U)
7521 
7522 #define CSL_DSS_VID2_ATTRIBUTES_COLORCONVENABLE_VAL_COLSPCENB (0x1U)
7523 #define CSL_DSS_VID2_ATTRIBUTES_COLORCONVENABLE_VAL_COLSPCDIS (0x0U)
7524 
7525 #define CSL_DSS_VID2_ATTRIBUTES_NIBBLEMODE_MASK (0x00000400U)
7526 #define CSL_DSS_VID2_ATTRIBUTES_NIBBLEMODE_SHIFT (0x0000000AU)
7527 #define CSL_DSS_VID2_ATTRIBUTES_NIBBLEMODE_MAX (0x00000001U)
7528 
7529 #define CSL_DSS_VID2_ATTRIBUTES_NIBBLEMODE_VAL_NIBBLEMODEEN (0x1U)
7530 #define CSL_DSS_VID2_ATTRIBUTES_NIBBLEMODE_VAL_NIBBLEMODEDIS (0x0U)
7531 
7532 #define CSL_DSS_VID2_ATTRIBUTES_FULLRANGE_MASK (0x00000800U)
7533 #define CSL_DSS_VID2_ATTRIBUTES_FULLRANGE_SHIFT (0x0000000BU)
7534 #define CSL_DSS_VID2_ATTRIBUTES_FULLRANGE_MAX (0x00000001U)
7535 
7536 #define CSL_DSS_VID2_ATTRIBUTES_FULLRANGE_VAL_FULLRANGE (0x1U)
7537 #define CSL_DSS_VID2_ATTRIBUTES_FULLRANGE_VAL_LIMRANGE (0x0U)
7538 
7539 #define CSL_DSS_VID2_ATTRIBUTES_FLIP_MASK (0x00001000U)
7540 #define CSL_DSS_VID2_ATTRIBUTES_FLIP_SHIFT (0x0000000CU)
7541 #define CSL_DSS_VID2_ATTRIBUTES_FLIP_MAX (0x00000001U)
7542 
7543 #define CSL_DSS_VID2_ATTRIBUTES_FLIP_VAL_FLIP (0x1U)
7544 #define CSL_DSS_VID2_ATTRIBUTES_FLIP_VAL_NOFLIP (0x0U)
7545 
7546 #define CSL_DSS_VID2_ATTRIBUTES_CROP_MASK (0x00002000U)
7547 #define CSL_DSS_VID2_ATTRIBUTES_CROP_SHIFT (0x0000000DU)
7548 #define CSL_DSS_VID2_ATTRIBUTES_CROP_MAX (0x00000001U)
7549 
7550 #define CSL_DSS_VID2_ATTRIBUTES_CROP_VAL_CROPEN (0x1U)
7551 #define CSL_DSS_VID2_ATTRIBUTES_CROP_VAL_CROPDIS (0x0U)
7552 
7553 #define CSL_DSS_VID2_ATTRIBUTES_RESERVED9_MASK (0x0001C000U)
7554 #define CSL_DSS_VID2_ATTRIBUTES_RESERVED9_SHIFT (0x0000000EU)
7555 #define CSL_DSS_VID2_ATTRIBUTES_RESERVED9_MAX (0x00000007U)
7556 
7557 #define CSL_DSS_VID2_ATTRIBUTES_SELFREFRESHAUTO_MASK (0x00020000U)
7558 #define CSL_DSS_VID2_ATTRIBUTES_SELFREFRESHAUTO_SHIFT (0x00000011U)
7559 #define CSL_DSS_VID2_ATTRIBUTES_SELFREFRESHAUTO_MAX (0x00000001U)
7560 
7561 #define CSL_DSS_VID2_ATTRIBUTES_SELFREFRESHAUTO_VAL_SELFREFRESHAUTOEN (0x1U)
7562 #define CSL_DSS_VID2_ATTRIBUTES_SELFREFRESHAUTO_VAL_SELFREFRESHAUTODIS (0x0U)
7563 
7564 #define CSL_DSS_VID2_ATTRIBUTES_RESERVED7_MASK (0x00040000U)
7565 #define CSL_DSS_VID2_ATTRIBUTES_RESERVED7_SHIFT (0x00000012U)
7566 #define CSL_DSS_VID2_ATTRIBUTES_RESERVED7_MAX (0x00000001U)
7567 
7568 #define CSL_DSS_VID2_ATTRIBUTES_BUFPRELOAD_MASK (0x00080000U)
7569 #define CSL_DSS_VID2_ATTRIBUTES_BUFPRELOAD_SHIFT (0x00000013U)
7570 #define CSL_DSS_VID2_ATTRIBUTES_BUFPRELOAD_MAX (0x00000001U)
7571 
7572 #define CSL_DSS_VID2_ATTRIBUTES_BUFPRELOAD_VAL_HIGHTHRES (0x1U)
7573 #define CSL_DSS_VID2_ATTRIBUTES_BUFPRELOAD_VAL_DEFVAL (0x0U)
7574 
7575 #define CSL_DSS_VID2_ATTRIBUTES_RESERVED2_MASK (0x00100000U)
7576 #define CSL_DSS_VID2_ATTRIBUTES_RESERVED2_SHIFT (0x00000014U)
7577 #define CSL_DSS_VID2_ATTRIBUTES_RESERVED2_MAX (0x00000001U)
7578 
7579 #define CSL_DSS_VID2_ATTRIBUTES_VERTICALTAPS_MASK (0x00200000U)
7580 #define CSL_DSS_VID2_ATTRIBUTES_VERTICALTAPS_SHIFT (0x00000015U)
7581 #define CSL_DSS_VID2_ATTRIBUTES_VERTICALTAPS_MAX (0x00000001U)
7582 
7583 #define CSL_DSS_VID2_ATTRIBUTES_VERTICALTAPS_VAL_TAPS5 (0x1U)
7584 #define CSL_DSS_VID2_ATTRIBUTES_VERTICALTAPS_VAL_TAPS3 (0x0U)
7585 
7586 #define CSL_DSS_VID2_ATTRIBUTES_RESERVED6_MASK (0x00400000U)
7587 #define CSL_DSS_VID2_ATTRIBUTES_RESERVED6_SHIFT (0x00000016U)
7588 #define CSL_DSS_VID2_ATTRIBUTES_RESERVED6_MAX (0x00000001U)
7589 
7590 #define CSL_DSS_VID2_ATTRIBUTES_ARBITRATION_MASK (0x00800000U)
7591 #define CSL_DSS_VID2_ATTRIBUTES_ARBITRATION_SHIFT (0x00000017U)
7592 #define CSL_DSS_VID2_ATTRIBUTES_ARBITRATION_MAX (0x00000001U)
7593 
7594 #define CSL_DSS_VID2_ATTRIBUTES_ARBITRATION_VAL_HIGHPRIO (0x1U)
7595 #define CSL_DSS_VID2_ATTRIBUTES_ARBITRATION_VAL_NORMALPRIO (0x0U)
7596 
7597 #define CSL_DSS_VID2_ATTRIBUTES_SELFREFRESH_MASK (0x01000000U)
7598 #define CSL_DSS_VID2_ATTRIBUTES_SELFREFRESH_SHIFT (0x00000018U)
7599 #define CSL_DSS_VID2_ATTRIBUTES_SELFREFRESH_MAX (0x00000001U)
7600 
7601 #define CSL_DSS_VID2_ATTRIBUTES_SELFREFRESH_VAL_SELFREFRESHENB (0x1U)
7602 #define CSL_DSS_VID2_ATTRIBUTES_SELFREFRESH_VAL_SELFREFRESHDIS (0x0U)
7603 
7604 #define CSL_DSS_VID2_ATTRIBUTES_RESERVED5_MASK (0x0E000000U)
7605 #define CSL_DSS_VID2_ATTRIBUTES_RESERVED5_SHIFT (0x00000019U)
7606 #define CSL_DSS_VID2_ATTRIBUTES_RESERVED5_MAX (0x00000007U)
7607 
7608 #define CSL_DSS_VID2_ATTRIBUTES_PREMULTIPLYALPHA_MASK (0x10000000U)
7609 #define CSL_DSS_VID2_ATTRIBUTES_PREMULTIPLYALPHA_SHIFT (0x0000001CU)
7610 #define CSL_DSS_VID2_ATTRIBUTES_PREMULTIPLYALPHA_MAX (0x00000001U)
7611 
7612 #define CSL_DSS_VID2_ATTRIBUTES_PREMULTIPLYALPHA_VAL_PREMULTIPLIEDALPHA (0x1U)
7613 #define CSL_DSS_VID2_ATTRIBUTES_PREMULTIPLYALPHA_VAL_NONPREMULTIPLIEDALPHA (0x0U)
7614 
7615 #define CSL_DSS_VID2_ATTRIBUTES_GAMMAINVERSIONPOS_MASK (0x20000000U)
7616 #define CSL_DSS_VID2_ATTRIBUTES_GAMMAINVERSIONPOS_SHIFT (0x0000001DU)
7617 #define CSL_DSS_VID2_ATTRIBUTES_GAMMAINVERSIONPOS_MAX (0x00000001U)
7618 
7619 #define CSL_DSS_VID2_ATTRIBUTES_GAMMAINVERSIONPOS_VAL_PRESCALER (0x0U)
7620 #define CSL_DSS_VID2_ATTRIBUTES_GAMMAINVERSIONPOS_VAL_POSTSCALER (0x1U)
7621 
7622 #define CSL_DSS_VID2_ATTRIBUTES_GAMMAINVERSION_MASK (0x40000000U)
7623 #define CSL_DSS_VID2_ATTRIBUTES_GAMMAINVERSION_SHIFT (0x0000001EU)
7624 #define CSL_DSS_VID2_ATTRIBUTES_GAMMAINVERSION_MAX (0x00000001U)
7625 
7626 #define CSL_DSS_VID2_ATTRIBUTES_GAMMAINVERSION_VAL_INVGAMMAEN (0x1U)
7627 #define CSL_DSS_VID2_ATTRIBUTES_GAMMAINVERSION_VAL_INVGAMMADIS (0x0U)
7628 
7629 #define CSL_DSS_VID2_ATTRIBUTES_LUMAKEYENABLE_MASK (0x80000000U)
7630 #define CSL_DSS_VID2_ATTRIBUTES_LUMAKEYENABLE_SHIFT (0x0000001FU)
7631 #define CSL_DSS_VID2_ATTRIBUTES_LUMAKEYENABLE_MAX (0x00000001U)
7632 
7633 #define CSL_DSS_VID2_ATTRIBUTES_LUMAKEYENABLE_VAL_LUMAKEYEN (0x1U)
7634 #define CSL_DSS_VID2_ATTRIBUTES_LUMAKEYENABLE_VAL_LUMAKEYDIS (0x0U)
7635 
7636 /* ATTRIBUTES2 */
7637 
7638 #define CSL_DSS_VID2_ATTRIBUTES2_VC1ENABLE_MASK (0x00000001U)
7639 #define CSL_DSS_VID2_ATTRIBUTES2_VC1ENABLE_SHIFT (0x00000000U)
7640 #define CSL_DSS_VID2_ATTRIBUTES2_VC1ENABLE_MAX (0x00000001U)
7641 
7642 #define CSL_DSS_VID2_ATTRIBUTES2_VC1ENABLE_VAL_VC1ENB (0x1U)
7643 #define CSL_DSS_VID2_ATTRIBUTES2_VC1ENABLE_VAL_VC1DIS (0x0U)
7644 
7645 #define CSL_DSS_VID2_ATTRIBUTES2_VC1_RANGE_Y_MASK (0x0000000EU)
7646 #define CSL_DSS_VID2_ATTRIBUTES2_VC1_RANGE_Y_SHIFT (0x00000001U)
7647 #define CSL_DSS_VID2_ATTRIBUTES2_VC1_RANGE_Y_MAX (0x00000007U)
7648 
7649 #define CSL_DSS_VID2_ATTRIBUTES2_VC1_RANGE_CBCR_MASK (0x00000070U)
7650 #define CSL_DSS_VID2_ATTRIBUTES2_VC1_RANGE_CBCR_SHIFT (0x00000004U)
7651 #define CSL_DSS_VID2_ATTRIBUTES2_VC1_RANGE_CBCR_MAX (0x00000007U)
7652 
7653 #define CSL_DSS_VID2_ATTRIBUTES2_YUV_SIZE_MASK (0x00000180U)
7654 #define CSL_DSS_VID2_ATTRIBUTES2_YUV_SIZE_SHIFT (0x00000007U)
7655 #define CSL_DSS_VID2_ATTRIBUTES2_YUV_SIZE_MAX (0x00000003U)
7656 
7657 #define CSL_DSS_VID2_ATTRIBUTES2_YUV_SIZE_VAL_8B (0x0U)
7658 #define CSL_DSS_VID2_ATTRIBUTES2_YUV_SIZE_VAL_10B (0x1U)
7659 #define CSL_DSS_VID2_ATTRIBUTES2_YUV_SIZE_VAL_12B (0x2U)
7660 
7661 #define CSL_DSS_VID2_ATTRIBUTES2_YUV_MODE_MASK (0x00000200U)
7662 #define CSL_DSS_VID2_ATTRIBUTES2_YUV_MODE_SHIFT (0x00000009U)
7663 #define CSL_DSS_VID2_ATTRIBUTES2_YUV_MODE_MAX (0x00000001U)
7664 
7665 #define CSL_DSS_VID2_ATTRIBUTES2_YUV_MODE_VAL_PACKED (0x0U)
7666 #define CSL_DSS_VID2_ATTRIBUTES2_YUV_MODE_VAL_UNPACKED (0x1U)
7667 
7668 #define CSL_DSS_VID2_ATTRIBUTES2_YUV_ALIGN_MASK (0x00000400U)
7669 #define CSL_DSS_VID2_ATTRIBUTES2_YUV_ALIGN_SHIFT (0x0000000AU)
7670 #define CSL_DSS_VID2_ATTRIBUTES2_YUV_ALIGN_MAX (0x00000001U)
7671 
7672 #define CSL_DSS_VID2_ATTRIBUTES2_YUV_ALIGN_VAL_MSB (0x1U)
7673 #define CSL_DSS_VID2_ATTRIBUTES2_YUV_ALIGN_VAL_LSB (0x0U)
7674 
7675 #define CSL_DSS_VID2_ATTRIBUTES2_RESERVED1_MASK (0x0000F800U)
7676 #define CSL_DSS_VID2_ATTRIBUTES2_RESERVED1_SHIFT (0x0000000BU)
7677 #define CSL_DSS_VID2_ATTRIBUTES2_RESERVED1_MAX (0x0000001FU)
7678 
7679 #define CSL_DSS_VID2_ATTRIBUTES2_RESERVED2_MASK (0x01F00000U)
7680 #define CSL_DSS_VID2_ATTRIBUTES2_RESERVED2_SHIFT (0x00000014U)
7681 #define CSL_DSS_VID2_ATTRIBUTES2_RESERVED2_MAX (0x0000001FU)
7682 
7683 #define CSL_DSS_VID2_ATTRIBUTES2_MPORTSEL_MASK (0x02000000U)
7684 #define CSL_DSS_VID2_ATTRIBUTES2_MPORTSEL_SHIFT (0x00000019U)
7685 #define CSL_DSS_VID2_ATTRIBUTES2_MPORTSEL_MAX (0x00000001U)
7686 
7687 #define CSL_DSS_VID2_ATTRIBUTES2_MPORTSEL_VAL_PRIMARY (0x0U)
7688 #define CSL_DSS_VID2_ATTRIBUTES2_MPORTSEL_VAL_SECONDARY (0x1U)
7689 
7690 #define CSL_DSS_VID2_ATTRIBUTES2_TAGS_MASK (0x7C000000U)
7691 #define CSL_DSS_VID2_ATTRIBUTES2_TAGS_SHIFT (0x0000001AU)
7692 #define CSL_DSS_VID2_ATTRIBUTES2_TAGS_MAX (0x0000001FU)
7693 
7694 #define CSL_DSS_VID2_ATTRIBUTES2_RESERVED3_MASK (0x80000000U)
7695 #define CSL_DSS_VID2_ATTRIBUTES2_RESERVED3_SHIFT (0x0000001FU)
7696 #define CSL_DSS_VID2_ATTRIBUTES2_RESERVED3_MAX (0x00000001U)
7697 
7698 /* BA_0 */
7699 
7700 #define CSL_DSS_VID2_BA_0_BA_MASK (0xFFFFFFFFU)
7701 #define CSL_DSS_VID2_BA_0_BA_SHIFT (0x00000000U)
7702 #define CSL_DSS_VID2_BA_0_BA_MAX (0xFFFFFFFFU)
7703 
7704 /* BA_1 */
7705 
7706 #define CSL_DSS_VID2_BA_1_BA_MASK (0xFFFFFFFFU)
7707 #define CSL_DSS_VID2_BA_1_BA_SHIFT (0x00000000U)
7708 #define CSL_DSS_VID2_BA_1_BA_MAX (0xFFFFFFFFU)
7709 
7710 /* BA_UV_0 */
7711 
7712 #define CSL_DSS_VID2_BA_UV_0_BA_MASK (0xFFFFFFFFU)
7713 #define CSL_DSS_VID2_BA_UV_0_BA_SHIFT (0x00000000U)
7714 #define CSL_DSS_VID2_BA_UV_0_BA_MAX (0xFFFFFFFFU)
7715 
7716 /* BA_UV_1 */
7717 
7718 #define CSL_DSS_VID2_BA_UV_1_BA_MASK (0xFFFFFFFFU)
7719 #define CSL_DSS_VID2_BA_UV_1_BA_SHIFT (0x00000000U)
7720 #define CSL_DSS_VID2_BA_UV_1_BA_MAX (0xFFFFFFFFU)
7721 
7722 /* BUF_SIZE_STATUS */
7723 
7724 #define CSL_DSS_VID2_BUF_SIZE_STATUS_BUFSIZE_MASK (0x0000FFFFU)
7725 #define CSL_DSS_VID2_BUF_SIZE_STATUS_BUFSIZE_SHIFT (0x00000000U)
7726 #define CSL_DSS_VID2_BUF_SIZE_STATUS_BUFSIZE_MAX (0x0000FFFFU)
7727 
7728 #define CSL_DSS_VID2_BUF_SIZE_STATUS_RESERVED_61_MASK (0xFFFF0000U)
7729 #define CSL_DSS_VID2_BUF_SIZE_STATUS_RESERVED_61_SHIFT (0x00000010U)
7730 #define CSL_DSS_VID2_BUF_SIZE_STATUS_RESERVED_61_MAX (0x0000FFFFU)
7731 
7732 /* BUF_THRESHOLD */
7733 
7734 #define CSL_DSS_VID2_BUF_THRESHOLD_BUFLOWTHRESHOLD_MASK (0x0000FFFFU)
7735 #define CSL_DSS_VID2_BUF_THRESHOLD_BUFLOWTHRESHOLD_SHIFT (0x00000000U)
7736 #define CSL_DSS_VID2_BUF_THRESHOLD_BUFLOWTHRESHOLD_MAX (0x0000FFFFU)
7737 
7738 #define CSL_DSS_VID2_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MASK (0xFFFF0000U)
7739 #define CSL_DSS_VID2_BUF_THRESHOLD_BUFHIGHTHRESHOLD_SHIFT (0x00000010U)
7740 #define CSL_DSS_VID2_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MAX (0x0000FFFFU)
7741 
7742 /* CSC_COEF0 */
7743 
7744 #define CSL_DSS_VID2_CSC_COEF0_C00_MASK (0x000007FFU)
7745 #define CSL_DSS_VID2_CSC_COEF0_C00_SHIFT (0x00000000U)
7746 #define CSL_DSS_VID2_CSC_COEF0_C00_MAX (0x000007FFU)
7747 
7748 #define CSL_DSS_VID2_CSC_COEF0_RESERVED_53_MASK (0x0000F800U)
7749 #define CSL_DSS_VID2_CSC_COEF0_RESERVED_53_SHIFT (0x0000000BU)
7750 #define CSL_DSS_VID2_CSC_COEF0_RESERVED_53_MAX (0x0000001FU)
7751 
7752 #define CSL_DSS_VID2_CSC_COEF0_C01_MASK (0x07FF0000U)
7753 #define CSL_DSS_VID2_CSC_COEF0_C01_SHIFT (0x00000010U)
7754 #define CSL_DSS_VID2_CSC_COEF0_C01_MAX (0x000007FFU)
7755 
7756 #define CSL_DSS_VID2_CSC_COEF0_RESERVED_52_MASK (0xF8000000U)
7757 #define CSL_DSS_VID2_CSC_COEF0_RESERVED_52_SHIFT (0x0000001BU)
7758 #define CSL_DSS_VID2_CSC_COEF0_RESERVED_52_MAX (0x0000001FU)
7759 
7760 /* CSC_COEF1 */
7761 
7762 #define CSL_DSS_VID2_CSC_COEF1_C02_MASK (0x000007FFU)
7763 #define CSL_DSS_VID2_CSC_COEF1_C02_SHIFT (0x00000000U)
7764 #define CSL_DSS_VID2_CSC_COEF1_C02_MAX (0x000007FFU)
7765 
7766 #define CSL_DSS_VID2_CSC_COEF1_RESERVED_55_MASK (0x0000F800U)
7767 #define CSL_DSS_VID2_CSC_COEF1_RESERVED_55_SHIFT (0x0000000BU)
7768 #define CSL_DSS_VID2_CSC_COEF1_RESERVED_55_MAX (0x0000001FU)
7769 
7770 #define CSL_DSS_VID2_CSC_COEF1_C10_MASK (0x07FF0000U)
7771 #define CSL_DSS_VID2_CSC_COEF1_C10_SHIFT (0x00000010U)
7772 #define CSL_DSS_VID2_CSC_COEF1_C10_MAX (0x000007FFU)
7773 
7774 #define CSL_DSS_VID2_CSC_COEF1_RESERVED_54_MASK (0xF8000000U)
7775 #define CSL_DSS_VID2_CSC_COEF1_RESERVED_54_SHIFT (0x0000001BU)
7776 #define CSL_DSS_VID2_CSC_COEF1_RESERVED_54_MAX (0x0000001FU)
7777 
7778 /* CSC_COEF2 */
7779 
7780 #define CSL_DSS_VID2_CSC_COEF2_C11_MASK (0x000007FFU)
7781 #define CSL_DSS_VID2_CSC_COEF2_C11_SHIFT (0x00000000U)
7782 #define CSL_DSS_VID2_CSC_COEF2_C11_MAX (0x000007FFU)
7783 
7784 #define CSL_DSS_VID2_CSC_COEF2_RESERVED_57_MASK (0x0000F800U)
7785 #define CSL_DSS_VID2_CSC_COEF2_RESERVED_57_SHIFT (0x0000000BU)
7786 #define CSL_DSS_VID2_CSC_COEF2_RESERVED_57_MAX (0x0000001FU)
7787 
7788 #define CSL_DSS_VID2_CSC_COEF2_C12_MASK (0x07FF0000U)
7789 #define CSL_DSS_VID2_CSC_COEF2_C12_SHIFT (0x00000010U)
7790 #define CSL_DSS_VID2_CSC_COEF2_C12_MAX (0x000007FFU)
7791 
7792 #define CSL_DSS_VID2_CSC_COEF2_RESERVED_56_MASK (0xF8000000U)
7793 #define CSL_DSS_VID2_CSC_COEF2_RESERVED_56_SHIFT (0x0000001BU)
7794 #define CSL_DSS_VID2_CSC_COEF2_RESERVED_56_MAX (0x0000001FU)
7795 
7796 /* CSC_COEF3 */
7797 
7798 #define CSL_DSS_VID2_CSC_COEF3_C20_MASK (0x000007FFU)
7799 #define CSL_DSS_VID2_CSC_COEF3_C20_SHIFT (0x00000000U)
7800 #define CSL_DSS_VID2_CSC_COEF3_C20_MAX (0x000007FFU)
7801 
7802 #define CSL_DSS_VID2_CSC_COEF3_RESERVED_59_MASK (0x0000F800U)
7803 #define CSL_DSS_VID2_CSC_COEF3_RESERVED_59_SHIFT (0x0000000BU)
7804 #define CSL_DSS_VID2_CSC_COEF3_RESERVED_59_MAX (0x0000001FU)
7805 
7806 #define CSL_DSS_VID2_CSC_COEF3_C21_MASK (0x07FF0000U)
7807 #define CSL_DSS_VID2_CSC_COEF3_C21_SHIFT (0x00000010U)
7808 #define CSL_DSS_VID2_CSC_COEF3_C21_MAX (0x000007FFU)
7809 
7810 #define CSL_DSS_VID2_CSC_COEF3_RESERVED_58_MASK (0xF8000000U)
7811 #define CSL_DSS_VID2_CSC_COEF3_RESERVED_58_SHIFT (0x0000001BU)
7812 #define CSL_DSS_VID2_CSC_COEF3_RESERVED_58_MAX (0x0000001FU)
7813 
7814 /* CSC_COEF4 */
7815 
7816 #define CSL_DSS_VID2_CSC_COEF4_C22_MASK (0x000007FFU)
7817 #define CSL_DSS_VID2_CSC_COEF4_C22_SHIFT (0x00000000U)
7818 #define CSL_DSS_VID2_CSC_COEF4_C22_MAX (0x000007FFU)
7819 
7820 #define CSL_DSS_VID2_CSC_COEF4_RESERVED_60_MASK (0xFFFFF800U)
7821 #define CSL_DSS_VID2_CSC_COEF4_RESERVED_60_SHIFT (0x0000000BU)
7822 #define CSL_DSS_VID2_CSC_COEF4_RESERVED_60_MAX (0x001FFFFFU)
7823 
7824 /* CSC_COEF5 */
7825 
7826 #define CSL_DSS_VID2_CSC_COEF5_RESERVED_MASK (0x00000007U)
7827 #define CSL_DSS_VID2_CSC_COEF5_RESERVED_SHIFT (0x00000000U)
7828 #define CSL_DSS_VID2_CSC_COEF5_RESERVED_MAX (0x00000007U)
7829 
7830 #define CSL_DSS_VID2_CSC_COEF5_PREOFFSET1_MASK (0x0000FFF8U)
7831 #define CSL_DSS_VID2_CSC_COEF5_PREOFFSET1_SHIFT (0x00000003U)
7832 #define CSL_DSS_VID2_CSC_COEF5_PREOFFSET1_MAX (0x00001FFFU)
7833 
7834 #define CSL_DSS_VID2_CSC_COEF5_RESERVED1_MASK (0x00070000U)
7835 #define CSL_DSS_VID2_CSC_COEF5_RESERVED1_SHIFT (0x00000010U)
7836 #define CSL_DSS_VID2_CSC_COEF5_RESERVED1_MAX (0x00000007U)
7837 
7838 #define CSL_DSS_VID2_CSC_COEF5_PREOFFSET2_MASK (0xFFF80000U)
7839 #define CSL_DSS_VID2_CSC_COEF5_PREOFFSET2_SHIFT (0x00000013U)
7840 #define CSL_DSS_VID2_CSC_COEF5_PREOFFSET2_MAX (0x00001FFFU)
7841 
7842 /* CSC_COEF6 */
7843 
7844 #define CSL_DSS_VID2_CSC_COEF6_RESERVED_MASK (0x00000007U)
7845 #define CSL_DSS_VID2_CSC_COEF6_RESERVED_SHIFT (0x00000000U)
7846 #define CSL_DSS_VID2_CSC_COEF6_RESERVED_MAX (0x00000007U)
7847 
7848 #define CSL_DSS_VID2_CSC_COEF6_PREOFFSET3_MASK (0x0000FFF8U)
7849 #define CSL_DSS_VID2_CSC_COEF6_PREOFFSET3_SHIFT (0x00000003U)
7850 #define CSL_DSS_VID2_CSC_COEF6_PREOFFSET3_MAX (0x00001FFFU)
7851 
7852 #define CSL_DSS_VID2_CSC_COEF6_RESERVED1_MASK (0x00070000U)
7853 #define CSL_DSS_VID2_CSC_COEF6_RESERVED1_SHIFT (0x00000010U)
7854 #define CSL_DSS_VID2_CSC_COEF6_RESERVED1_MAX (0x00000007U)
7855 
7856 #define CSL_DSS_VID2_CSC_COEF6_POSTOFFSET1_MASK (0xFFF80000U)
7857 #define CSL_DSS_VID2_CSC_COEF6_POSTOFFSET1_SHIFT (0x00000013U)
7858 #define CSL_DSS_VID2_CSC_COEF6_POSTOFFSET1_MAX (0x00001FFFU)
7859 
7860 /* FIRH */
7861 
7862 #define CSL_DSS_VID2_FIRH_FIRHINC_MASK (0x00FFFFFFU)
7863 #define CSL_DSS_VID2_FIRH_FIRHINC_SHIFT (0x00000000U)
7864 #define CSL_DSS_VID2_FIRH_FIRHINC_MAX (0x00FFFFFFU)
7865 
7866 #define CSL_DSS_VID2_FIRH_RESERVED_MASK (0xFF000000U)
7867 #define CSL_DSS_VID2_FIRH_RESERVED_SHIFT (0x00000018U)
7868 #define CSL_DSS_VID2_FIRH_RESERVED_MAX (0x000000FFU)
7869 
7870 /* FIRH2 */
7871 
7872 #define CSL_DSS_VID2_FIRH2_FIRHINC_MASK (0x00FFFFFFU)
7873 #define CSL_DSS_VID2_FIRH2_FIRHINC_SHIFT (0x00000000U)
7874 #define CSL_DSS_VID2_FIRH2_FIRHINC_MAX (0x00FFFFFFU)
7875 
7876 #define CSL_DSS_VID2_FIRH2_RESERVED_MASK (0xFF000000U)
7877 #define CSL_DSS_VID2_FIRH2_RESERVED_SHIFT (0x00000018U)
7878 #define CSL_DSS_VID2_FIRH2_RESERVED_MAX (0x000000FFU)
7879 
7880 /* FIRV */
7881 
7882 #define CSL_DSS_VID2_FIRV_FIRVINC_MASK (0x00FFFFFFU)
7883 #define CSL_DSS_VID2_FIRV_FIRVINC_SHIFT (0x00000000U)
7884 #define CSL_DSS_VID2_FIRV_FIRVINC_MAX (0x00FFFFFFU)
7885 
7886 #define CSL_DSS_VID2_FIRV_RESERVED_MASK (0xFF000000U)
7887 #define CSL_DSS_VID2_FIRV_RESERVED_SHIFT (0x00000018U)
7888 #define CSL_DSS_VID2_FIRV_RESERVED_MAX (0x000000FFU)
7889 
7890 /* FIRV2 */
7891 
7892 #define CSL_DSS_VID2_FIRV2_FIRVINC_MASK (0x00FFFFFFU)
7893 #define CSL_DSS_VID2_FIRV2_FIRVINC_SHIFT (0x00000000U)
7894 #define CSL_DSS_VID2_FIRV2_FIRVINC_MAX (0x00FFFFFFU)
7895 
7896 #define CSL_DSS_VID2_FIRV2_RESERVED_MASK (0xFF000000U)
7897 #define CSL_DSS_VID2_FIRV2_RESERVED_SHIFT (0x00000018U)
7898 #define CSL_DSS_VID2_FIRV2_RESERVED_MAX (0x000000FFU)
7899 
7900 /* FIR_COEF_H0 */
7901 
7902 #define CSL_DSS_VID2_FIR_COEF_H0_FIRHC0_MASK (0x000003FFU)
7903 #define CSL_DSS_VID2_FIR_COEF_H0_FIRHC0_SHIFT (0x00000000U)
7904 #define CSL_DSS_VID2_FIR_COEF_H0_FIRHC0_MAX (0x000003FFU)
7905 
7906 #define CSL_DSS_VID2_FIR_COEF_H0_RESERVED1_MASK (0x3FFFFC00U)
7907 #define CSL_DSS_VID2_FIR_COEF_H0_RESERVED1_SHIFT (0x0000000AU)
7908 #define CSL_DSS_VID2_FIR_COEF_H0_RESERVED1_MAX (0x000FFFFFU)
7909 
7910 #define CSL_DSS_VID2_FIR_COEF_H0_RESERVED_MASK (0xC0000000U)
7911 #define CSL_DSS_VID2_FIR_COEF_H0_RESERVED_SHIFT (0x0000001EU)
7912 #define CSL_DSS_VID2_FIR_COEF_H0_RESERVED_MAX (0x00000003U)
7913 
7914 /* FIR_COEF_H0_C */
7915 
7916 #define CSL_DSS_VID2_FIR_COEF_H0_C_FIRHC0_MASK (0x000003FFU)
7917 #define CSL_DSS_VID2_FIR_COEF_H0_C_FIRHC0_SHIFT (0x00000000U)
7918 #define CSL_DSS_VID2_FIR_COEF_H0_C_FIRHC0_MAX (0x000003FFU)
7919 
7920 #define CSL_DSS_VID2_FIR_COEF_H0_C_RESERVED1_MASK (0x3FFFFC00U)
7921 #define CSL_DSS_VID2_FIR_COEF_H0_C_RESERVED1_SHIFT (0x0000000AU)
7922 #define CSL_DSS_VID2_FIR_COEF_H0_C_RESERVED1_MAX (0x000FFFFFU)
7923 
7924 #define CSL_DSS_VID2_FIR_COEF_H0_C_RESERVED_MASK (0xC0000000U)
7925 #define CSL_DSS_VID2_FIR_COEF_H0_C_RESERVED_SHIFT (0x0000001EU)
7926 #define CSL_DSS_VID2_FIR_COEF_H0_C_RESERVED_MAX (0x00000003U)
7927 
7928 /* FIR_COEF_H12 */
7929 
7930 #define CSL_DSS_VID2_FIR_COEF_H12_RESERVED1_MASK (0x000003FFU)
7931 #define CSL_DSS_VID2_FIR_COEF_H12_RESERVED1_SHIFT (0x00000000U)
7932 #define CSL_DSS_VID2_FIR_COEF_H12_RESERVED1_MAX (0x000003FFU)
7933 
7934 #define CSL_DSS_VID2_FIR_COEF_H12_FIRHC1_MASK (0x000FFC00U)
7935 #define CSL_DSS_VID2_FIR_COEF_H12_FIRHC1_SHIFT (0x0000000AU)
7936 #define CSL_DSS_VID2_FIR_COEF_H12_FIRHC1_MAX (0x000003FFU)
7937 
7938 #define CSL_DSS_VID2_FIR_COEF_H12_FIRHC2_MASK (0x3FF00000U)
7939 #define CSL_DSS_VID2_FIR_COEF_H12_FIRHC2_SHIFT (0x00000014U)
7940 #define CSL_DSS_VID2_FIR_COEF_H12_FIRHC2_MAX (0x000003FFU)
7941 
7942 #define CSL_DSS_VID2_FIR_COEF_H12_RESERVED_MASK (0xC0000000U)
7943 #define CSL_DSS_VID2_FIR_COEF_H12_RESERVED_SHIFT (0x0000001EU)
7944 #define CSL_DSS_VID2_FIR_COEF_H12_RESERVED_MAX (0x00000003U)
7945 
7946 /* FIR_COEF_H12_C */
7947 
7948 #define CSL_DSS_VID2_FIR_COEF_H12_C_RESERVED1_MASK (0x000003FFU)
7949 #define CSL_DSS_VID2_FIR_COEF_H12_C_RESERVED1_SHIFT (0x00000000U)
7950 #define CSL_DSS_VID2_FIR_COEF_H12_C_RESERVED1_MAX (0x000003FFU)
7951 
7952 #define CSL_DSS_VID2_FIR_COEF_H12_C_FIRHC1_MASK (0x000FFC00U)
7953 #define CSL_DSS_VID2_FIR_COEF_H12_C_FIRHC1_SHIFT (0x0000000AU)
7954 #define CSL_DSS_VID2_FIR_COEF_H12_C_FIRHC1_MAX (0x000003FFU)
7955 
7956 #define CSL_DSS_VID2_FIR_COEF_H12_C_FIRHC2_MASK (0x3FF00000U)
7957 #define CSL_DSS_VID2_FIR_COEF_H12_C_FIRHC2_SHIFT (0x00000014U)
7958 #define CSL_DSS_VID2_FIR_COEF_H12_C_FIRHC2_MAX (0x000003FFU)
7959 
7960 #define CSL_DSS_VID2_FIR_COEF_H12_C_RESERVED_MASK (0xC0000000U)
7961 #define CSL_DSS_VID2_FIR_COEF_H12_C_RESERVED_SHIFT (0x0000001EU)
7962 #define CSL_DSS_VID2_FIR_COEF_H12_C_RESERVED_MAX (0x00000003U)
7963 
7964 /* FIR_COEF_V0 */
7965 
7966 #define CSL_DSS_VID2_FIR_COEF_V0_FIRVC0_MASK (0x000003FFU)
7967 #define CSL_DSS_VID2_FIR_COEF_V0_FIRVC0_SHIFT (0x00000000U)
7968 #define CSL_DSS_VID2_FIR_COEF_V0_FIRVC0_MAX (0x000003FFU)
7969 
7970 #define CSL_DSS_VID2_FIR_COEF_V0_RESERVED1_MASK (0x3FFFFC00U)
7971 #define CSL_DSS_VID2_FIR_COEF_V0_RESERVED1_SHIFT (0x0000000AU)
7972 #define CSL_DSS_VID2_FIR_COEF_V0_RESERVED1_MAX (0x000FFFFFU)
7973 
7974 #define CSL_DSS_VID2_FIR_COEF_V0_RESERVED_MASK (0xC0000000U)
7975 #define CSL_DSS_VID2_FIR_COEF_V0_RESERVED_SHIFT (0x0000001EU)
7976 #define CSL_DSS_VID2_FIR_COEF_V0_RESERVED_MAX (0x00000003U)
7977 
7978 /* FIR_COEF_V0_C */
7979 
7980 #define CSL_DSS_VID2_FIR_COEF_V0_C_FIRVC0_MASK (0x000003FFU)
7981 #define CSL_DSS_VID2_FIR_COEF_V0_C_FIRVC0_SHIFT (0x00000000U)
7982 #define CSL_DSS_VID2_FIR_COEF_V0_C_FIRVC0_MAX (0x000003FFU)
7983 
7984 #define CSL_DSS_VID2_FIR_COEF_V0_C_RESERVED1_MASK (0x3FFFFC00U)
7985 #define CSL_DSS_VID2_FIR_COEF_V0_C_RESERVED1_SHIFT (0x0000000AU)
7986 #define CSL_DSS_VID2_FIR_COEF_V0_C_RESERVED1_MAX (0x000FFFFFU)
7987 
7988 #define CSL_DSS_VID2_FIR_COEF_V0_C_RESERVED_MASK (0xC0000000U)
7989 #define CSL_DSS_VID2_FIR_COEF_V0_C_RESERVED_SHIFT (0x0000001EU)
7990 #define CSL_DSS_VID2_FIR_COEF_V0_C_RESERVED_MAX (0x00000003U)
7991 
7992 /* FIR_COEF_V12 */
7993 
7994 #define CSL_DSS_VID2_FIR_COEF_V12_RESERVED1_MASK (0x000003FFU)
7995 #define CSL_DSS_VID2_FIR_COEF_V12_RESERVED1_SHIFT (0x00000000U)
7996 #define CSL_DSS_VID2_FIR_COEF_V12_RESERVED1_MAX (0x000003FFU)
7997 
7998 #define CSL_DSS_VID2_FIR_COEF_V12_FIRVC1_MASK (0x000FFC00U)
7999 #define CSL_DSS_VID2_FIR_COEF_V12_FIRVC1_SHIFT (0x0000000AU)
8000 #define CSL_DSS_VID2_FIR_COEF_V12_FIRVC1_MAX (0x000003FFU)
8001 
8002 #define CSL_DSS_VID2_FIR_COEF_V12_FIRVC2_MASK (0x3FF00000U)
8003 #define CSL_DSS_VID2_FIR_COEF_V12_FIRVC2_SHIFT (0x00000014U)
8004 #define CSL_DSS_VID2_FIR_COEF_V12_FIRVC2_MAX (0x000003FFU)
8005 
8006 #define CSL_DSS_VID2_FIR_COEF_V12_RESERVED_MASK (0xC0000000U)
8007 #define CSL_DSS_VID2_FIR_COEF_V12_RESERVED_SHIFT (0x0000001EU)
8008 #define CSL_DSS_VID2_FIR_COEF_V12_RESERVED_MAX (0x00000003U)
8009 
8010 /* FIR_COEF_V12_C */
8011 
8012 #define CSL_DSS_VID2_FIR_COEF_V12_C_RESERVED1_MASK (0x000003FFU)
8013 #define CSL_DSS_VID2_FIR_COEF_V12_C_RESERVED1_SHIFT (0x00000000U)
8014 #define CSL_DSS_VID2_FIR_COEF_V12_C_RESERVED1_MAX (0x000003FFU)
8015 
8016 #define CSL_DSS_VID2_FIR_COEF_V12_C_FIRVC1_MASK (0x000FFC00U)
8017 #define CSL_DSS_VID2_FIR_COEF_V12_C_FIRVC1_SHIFT (0x0000000AU)
8018 #define CSL_DSS_VID2_FIR_COEF_V12_C_FIRVC1_MAX (0x000003FFU)
8019 
8020 #define CSL_DSS_VID2_FIR_COEF_V12_C_FIRVC2_MASK (0x3FF00000U)
8021 #define CSL_DSS_VID2_FIR_COEF_V12_C_FIRVC2_SHIFT (0x00000014U)
8022 #define CSL_DSS_VID2_FIR_COEF_V12_C_FIRVC2_MAX (0x000003FFU)
8023 
8024 #define CSL_DSS_VID2_FIR_COEF_V12_C_RESERVED_MASK (0xC0000000U)
8025 #define CSL_DSS_VID2_FIR_COEF_V12_C_RESERVED_SHIFT (0x0000001EU)
8026 #define CSL_DSS_VID2_FIR_COEF_V12_C_RESERVED_MAX (0x00000003U)
8027 
8028 /* GLOBAL_ALPHA */
8029 
8030 #define CSL_DSS_VID2_GLOBAL_ALPHA_GLOBALALPHA_MASK (0x000000FFU)
8031 #define CSL_DSS_VID2_GLOBAL_ALPHA_GLOBALALPHA_SHIFT (0x00000000U)
8032 #define CSL_DSS_VID2_GLOBAL_ALPHA_GLOBALALPHA_MAX (0x000000FFU)
8033 
8034 #define CSL_DSS_VID2_GLOBAL_ALPHA_RESERVED_MASK (0xFFFFFF00U)
8035 #define CSL_DSS_VID2_GLOBAL_ALPHA_RESERVED_SHIFT (0x00000008U)
8036 #define CSL_DSS_VID2_GLOBAL_ALPHA_RESERVED_MAX (0x00FFFFFFU)
8037 
8038 /* MFLAG_THRESHOLD */
8039 
8040 #define CSL_DSS_VID2_MFLAG_THRESHOLD_LT_MFLAG_MASK (0x0000FFFFU)
8041 #define CSL_DSS_VID2_MFLAG_THRESHOLD_LT_MFLAG_SHIFT (0x00000000U)
8042 #define CSL_DSS_VID2_MFLAG_THRESHOLD_LT_MFLAG_MAX (0x0000FFFFU)
8043 
8044 #define CSL_DSS_VID2_MFLAG_THRESHOLD_HT_MFLAG_MASK (0xFFFF0000U)
8045 #define CSL_DSS_VID2_MFLAG_THRESHOLD_HT_MFLAG_SHIFT (0x00000010U)
8046 #define CSL_DSS_VID2_MFLAG_THRESHOLD_HT_MFLAG_MAX (0x0000FFFFU)
8047 
8048 /* PICTURE_SIZE */
8049 
8050 #define CSL_DSS_VID2_PICTURE_SIZE_MEMSIZEX_MASK (0x00003FFFU)
8051 #define CSL_DSS_VID2_PICTURE_SIZE_MEMSIZEX_SHIFT (0x00000000U)
8052 #define CSL_DSS_VID2_PICTURE_SIZE_MEMSIZEX_MAX (0x00003FFFU)
8053 
8054 #define CSL_DSS_VID2_PICTURE_SIZE_MEMSIZEY_MASK (0x3FFF0000U)
8055 #define CSL_DSS_VID2_PICTURE_SIZE_MEMSIZEY_SHIFT (0x00000010U)
8056 #define CSL_DSS_VID2_PICTURE_SIZE_MEMSIZEY_MAX (0x00003FFFU)
8057 
8058 /* PIXEL_INC */
8059 
8060 #define CSL_DSS_VID2_PIXEL_INC_PIXELINC_MASK (0x000000FFU)
8061 #define CSL_DSS_VID2_PIXEL_INC_PIXELINC_SHIFT (0x00000000U)
8062 #define CSL_DSS_VID2_PIXEL_INC_PIXELINC_MAX (0x000000FFU)
8063 
8064 #define CSL_DSS_VID2_PIXEL_INC_RESERVED_68_MASK (0xFFFFFF00U)
8065 #define CSL_DSS_VID2_PIXEL_INC_RESERVED_68_SHIFT (0x00000008U)
8066 #define CSL_DSS_VID2_PIXEL_INC_RESERVED_68_MAX (0x00FFFFFFU)
8067 
8068 /* PRELOAD */
8069 
8070 #define CSL_DSS_VID2_PRELOAD_PRELOAD_MASK (0x00000FFFU)
8071 #define CSL_DSS_VID2_PRELOAD_PRELOAD_SHIFT (0x00000000U)
8072 #define CSL_DSS_VID2_PRELOAD_PRELOAD_MAX (0x00000FFFU)
8073 
8074 #define CSL_DSS_VID2_PRELOAD_RESERVED_212_MASK (0xFFFFF000U)
8075 #define CSL_DSS_VID2_PRELOAD_RESERVED_212_SHIFT (0x0000000CU)
8076 #define CSL_DSS_VID2_PRELOAD_RESERVED_212_MAX (0x000FFFFFU)
8077 
8078 /* ROW_INC */
8079 
8080 #define CSL_DSS_VID2_ROW_INC_ROWINC_MASK (0xFFFFFFFFU)
8081 #define CSL_DSS_VID2_ROW_INC_ROWINC_SHIFT (0x00000000U)
8082 #define CSL_DSS_VID2_ROW_INC_ROWINC_MAX (0xFFFFFFFFU)
8083 
8084 /* SIZE */
8085 
8086 #define CSL_DSS_VID2_SIZE_SIZEX_MASK (0x00003FFFU)
8087 #define CSL_DSS_VID2_SIZE_SIZEX_SHIFT (0x00000000U)
8088 #define CSL_DSS_VID2_SIZE_SIZEX_MAX (0x00003FFFU)
8089 
8090 #define CSL_DSS_VID2_SIZE_SIZEY_MASK (0x3FFF0000U)
8091 #define CSL_DSS_VID2_SIZE_SIZEY_SHIFT (0x00000010U)
8092 #define CSL_DSS_VID2_SIZE_SIZEY_MAX (0x00003FFFU)
8093 
8094 /* BA_EXT_0 */
8095 
8096 #define CSL_DSS_VID2_BA_EXT_0_BA_EXT_MASK (0x0000FFFFU)
8097 #define CSL_DSS_VID2_BA_EXT_0_BA_EXT_SHIFT (0x00000000U)
8098 #define CSL_DSS_VID2_BA_EXT_0_BA_EXT_MAX (0x0000FFFFU)
8099 
8100 #define CSL_DSS_VID2_BA_EXT_0_RESERVED_MASK (0xFFFF0000U)
8101 #define CSL_DSS_VID2_BA_EXT_0_RESERVED_SHIFT (0x00000010U)
8102 #define CSL_DSS_VID2_BA_EXT_0_RESERVED_MAX (0x0000FFFFU)
8103 
8104 /* BA_EXT_1 */
8105 
8106 #define CSL_DSS_VID2_BA_EXT_1_BA_EXT_MASK (0x0000FFFFU)
8107 #define CSL_DSS_VID2_BA_EXT_1_BA_EXT_SHIFT (0x00000000U)
8108 #define CSL_DSS_VID2_BA_EXT_1_BA_EXT_MAX (0x0000FFFFU)
8109 
8110 #define CSL_DSS_VID2_BA_EXT_1_RESERVED_MASK (0xFFFF0000U)
8111 #define CSL_DSS_VID2_BA_EXT_1_RESERVED_SHIFT (0x00000010U)
8112 #define CSL_DSS_VID2_BA_EXT_1_RESERVED_MAX (0x0000FFFFU)
8113 
8114 /* BA_UV_EXT_0 */
8115 
8116 #define CSL_DSS_VID2_BA_UV_EXT_0_BA_UV_EXT_MASK (0x0000FFFFU)
8117 #define CSL_DSS_VID2_BA_UV_EXT_0_BA_UV_EXT_SHIFT (0x00000000U)
8118 #define CSL_DSS_VID2_BA_UV_EXT_0_BA_UV_EXT_MAX (0x0000FFFFU)
8119 
8120 #define CSL_DSS_VID2_BA_UV_EXT_0_RESERVED_MASK (0xFFFF0000U)
8121 #define CSL_DSS_VID2_BA_UV_EXT_0_RESERVED_SHIFT (0x00000010U)
8122 #define CSL_DSS_VID2_BA_UV_EXT_0_RESERVED_MAX (0x0000FFFFU)
8123 
8124 /* BA_UV_EXT_1 */
8125 
8126 #define CSL_DSS_VID2_BA_UV_EXT_1_BA_UV_EXT_MASK (0x0000FFFFU)
8127 #define CSL_DSS_VID2_BA_UV_EXT_1_BA_UV_EXT_SHIFT (0x00000000U)
8128 #define CSL_DSS_VID2_BA_UV_EXT_1_BA_UV_EXT_MAX (0x0000FFFFU)
8129 
8130 #define CSL_DSS_VID2_BA_UV_EXT_1_RESERVED_MASK (0xFFFF0000U)
8131 #define CSL_DSS_VID2_BA_UV_EXT_1_RESERVED_SHIFT (0x00000010U)
8132 #define CSL_DSS_VID2_BA_UV_EXT_1_RESERVED_MAX (0x0000FFFFU)
8133 
8134 /* CSC_COEF7 */
8135 
8136 #define CSL_DSS_VID2_CSC_COEF7_RESERVED_MASK (0x00000007U)
8137 #define CSL_DSS_VID2_CSC_COEF7_RESERVED_SHIFT (0x00000000U)
8138 #define CSL_DSS_VID2_CSC_COEF7_RESERVED_MAX (0x00000007U)
8139 
8140 #define CSL_DSS_VID2_CSC_COEF7_POSTOFFSET2_MASK (0x0000FFF8U)
8141 #define CSL_DSS_VID2_CSC_COEF7_POSTOFFSET2_SHIFT (0x00000003U)
8142 #define CSL_DSS_VID2_CSC_COEF7_POSTOFFSET2_MAX (0x00001FFFU)
8143 
8144 #define CSL_DSS_VID2_CSC_COEF7_RESERVED1_MASK (0x00070000U)
8145 #define CSL_DSS_VID2_CSC_COEF7_RESERVED1_SHIFT (0x00000010U)
8146 #define CSL_DSS_VID2_CSC_COEF7_RESERVED1_MAX (0x00000007U)
8147 
8148 #define CSL_DSS_VID2_CSC_COEF7_POSTOFFSET3_MASK (0xFFF80000U)
8149 #define CSL_DSS_VID2_CSC_COEF7_POSTOFFSET3_SHIFT (0x00000013U)
8150 #define CSL_DSS_VID2_CSC_COEF7_POSTOFFSET3_MAX (0x00001FFFU)
8151 
8152 /* ROW_INC_UV */
8153 
8154 #define CSL_DSS_VID2_ROW_INC_UV_ROWINC_MASK (0xFFFFFFFFU)
8155 #define CSL_DSS_VID2_ROW_INC_UV_ROWINC_SHIFT (0x00000000U)
8156 #define CSL_DSS_VID2_ROW_INC_UV_ROWINC_MAX (0xFFFFFFFFU)
8157 
8158 /* TILE */
8159 
8160 #define CSL_DSS_VID2_TILE_TILEINDEX_MASK (0x007FFFFFU)
8161 #define CSL_DSS_VID2_TILE_TILEINDEX_SHIFT (0x00000000U)
8162 #define CSL_DSS_VID2_TILE_TILEINDEX_MAX (0x007FFFFFU)
8163 
8164 /* TILE2 */
8165 
8166 #define CSL_DSS_VID2_TILE2_NUM_TILES_MASK (0x007FFFFFU)
8167 #define CSL_DSS_VID2_TILE2_NUM_TILES_SHIFT (0x00000000U)
8168 #define CSL_DSS_VID2_TILE2_NUM_TILES_MAX (0x007FFFFFU)
8169 
8170 #define CSL_DSS_VID2_TILE2_RESERVED_MASK (0xFF800000U)
8171 #define CSL_DSS_VID2_TILE2_RESERVED_SHIFT (0x00000017U)
8172 #define CSL_DSS_VID2_TILE2_RESERVED_MAX (0x000001FFU)
8173 
8174 /* FBDC_ATTRIBUTES */
8175 
8176 #define CSL_DSS_VID2_FBDC_ATTRIBUTES_ENABLE_MASK (0x00000001U)
8177 #define CSL_DSS_VID2_FBDC_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
8178 #define CSL_DSS_VID2_FBDC_ATTRIBUTES_ENABLE_MAX (0x00000001U)
8179 
8180 #define CSL_DSS_VID2_FBDC_ATTRIBUTES_FORMAT_MASK (0x000000FEU)
8181 #define CSL_DSS_VID2_FBDC_ATTRIBUTES_FORMAT_SHIFT (0x00000001U)
8182 #define CSL_DSS_VID2_FBDC_ATTRIBUTES_FORMAT_MAX (0x0000007FU)
8183 
8184 #define CSL_DSS_VID2_FBDC_ATTRIBUTES_FORMAT_VAL_U8U8U8U8 (0xCU)
8185 #define CSL_DSS_VID2_FBDC_ATTRIBUTES_FORMAT_VAL_A2R10B10G10 (0xEU)
8186 
8187 #define CSL_DSS_VID2_FBDC_ATTRIBUTES_TILETYPE_MASK (0x00000300U)
8188 #define CSL_DSS_VID2_FBDC_ATTRIBUTES_TILETYPE_SHIFT (0x00000008U)
8189 #define CSL_DSS_VID2_FBDC_ATTRIBUTES_TILETYPE_MAX (0x00000003U)
8190 
8191 #define CSL_DSS_VID2_FBDC_ATTRIBUTES_TILETYPE_VAL_TILE16BY4 (0x2U)
8192 #define CSL_DSS_VID2_FBDC_ATTRIBUTES_TILETYPE_VAL_TILE32BY2 (0x3U)
8193 
8194 /* FBDC_CLEAR_COLOR */
8195 
8196 #define CSL_DSS_VID2_FBDC_CLEAR_COLOR_CLEARCOLOR_MASK (0xFFFFFFFFU)
8197 #define CSL_DSS_VID2_FBDC_CLEAR_COLOR_CLEARCOLOR_SHIFT (0x00000000U)
8198 #define CSL_DSS_VID2_FBDC_CLEAR_COLOR_CLEARCOLOR_MAX (0xFFFFFFFFU)
8199 
8200 /* CLUT_0 */
8201 
8202 #define CSL_DSS_VID2_CLUT_0_VALUE_B_MASK (0x000003FFU)
8203 #define CSL_DSS_VID2_CLUT_0_VALUE_B_SHIFT (0x00000000U)
8204 #define CSL_DSS_VID2_CLUT_0_VALUE_B_MAX (0x000003FFU)
8205 
8206 #define CSL_DSS_VID2_CLUT_0_VALUE_G_MASK (0x000FFC00U)
8207 #define CSL_DSS_VID2_CLUT_0_VALUE_G_SHIFT (0x0000000AU)
8208 #define CSL_DSS_VID2_CLUT_0_VALUE_G_MAX (0x000003FFU)
8209 
8210 #define CSL_DSS_VID2_CLUT_0_VALUE_R_MASK (0x3FF00000U)
8211 #define CSL_DSS_VID2_CLUT_0_VALUE_R_SHIFT (0x00000014U)
8212 #define CSL_DSS_VID2_CLUT_0_VALUE_R_MAX (0x000003FFU)
8213 
8214 #define CSL_DSS_VID2_CLUT_0_INDEX_MASK (0x80000000U)
8215 #define CSL_DSS_VID2_CLUT_0_INDEX_SHIFT (0x0000001FU)
8216 #define CSL_DSS_VID2_CLUT_0_INDEX_MAX (0x00000001U)
8217 
8218 /* CLUT_1 */
8219 
8220 #define CSL_DSS_VID2_CLUT_1_VALUE_B_MASK (0x000003FFU)
8221 #define CSL_DSS_VID2_CLUT_1_VALUE_B_SHIFT (0x00000000U)
8222 #define CSL_DSS_VID2_CLUT_1_VALUE_B_MAX (0x000003FFU)
8223 
8224 #define CSL_DSS_VID2_CLUT_1_VALUE_G_MASK (0x000FFC00U)
8225 #define CSL_DSS_VID2_CLUT_1_VALUE_G_SHIFT (0x0000000AU)
8226 #define CSL_DSS_VID2_CLUT_1_VALUE_G_MAX (0x000003FFU)
8227 
8228 #define CSL_DSS_VID2_CLUT_1_VALUE_R_MASK (0x3FF00000U)
8229 #define CSL_DSS_VID2_CLUT_1_VALUE_R_SHIFT (0x00000014U)
8230 #define CSL_DSS_VID2_CLUT_1_VALUE_R_MAX (0x000003FFU)
8231 
8232 #define CSL_DSS_VID2_CLUT_1_INDEX_MASK (0x80000000U)
8233 #define CSL_DSS_VID2_CLUT_1_INDEX_SHIFT (0x0000001FU)
8234 #define CSL_DSS_VID2_CLUT_1_INDEX_MAX (0x00000001U)
8235 
8236 /* CLUT_2 */
8237 
8238 #define CSL_DSS_VID2_CLUT_2_VALUE_B_MASK (0x000003FFU)
8239 #define CSL_DSS_VID2_CLUT_2_VALUE_B_SHIFT (0x00000000U)
8240 #define CSL_DSS_VID2_CLUT_2_VALUE_B_MAX (0x000003FFU)
8241 
8242 #define CSL_DSS_VID2_CLUT_2_VALUE_G_MASK (0x000FFC00U)
8243 #define CSL_DSS_VID2_CLUT_2_VALUE_G_SHIFT (0x0000000AU)
8244 #define CSL_DSS_VID2_CLUT_2_VALUE_G_MAX (0x000003FFU)
8245 
8246 #define CSL_DSS_VID2_CLUT_2_VALUE_R_MASK (0x3FF00000U)
8247 #define CSL_DSS_VID2_CLUT_2_VALUE_R_SHIFT (0x00000014U)
8248 #define CSL_DSS_VID2_CLUT_2_VALUE_R_MAX (0x000003FFU)
8249 
8250 #define CSL_DSS_VID2_CLUT_2_INDEX_MASK (0x80000000U)
8251 #define CSL_DSS_VID2_CLUT_2_INDEX_SHIFT (0x0000001FU)
8252 #define CSL_DSS_VID2_CLUT_2_INDEX_MAX (0x00000001U)
8253 
8254 /* CLUT_3 */
8255 
8256 #define CSL_DSS_VID2_CLUT_3_VALUE_B_MASK (0x000003FFU)
8257 #define CSL_DSS_VID2_CLUT_3_VALUE_B_SHIFT (0x00000000U)
8258 #define CSL_DSS_VID2_CLUT_3_VALUE_B_MAX (0x000003FFU)
8259 
8260 #define CSL_DSS_VID2_CLUT_3_VALUE_G_MASK (0x000FFC00U)
8261 #define CSL_DSS_VID2_CLUT_3_VALUE_G_SHIFT (0x0000000AU)
8262 #define CSL_DSS_VID2_CLUT_3_VALUE_G_MAX (0x000003FFU)
8263 
8264 #define CSL_DSS_VID2_CLUT_3_VALUE_R_MASK (0x3FF00000U)
8265 #define CSL_DSS_VID2_CLUT_3_VALUE_R_SHIFT (0x00000014U)
8266 #define CSL_DSS_VID2_CLUT_3_VALUE_R_MAX (0x000003FFU)
8267 
8268 #define CSL_DSS_VID2_CLUT_3_INDEX_MASK (0x80000000U)
8269 #define CSL_DSS_VID2_CLUT_3_INDEX_SHIFT (0x0000001FU)
8270 #define CSL_DSS_VID2_CLUT_3_INDEX_MAX (0x00000001U)
8271 
8272 /* CLUT_4 */
8273 
8274 #define CSL_DSS_VID2_CLUT_4_VALUE_B_MASK (0x000003FFU)
8275 #define CSL_DSS_VID2_CLUT_4_VALUE_B_SHIFT (0x00000000U)
8276 #define CSL_DSS_VID2_CLUT_4_VALUE_B_MAX (0x000003FFU)
8277 
8278 #define CSL_DSS_VID2_CLUT_4_VALUE_G_MASK (0x000FFC00U)
8279 #define CSL_DSS_VID2_CLUT_4_VALUE_G_SHIFT (0x0000000AU)
8280 #define CSL_DSS_VID2_CLUT_4_VALUE_G_MAX (0x000003FFU)
8281 
8282 #define CSL_DSS_VID2_CLUT_4_VALUE_R_MASK (0x3FF00000U)
8283 #define CSL_DSS_VID2_CLUT_4_VALUE_R_SHIFT (0x00000014U)
8284 #define CSL_DSS_VID2_CLUT_4_VALUE_R_MAX (0x000003FFU)
8285 
8286 #define CSL_DSS_VID2_CLUT_4_INDEX_MASK (0x80000000U)
8287 #define CSL_DSS_VID2_CLUT_4_INDEX_SHIFT (0x0000001FU)
8288 #define CSL_DSS_VID2_CLUT_4_INDEX_MAX (0x00000001U)
8289 
8290 /* CLUT_5 */
8291 
8292 #define CSL_DSS_VID2_CLUT_5_VALUE_B_MASK (0x000003FFU)
8293 #define CSL_DSS_VID2_CLUT_5_VALUE_B_SHIFT (0x00000000U)
8294 #define CSL_DSS_VID2_CLUT_5_VALUE_B_MAX (0x000003FFU)
8295 
8296 #define CSL_DSS_VID2_CLUT_5_VALUE_G_MASK (0x000FFC00U)
8297 #define CSL_DSS_VID2_CLUT_5_VALUE_G_SHIFT (0x0000000AU)
8298 #define CSL_DSS_VID2_CLUT_5_VALUE_G_MAX (0x000003FFU)
8299 
8300 #define CSL_DSS_VID2_CLUT_5_VALUE_R_MASK (0x3FF00000U)
8301 #define CSL_DSS_VID2_CLUT_5_VALUE_R_SHIFT (0x00000014U)
8302 #define CSL_DSS_VID2_CLUT_5_VALUE_R_MAX (0x000003FFU)
8303 
8304 #define CSL_DSS_VID2_CLUT_5_INDEX_MASK (0x80000000U)
8305 #define CSL_DSS_VID2_CLUT_5_INDEX_SHIFT (0x0000001FU)
8306 #define CSL_DSS_VID2_CLUT_5_INDEX_MAX (0x00000001U)
8307 
8308 /* CLUT_6 */
8309 
8310 #define CSL_DSS_VID2_CLUT_6_VALUE_B_MASK (0x000003FFU)
8311 #define CSL_DSS_VID2_CLUT_6_VALUE_B_SHIFT (0x00000000U)
8312 #define CSL_DSS_VID2_CLUT_6_VALUE_B_MAX (0x000003FFU)
8313 
8314 #define CSL_DSS_VID2_CLUT_6_VALUE_G_MASK (0x000FFC00U)
8315 #define CSL_DSS_VID2_CLUT_6_VALUE_G_SHIFT (0x0000000AU)
8316 #define CSL_DSS_VID2_CLUT_6_VALUE_G_MAX (0x000003FFU)
8317 
8318 #define CSL_DSS_VID2_CLUT_6_VALUE_R_MASK (0x3FF00000U)
8319 #define CSL_DSS_VID2_CLUT_6_VALUE_R_SHIFT (0x00000014U)
8320 #define CSL_DSS_VID2_CLUT_6_VALUE_R_MAX (0x000003FFU)
8321 
8322 #define CSL_DSS_VID2_CLUT_6_INDEX_MASK (0x80000000U)
8323 #define CSL_DSS_VID2_CLUT_6_INDEX_SHIFT (0x0000001FU)
8324 #define CSL_DSS_VID2_CLUT_6_INDEX_MAX (0x00000001U)
8325 
8326 /* CLUT_7 */
8327 
8328 #define CSL_DSS_VID2_CLUT_7_VALUE_B_MASK (0x000003FFU)
8329 #define CSL_DSS_VID2_CLUT_7_VALUE_B_SHIFT (0x00000000U)
8330 #define CSL_DSS_VID2_CLUT_7_VALUE_B_MAX (0x000003FFU)
8331 
8332 #define CSL_DSS_VID2_CLUT_7_VALUE_G_MASK (0x000FFC00U)
8333 #define CSL_DSS_VID2_CLUT_7_VALUE_G_SHIFT (0x0000000AU)
8334 #define CSL_DSS_VID2_CLUT_7_VALUE_G_MAX (0x000003FFU)
8335 
8336 #define CSL_DSS_VID2_CLUT_7_VALUE_R_MASK (0x3FF00000U)
8337 #define CSL_DSS_VID2_CLUT_7_VALUE_R_SHIFT (0x00000014U)
8338 #define CSL_DSS_VID2_CLUT_7_VALUE_R_MAX (0x000003FFU)
8339 
8340 #define CSL_DSS_VID2_CLUT_7_INDEX_MASK (0x80000000U)
8341 #define CSL_DSS_VID2_CLUT_7_INDEX_SHIFT (0x0000001FU)
8342 #define CSL_DSS_VID2_CLUT_7_INDEX_MAX (0x00000001U)
8343 
8344 /* CLUT_8 */
8345 
8346 #define CSL_DSS_VID2_CLUT_8_VALUE_B_MASK (0x000003FFU)
8347 #define CSL_DSS_VID2_CLUT_8_VALUE_B_SHIFT (0x00000000U)
8348 #define CSL_DSS_VID2_CLUT_8_VALUE_B_MAX (0x000003FFU)
8349 
8350 #define CSL_DSS_VID2_CLUT_8_VALUE_G_MASK (0x000FFC00U)
8351 #define CSL_DSS_VID2_CLUT_8_VALUE_G_SHIFT (0x0000000AU)
8352 #define CSL_DSS_VID2_CLUT_8_VALUE_G_MAX (0x000003FFU)
8353 
8354 #define CSL_DSS_VID2_CLUT_8_VALUE_R_MASK (0x3FF00000U)
8355 #define CSL_DSS_VID2_CLUT_8_VALUE_R_SHIFT (0x00000014U)
8356 #define CSL_DSS_VID2_CLUT_8_VALUE_R_MAX (0x000003FFU)
8357 
8358 #define CSL_DSS_VID2_CLUT_8_INDEX_MASK (0x80000000U)
8359 #define CSL_DSS_VID2_CLUT_8_INDEX_SHIFT (0x0000001FU)
8360 #define CSL_DSS_VID2_CLUT_8_INDEX_MAX (0x00000001U)
8361 
8362 /* CLUT_9 */
8363 
8364 #define CSL_DSS_VID2_CLUT_9_VALUE_B_MASK (0x000003FFU)
8365 #define CSL_DSS_VID2_CLUT_9_VALUE_B_SHIFT (0x00000000U)
8366 #define CSL_DSS_VID2_CLUT_9_VALUE_B_MAX (0x000003FFU)
8367 
8368 #define CSL_DSS_VID2_CLUT_9_VALUE_G_MASK (0x000FFC00U)
8369 #define CSL_DSS_VID2_CLUT_9_VALUE_G_SHIFT (0x0000000AU)
8370 #define CSL_DSS_VID2_CLUT_9_VALUE_G_MAX (0x000003FFU)
8371 
8372 #define CSL_DSS_VID2_CLUT_9_VALUE_R_MASK (0x3FF00000U)
8373 #define CSL_DSS_VID2_CLUT_9_VALUE_R_SHIFT (0x00000014U)
8374 #define CSL_DSS_VID2_CLUT_9_VALUE_R_MAX (0x000003FFU)
8375 
8376 #define CSL_DSS_VID2_CLUT_9_INDEX_MASK (0x80000000U)
8377 #define CSL_DSS_VID2_CLUT_9_INDEX_SHIFT (0x0000001FU)
8378 #define CSL_DSS_VID2_CLUT_9_INDEX_MAX (0x00000001U)
8379 
8380 /* CLUT_10 */
8381 
8382 #define CSL_DSS_VID2_CLUT_10_VALUE_B_MASK (0x000003FFU)
8383 #define CSL_DSS_VID2_CLUT_10_VALUE_B_SHIFT (0x00000000U)
8384 #define CSL_DSS_VID2_CLUT_10_VALUE_B_MAX (0x000003FFU)
8385 
8386 #define CSL_DSS_VID2_CLUT_10_VALUE_G_MASK (0x000FFC00U)
8387 #define CSL_DSS_VID2_CLUT_10_VALUE_G_SHIFT (0x0000000AU)
8388 #define CSL_DSS_VID2_CLUT_10_VALUE_G_MAX (0x000003FFU)
8389 
8390 #define CSL_DSS_VID2_CLUT_10_VALUE_R_MASK (0x3FF00000U)
8391 #define CSL_DSS_VID2_CLUT_10_VALUE_R_SHIFT (0x00000014U)
8392 #define CSL_DSS_VID2_CLUT_10_VALUE_R_MAX (0x000003FFU)
8393 
8394 #define CSL_DSS_VID2_CLUT_10_INDEX_MASK (0x80000000U)
8395 #define CSL_DSS_VID2_CLUT_10_INDEX_SHIFT (0x0000001FU)
8396 #define CSL_DSS_VID2_CLUT_10_INDEX_MAX (0x00000001U)
8397 
8398 /* CLUT_11 */
8399 
8400 #define CSL_DSS_VID2_CLUT_11_VALUE_B_MASK (0x000003FFU)
8401 #define CSL_DSS_VID2_CLUT_11_VALUE_B_SHIFT (0x00000000U)
8402 #define CSL_DSS_VID2_CLUT_11_VALUE_B_MAX (0x000003FFU)
8403 
8404 #define CSL_DSS_VID2_CLUT_11_VALUE_G_MASK (0x000FFC00U)
8405 #define CSL_DSS_VID2_CLUT_11_VALUE_G_SHIFT (0x0000000AU)
8406 #define CSL_DSS_VID2_CLUT_11_VALUE_G_MAX (0x000003FFU)
8407 
8408 #define CSL_DSS_VID2_CLUT_11_VALUE_R_MASK (0x3FF00000U)
8409 #define CSL_DSS_VID2_CLUT_11_VALUE_R_SHIFT (0x00000014U)
8410 #define CSL_DSS_VID2_CLUT_11_VALUE_R_MAX (0x000003FFU)
8411 
8412 #define CSL_DSS_VID2_CLUT_11_INDEX_MASK (0x80000000U)
8413 #define CSL_DSS_VID2_CLUT_11_INDEX_SHIFT (0x0000001FU)
8414 #define CSL_DSS_VID2_CLUT_11_INDEX_MAX (0x00000001U)
8415 
8416 /* CLUT_12 */
8417 
8418 #define CSL_DSS_VID2_CLUT_12_VALUE_B_MASK (0x000003FFU)
8419 #define CSL_DSS_VID2_CLUT_12_VALUE_B_SHIFT (0x00000000U)
8420 #define CSL_DSS_VID2_CLUT_12_VALUE_B_MAX (0x000003FFU)
8421 
8422 #define CSL_DSS_VID2_CLUT_12_VALUE_G_MASK (0x000FFC00U)
8423 #define CSL_DSS_VID2_CLUT_12_VALUE_G_SHIFT (0x0000000AU)
8424 #define CSL_DSS_VID2_CLUT_12_VALUE_G_MAX (0x000003FFU)
8425 
8426 #define CSL_DSS_VID2_CLUT_12_VALUE_R_MASK (0x3FF00000U)
8427 #define CSL_DSS_VID2_CLUT_12_VALUE_R_SHIFT (0x00000014U)
8428 #define CSL_DSS_VID2_CLUT_12_VALUE_R_MAX (0x000003FFU)
8429 
8430 #define CSL_DSS_VID2_CLUT_12_INDEX_MASK (0x80000000U)
8431 #define CSL_DSS_VID2_CLUT_12_INDEX_SHIFT (0x0000001FU)
8432 #define CSL_DSS_VID2_CLUT_12_INDEX_MAX (0x00000001U)
8433 
8434 /* CLUT_13 */
8435 
8436 #define CSL_DSS_VID2_CLUT_13_VALUE_B_MASK (0x000003FFU)
8437 #define CSL_DSS_VID2_CLUT_13_VALUE_B_SHIFT (0x00000000U)
8438 #define CSL_DSS_VID2_CLUT_13_VALUE_B_MAX (0x000003FFU)
8439 
8440 #define CSL_DSS_VID2_CLUT_13_VALUE_G_MASK (0x000FFC00U)
8441 #define CSL_DSS_VID2_CLUT_13_VALUE_G_SHIFT (0x0000000AU)
8442 #define CSL_DSS_VID2_CLUT_13_VALUE_G_MAX (0x000003FFU)
8443 
8444 #define CSL_DSS_VID2_CLUT_13_VALUE_R_MASK (0x3FF00000U)
8445 #define CSL_DSS_VID2_CLUT_13_VALUE_R_SHIFT (0x00000014U)
8446 #define CSL_DSS_VID2_CLUT_13_VALUE_R_MAX (0x000003FFU)
8447 
8448 #define CSL_DSS_VID2_CLUT_13_INDEX_MASK (0x80000000U)
8449 #define CSL_DSS_VID2_CLUT_13_INDEX_SHIFT (0x0000001FU)
8450 #define CSL_DSS_VID2_CLUT_13_INDEX_MAX (0x00000001U)
8451 
8452 /* CLUT_14 */
8453 
8454 #define CSL_DSS_VID2_CLUT_14_VALUE_B_MASK (0x000003FFU)
8455 #define CSL_DSS_VID2_CLUT_14_VALUE_B_SHIFT (0x00000000U)
8456 #define CSL_DSS_VID2_CLUT_14_VALUE_B_MAX (0x000003FFU)
8457 
8458 #define CSL_DSS_VID2_CLUT_14_VALUE_G_MASK (0x000FFC00U)
8459 #define CSL_DSS_VID2_CLUT_14_VALUE_G_SHIFT (0x0000000AU)
8460 #define CSL_DSS_VID2_CLUT_14_VALUE_G_MAX (0x000003FFU)
8461 
8462 #define CSL_DSS_VID2_CLUT_14_VALUE_R_MASK (0x3FF00000U)
8463 #define CSL_DSS_VID2_CLUT_14_VALUE_R_SHIFT (0x00000014U)
8464 #define CSL_DSS_VID2_CLUT_14_VALUE_R_MAX (0x000003FFU)
8465 
8466 #define CSL_DSS_VID2_CLUT_14_INDEX_MASK (0x80000000U)
8467 #define CSL_DSS_VID2_CLUT_14_INDEX_SHIFT (0x0000001FU)
8468 #define CSL_DSS_VID2_CLUT_14_INDEX_MAX (0x00000001U)
8469 
8470 /* CLUT_15 */
8471 
8472 #define CSL_DSS_VID2_CLUT_15_VALUE_B_MASK (0x000003FFU)
8473 #define CSL_DSS_VID2_CLUT_15_VALUE_B_SHIFT (0x00000000U)
8474 #define CSL_DSS_VID2_CLUT_15_VALUE_B_MAX (0x000003FFU)
8475 
8476 #define CSL_DSS_VID2_CLUT_15_VALUE_G_MASK (0x000FFC00U)
8477 #define CSL_DSS_VID2_CLUT_15_VALUE_G_SHIFT (0x0000000AU)
8478 #define CSL_DSS_VID2_CLUT_15_VALUE_G_MAX (0x000003FFU)
8479 
8480 #define CSL_DSS_VID2_CLUT_15_VALUE_R_MASK (0x3FF00000U)
8481 #define CSL_DSS_VID2_CLUT_15_VALUE_R_SHIFT (0x00000014U)
8482 #define CSL_DSS_VID2_CLUT_15_VALUE_R_MAX (0x000003FFU)
8483 
8484 #define CSL_DSS_VID2_CLUT_15_INDEX_MASK (0x80000000U)
8485 #define CSL_DSS_VID2_CLUT_15_INDEX_SHIFT (0x0000001FU)
8486 #define CSL_DSS_VID2_CLUT_15_INDEX_MAX (0x00000001U)
8487 
8488 /* SAFETY_ATTRIBUTES */
8489 
8490 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_ENABLE_MASK (0x00000001U)
8491 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
8492 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_ENABLE_MAX (0x00000001U)
8493 
8494 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_CAPTUREMODE_MASK (0x00000002U)
8495 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_CAPTUREMODE_SHIFT (0x00000001U)
8496 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_CAPTUREMODE_MAX (0x00000001U)
8497 
8498 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_DATACHECK (0x1U)
8499 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_FRAMEFREEZE (0x0U)
8500 
8501 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_SEEDSELECT_MASK (0x00000004U)
8502 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_SEEDSELECT_SHIFT (0x00000002U)
8503 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_SEEDSELECT_MAX (0x00000001U)
8504 
8505 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_ENABLE (0x1U)
8506 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_DISABLE (0x0U)
8507 
8508 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_THRESHOLD_MASK (0x000007F8U)
8509 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_THRESHOLD_SHIFT (0x00000003U)
8510 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_THRESHOLD_MAX (0x000000FFU)
8511 
8512 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_FRAMESKIP_MASK (0x00001800U)
8513 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_FRAMESKIP_SHIFT (0x0000000BU)
8514 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_FRAMESKIP_MAX (0x00000003U)
8515 
8516 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_DISABLE (0x0U)
8517 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_EVEN (0x1U)
8518 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_ODD (0x2U)
8519 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_RESERVED (0x3U)
8520 
8521 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_RESERVED_MASK (0xFFFFE000U)
8522 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_RESERVED_SHIFT (0x0000000DU)
8523 #define CSL_DSS_VID2_SAFETY_ATTRIBUTES_RESERVED_MAX (0x0007FFFFU)
8524 
8525 /* SAFETY_CAPT_SIGNATURE */
8526 
8527 #define CSL_DSS_VID2_SAFETY_CAPT_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
8528 #define CSL_DSS_VID2_SAFETY_CAPT_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
8529 #define CSL_DSS_VID2_SAFETY_CAPT_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
8530 
8531 /* SAFETY_POSITION */
8532 
8533 #define CSL_DSS_VID2_SAFETY_POSITION_POSX_MASK (0x00003FFFU)
8534 #define CSL_DSS_VID2_SAFETY_POSITION_POSX_SHIFT (0x00000000U)
8535 #define CSL_DSS_VID2_SAFETY_POSITION_POSX_MAX (0x00003FFFU)
8536 
8537 #define CSL_DSS_VID2_SAFETY_POSITION_POSY_MASK (0x3FFF0000U)
8538 #define CSL_DSS_VID2_SAFETY_POSITION_POSY_SHIFT (0x00000010U)
8539 #define CSL_DSS_VID2_SAFETY_POSITION_POSY_MAX (0x00003FFFU)
8540 
8541 /* SAFETY_REF_SIGNATURE */
8542 
8543 #define CSL_DSS_VID2_SAFETY_REF_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
8544 #define CSL_DSS_VID2_SAFETY_REF_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
8545 #define CSL_DSS_VID2_SAFETY_REF_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
8546 
8547 /* SAFETY_SIZE */
8548 
8549 #define CSL_DSS_VID2_SAFETY_SIZE_SIZEX_MASK (0x00003FFFU)
8550 #define CSL_DSS_VID2_SAFETY_SIZE_SIZEX_SHIFT (0x00000000U)
8551 #define CSL_DSS_VID2_SAFETY_SIZE_SIZEX_MAX (0x00003FFFU)
8552 
8553 #define CSL_DSS_VID2_SAFETY_SIZE_SIZEY_MASK (0x3FFF0000U)
8554 #define CSL_DSS_VID2_SAFETY_SIZE_SIZEY_SHIFT (0x00000010U)
8555 #define CSL_DSS_VID2_SAFETY_SIZE_SIZEY_MAX (0x00003FFFU)
8556 
8557 /* SAFETY_LFSR_SEED */
8558 
8559 #define CSL_DSS_VID2_SAFETY_LFSR_SEED_SEED_MASK (0xFFFFFFFFU)
8560 #define CSL_DSS_VID2_SAFETY_LFSR_SEED_SEED_SHIFT (0x00000000U)
8561 #define CSL_DSS_VID2_SAFETY_LFSR_SEED_SEED_MAX (0xFFFFFFFFU)
8562 
8563 /* LUMAKEY */
8564 
8565 #define CSL_DSS_VID2_LUMAKEY_LUMAKEYMIN_MASK (0x00000FFFU)
8566 #define CSL_DSS_VID2_LUMAKEY_LUMAKEYMIN_SHIFT (0x00000000U)
8567 #define CSL_DSS_VID2_LUMAKEY_LUMAKEYMIN_MAX (0x00000FFFU)
8568 
8569 #define CSL_DSS_VID2_LUMAKEY_RESERVED_MASK (0x0000F000U)
8570 #define CSL_DSS_VID2_LUMAKEY_RESERVED_SHIFT (0x0000000CU)
8571 #define CSL_DSS_VID2_LUMAKEY_RESERVED_MAX (0x0000000FU)
8572 
8573 #define CSL_DSS_VID2_LUMAKEY_LUMAKEYMAX_MASK (0x0FFF0000U)
8574 #define CSL_DSS_VID2_LUMAKEY_LUMAKEYMAX_SHIFT (0x00000010U)
8575 #define CSL_DSS_VID2_LUMAKEY_LUMAKEYMAX_MAX (0x00000FFFU)
8576 
8577 #define CSL_DSS_VID2_LUMAKEY_RESERVED1_MASK (0xF0000000U)
8578 #define CSL_DSS_VID2_LUMAKEY_RESERVED1_SHIFT (0x0000001CU)
8579 #define CSL_DSS_VID2_LUMAKEY_RESERVED1_MAX (0x0000000FU)
8580 
8581 /* DMA_BUFSIZE */
8582 
8583 #define CSL_DSS_VID2_DMA_BUFSIZE_BUFSIZE_MASK (0x0000001FU)
8584 #define CSL_DSS_VID2_DMA_BUFSIZE_BUFSIZE_SHIFT (0x00000000U)
8585 #define CSL_DSS_VID2_DMA_BUFSIZE_BUFSIZE_MAX (0x0000001FU)
8586 
8587 #define CSL_DSS_VID2_DMA_BUFSIZE_RESERVED_MASK (0xFFFFFFE0U)
8588 #define CSL_DSS_VID2_DMA_BUFSIZE_RESERVED_SHIFT (0x00000005U)
8589 #define CSL_DSS_VID2_DMA_BUFSIZE_RESERVED_MAX (0x07FFFFFFU)
8590 
8591 /* CROP */
8592 
8593 #define CSL_DSS_VID2_CROP_CROPLEFT_MASK (0x0000001FU)
8594 #define CSL_DSS_VID2_CROP_CROPLEFT_SHIFT (0x00000000U)
8595 #define CSL_DSS_VID2_CROP_CROPLEFT_MAX (0x0000001FU)
8596 
8597 #define CSL_DSS_VID2_CROP_CROPRIGHT_MASK (0x00001F00U)
8598 #define CSL_DSS_VID2_CROP_CROPRIGHT_SHIFT (0x00000008U)
8599 #define CSL_DSS_VID2_CROP_CROPRIGHT_MAX (0x0000001FU)
8600 
8601 #define CSL_DSS_VID2_CROP_CROPTOP_MASK (0x001F0000U)
8602 #define CSL_DSS_VID2_CROP_CROPTOP_SHIFT (0x00000010U)
8603 #define CSL_DSS_VID2_CROP_CROPTOP_MAX (0x0000001FU)
8604 
8605 #define CSL_DSS_VID2_CROP_CROPBOTTOM_MASK (0x1F000000U)
8606 #define CSL_DSS_VID2_CROP_CROPBOTTOM_SHIFT (0x00000018U)
8607 #define CSL_DSS_VID2_CROP_CROPBOTTOM_MAX (0x0000001FU)
8608 
8609 /* SECURE */
8610 
8611 #define CSL_DSS_VID2_SECURE_SECURE_MASK (0x00000001U)
8612 #define CSL_DSS_VID2_SECURE_SECURE_SHIFT (0x00000000U)
8613 #define CSL_DSS_VID2_SECURE_SECURE_MAX (0x00000001U)
8614 
8615 #define CSL_DSS_VID2_SECURE_SECURE_VAL_SECUREDIS (0x0U)
8616 #define CSL_DSS_VID2_SECURE_SECURE_VAL_SECUREEN (0x1U)
8617 
8618 #define CSL_DSS_VID2_SECURE_RESERVED_MASK (0xFFFFFFFEU)
8619 #define CSL_DSS_VID2_SECURE_RESERVED_SHIFT (0x00000001U)
8620 #define CSL_DSS_VID2_SECURE_RESERVED_MAX (0x7FFFFFFFU)
8621 
8622 /* PIPE_GO */
8623 
8624 #define CSL_DSS_VID2_PIPE_GO_GOBIT_MASK (0x00000001U)
8625 #define CSL_DSS_VID2_PIPE_GO_GOBIT_SHIFT (0x00000000U)
8626 #define CSL_DSS_VID2_PIPE_GO_GOBIT_MAX (0x00000001U)
8627 
8628 #define CSL_DSS_VID2_PIPE_GO_GOBIT_VAL_HFUISR (0x0U)
8629 #define CSL_DSS_VID2_PIPE_GO_GOBIT_VAL_UFPSR (0x1U)
8630 
8631 #define CSL_DSS_VID2_PIPE_GO_RESERVED_MASK (0xFFFFFFFEU)
8632 #define CSL_DSS_VID2_PIPE_GO_RESERVED_SHIFT (0x00000001U)
8633 #define CSL_DSS_VID2_PIPE_GO_RESERVED_MAX (0x7FFFFFFFU)
8634 
8635 /**************************************************************************
8636 * Hardware Region : OVR1 Registers
8637 **************************************************************************/
8638 
8639 
8640 /**************************************************************************
8641 * Register Overlay Structure
8642 **************************************************************************/
8643 
8644 typedef struct {
8645  volatile uint32_t CONFIG; /* CONFIG */
8646  volatile uint32_t VIRTUALVP; /* VIRTUALVP */
8647  volatile uint32_t DEFAULT_COLOR; /* DEFAULT_COLOR */
8648  volatile uint32_t DEFAULT_COLOR2; /* DEFAULT_COLOR2 */
8649  volatile uint32_t TRANS_COLOR_MAX; /* TRANS_COLOR_MAX */
8650  volatile uint32_t TRANS_COLOR_MAX2; /* TRANS_COLOR_MAX2 */
8651  volatile uint32_t TRANS_COLOR_MIN; /* TRANS_COLOR_MIN */
8652  volatile uint32_t TRANS_COLOR_MIN2; /* TRANS_COLOR_MIN2 */
8653  volatile uint32_t ATTRIBUTES[5U]; /* ATTRIBUTES 0..4 */
8654  volatile uint32_t ATTRIBUTES2[5U]; /* ATTRIBUTES2 0..4 */
8655  volatile uint32_t SECURE; /* SECURE */
8657 
8658 
8659 /**************************************************************************
8660 * Register Macros
8661 **************************************************************************/
8662 
8663 #define CSL_DSS_OVR1_CONFIG (0x00000000U)
8664 #define CSL_DSS_OVR1_VIRTUALVP (0x00000004U)
8665 #define CSL_DSS_OVR1_DEFAULT_COLOR (0x00000008U)
8666 #define CSL_DSS_OVR1_DEFAULT_COLOR2 (0x0000000CU)
8667 #define CSL_DSS_OVR1_TRANS_COLOR_MAX (0x00000010U)
8668 #define CSL_DSS_OVR1_TRANS_COLOR_MAX2 (0x00000014U)
8669 #define CSL_DSS_OVR1_TRANS_COLOR_MIN (0x00000018U)
8670 #define CSL_DSS_OVR1_TRANS_COLOR_MIN2 (0x0000001CU)
8671 #define CSL_DSS_OVR1_ATTRIBUTES(index) (0x00000020U+((uint32_t)(index)*0x4U))
8672 #define CSL_DSS_OVR1_ATTRIBUTES2(index) (0x00000034U+((uint32_t)(index)*0x4U))
8673 #define CSL_DSS_OVR1_SECURE (0x00000048U)
8674 
8675 /**************************************************************************
8676 * Field Definition Macros
8677 **************************************************************************/
8678 
8679 
8680 /* CONFIG */
8681 
8682 #define CSL_DSS_OVR1_CONFIG_RESERVED6_MASK (0x00000001U)
8683 #define CSL_DSS_OVR1_CONFIG_RESERVED6_SHIFT (0x00000000U)
8684 #define CSL_DSS_OVR1_CONFIG_RESERVED6_MAX (0x00000001U)
8685 
8686 #define CSL_DSS_OVR1_CONFIG_COLORBAREN_MASK (0x00000002U)
8687 #define CSL_DSS_OVR1_CONFIG_COLORBAREN_SHIFT (0x00000001U)
8688 #define CSL_DSS_OVR1_CONFIG_COLORBAREN_MAX (0x00000001U)
8689 
8690 #define CSL_DSS_OVR1_CONFIG_COLORBAREN_VAL_COLORBARDIS (0x0U)
8691 #define CSL_DSS_OVR1_CONFIG_COLORBAREN_VAL_COLORBAREN (0x1U)
8692 
8693 #define CSL_DSS_OVR1_CONFIG_RESERVED_MASK (0x000003FCU)
8694 #define CSL_DSS_OVR1_CONFIG_RESERVED_SHIFT (0x00000002U)
8695 #define CSL_DSS_OVR1_CONFIG_RESERVED_MAX (0x000000FFU)
8696 
8697 #define CSL_DSS_OVR1_CONFIG_TCKLCDENABLE_MASK (0x00000400U)
8698 #define CSL_DSS_OVR1_CONFIG_TCKLCDENABLE_SHIFT (0x0000000AU)
8699 #define CSL_DSS_OVR1_CONFIG_TCKLCDENABLE_MAX (0x00000001U)
8700 
8701 #define CSL_DSS_OVR1_CONFIG_TCKLCDENABLE_VAL_DISTCK (0x0U)
8702 #define CSL_DSS_OVR1_CONFIG_TCKLCDENABLE_VAL_ENBTCK (0x1U)
8703 
8704 #define CSL_DSS_OVR1_CONFIG_TCKLCDSELECTION_MASK (0x00000800U)
8705 #define CSL_DSS_OVR1_CONFIG_TCKLCDSELECTION_SHIFT (0x0000000BU)
8706 #define CSL_DSS_OVR1_CONFIG_TCKLCDSELECTION_MAX (0x00000001U)
8707 
8708 #define CSL_DSS_OVR1_CONFIG_TCKLCDSELECTION_VAL_GDTK (0x0U)
8709 #define CSL_DSS_OVR1_CONFIG_TCKLCDSELECTION_VAL_VSTK (0x1U)
8710 
8711 #define CSL_DSS_OVR1_CONFIG_RESERVED2_MASK (0x00001000U)
8712 #define CSL_DSS_OVR1_CONFIG_RESERVED2_SHIFT (0x0000000CU)
8713 #define CSL_DSS_OVR1_CONFIG_RESERVED2_MAX (0x00000001U)
8714 
8715 #define CSL_DSS_OVR1_CONFIG_RESERVED3_MASK (0x00002000U)
8716 #define CSL_DSS_OVR1_CONFIG_RESERVED3_SHIFT (0x0000000DU)
8717 #define CSL_DSS_OVR1_CONFIG_RESERVED3_MAX (0x00000001U)
8718 
8719 #define CSL_DSS_OVR1_CONFIG_RESERVED1_MASK (0xFFFFC000U)
8720 #define CSL_DSS_OVR1_CONFIG_RESERVED1_SHIFT (0x0000000EU)
8721 #define CSL_DSS_OVR1_CONFIG_RESERVED1_MAX (0x0003FFFFU)
8722 
8723 /* VIRTUALVP */
8724 
8725 #define CSL_DSS_OVR1_VIRTUALVP_PPL_MASK (0x00003FFFU)
8726 #define CSL_DSS_OVR1_VIRTUALVP_PPL_SHIFT (0x00000000U)
8727 #define CSL_DSS_OVR1_VIRTUALVP_PPL_MAX (0x00003FFFU)
8728 
8729 #define CSL_DSS_OVR1_VIRTUALVP_LPP_MASK (0x3FFF0000U)
8730 #define CSL_DSS_OVR1_VIRTUALVP_LPP_SHIFT (0x00000010U)
8731 #define CSL_DSS_OVR1_VIRTUALVP_LPP_MAX (0x00003FFFU)
8732 
8733 #define CSL_DSS_OVR1_VIRTUALVP_ENABLE_MASK (0x80000000U)
8734 #define CSL_DSS_OVR1_VIRTUALVP_ENABLE_SHIFT (0x0000001FU)
8735 #define CSL_DSS_OVR1_VIRTUALVP_ENABLE_MAX (0x00000001U)
8736 
8737 /* DEFAULT_COLOR */
8738 
8739 #define CSL_DSS_OVR1_DEFAULT_COLOR_DEFAULTCOLOR_MASK (0xFFFFFFFFU)
8740 #define CSL_DSS_OVR1_DEFAULT_COLOR_DEFAULTCOLOR_SHIFT (0x00000000U)
8741 #define CSL_DSS_OVR1_DEFAULT_COLOR_DEFAULTCOLOR_MAX (0xFFFFFFFFU)
8742 
8743 /* DEFAULT_COLOR2 */
8744 
8745 #define CSL_DSS_OVR1_DEFAULT_COLOR2_DEFAULTCOLOR_MASK (0x0000FFFFU)
8746 #define CSL_DSS_OVR1_DEFAULT_COLOR2_DEFAULTCOLOR_SHIFT (0x00000000U)
8747 #define CSL_DSS_OVR1_DEFAULT_COLOR2_DEFAULTCOLOR_MAX (0x0000FFFFU)
8748 
8749 #define CSL_DSS_OVR1_DEFAULT_COLOR2_RESERVED_MASK (0xFFFF0000U)
8750 #define CSL_DSS_OVR1_DEFAULT_COLOR2_RESERVED_SHIFT (0x00000010U)
8751 #define CSL_DSS_OVR1_DEFAULT_COLOR2_RESERVED_MAX (0x0000FFFFU)
8752 
8753 /* TRANS_COLOR_MAX */
8754 
8755 #define CSL_DSS_OVR1_TRANS_COLOR_MAX_TRANSCOLORKEY_MASK (0xFFFFFFFFU)
8756 #define CSL_DSS_OVR1_TRANS_COLOR_MAX_TRANSCOLORKEY_SHIFT (0x00000000U)
8757 #define CSL_DSS_OVR1_TRANS_COLOR_MAX_TRANSCOLORKEY_MAX (0xFFFFFFFFU)
8758 
8759 /* TRANS_COLOR_MAX2 */
8760 
8761 #define CSL_DSS_OVR1_TRANS_COLOR_MAX2_TRANSCOLORKEY_MASK (0x0000000FU)
8762 #define CSL_DSS_OVR1_TRANS_COLOR_MAX2_TRANSCOLORKEY_SHIFT (0x00000000U)
8763 #define CSL_DSS_OVR1_TRANS_COLOR_MAX2_TRANSCOLORKEY_MAX (0x0000000FU)
8764 
8765 #define CSL_DSS_OVR1_TRANS_COLOR_MAX2_RESERVED_MASK (0xFFFFFFF0U)
8766 #define CSL_DSS_OVR1_TRANS_COLOR_MAX2_RESERVED_SHIFT (0x00000004U)
8767 #define CSL_DSS_OVR1_TRANS_COLOR_MAX2_RESERVED_MAX (0x0FFFFFFFU)
8768 
8769 /* TRANS_COLOR_MIN */
8770 
8771 #define CSL_DSS_OVR1_TRANS_COLOR_MIN_TRANSCOLORKEY_MASK (0xFFFFFFFFU)
8772 #define CSL_DSS_OVR1_TRANS_COLOR_MIN_TRANSCOLORKEY_SHIFT (0x00000000U)
8773 #define CSL_DSS_OVR1_TRANS_COLOR_MIN_TRANSCOLORKEY_MAX (0xFFFFFFFFU)
8774 
8775 /* TRANS_COLOR_MIN2 */
8776 
8777 #define CSL_DSS_OVR1_TRANS_COLOR_MIN2_TRANSCOLORKEY_MASK (0x0000000FU)
8778 #define CSL_DSS_OVR1_TRANS_COLOR_MIN2_TRANSCOLORKEY_SHIFT (0x00000000U)
8779 #define CSL_DSS_OVR1_TRANS_COLOR_MIN2_TRANSCOLORKEY_MAX (0x0000000FU)
8780 
8781 #define CSL_DSS_OVR1_TRANS_COLOR_MIN2_RESERVED_MASK (0xFFFFFFF0U)
8782 #define CSL_DSS_OVR1_TRANS_COLOR_MIN2_RESERVED_SHIFT (0x00000004U)
8783 #define CSL_DSS_OVR1_TRANS_COLOR_MIN2_RESERVED_MAX (0x0FFFFFFFU)
8784 
8785 /* ATTRIBUTES */
8786 
8787 #define CSL_DSS_OVR1_ATTRIBUTES_ENABLE_MASK (0x00000001U)
8788 #define CSL_DSS_OVR1_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
8789 #define CSL_DSS_OVR1_ATTRIBUTES_ENABLE_MAX (0x00000001U)
8790 
8791 #define CSL_DSS_OVR1_ATTRIBUTES_CHANNELIN_MASK (0x0000001EU)
8792 #define CSL_DSS_OVR1_ATTRIBUTES_CHANNELIN_SHIFT (0x00000001U)
8793 #define CSL_DSS_OVR1_ATTRIBUTES_CHANNELIN_MAX (0x0000000FU)
8794 
8795 #define CSL_DSS_OVR1_ATTRIBUTES_CHANNELIN_VAL_VID1 (0x0U)
8796 #define CSL_DSS_OVR1_ATTRIBUTES_CHANNELIN_VAL_VIDL1 (0x1U)
8797 #define CSL_DSS_OVR1_ATTRIBUTES_CHANNELIN_VAL_VID2 (0x2U)
8798 #define CSL_DSS_OVR1_ATTRIBUTES_CHANNELIN_VAL_VIDL2 (0x3U)
8799 #define CSL_DSS_OVR1_ATTRIBUTES_CHANNELIN_VAL_VIRTCH (0x4U)
8800 
8801 /* ATTRIBUTES2 */
8802 
8803 #define CSL_DSS_OVR1_ATTRIBUTES2_POSX_MASK (0x00003FFFU)
8804 #define CSL_DSS_OVR1_ATTRIBUTES2_POSX_SHIFT (0x00000000U)
8805 #define CSL_DSS_OVR1_ATTRIBUTES2_POSX_MAX (0x00003FFFU)
8806 
8807 #define CSL_DSS_OVR1_ATTRIBUTES2_POSY_MASK (0x3FFF0000U)
8808 #define CSL_DSS_OVR1_ATTRIBUTES2_POSY_SHIFT (0x00000010U)
8809 #define CSL_DSS_OVR1_ATTRIBUTES2_POSY_MAX (0x00003FFFU)
8810 
8811 /* SECURE */
8812 
8813 #define CSL_DSS_OVR1_SECURE_SECURE_MASK (0x00000001U)
8814 #define CSL_DSS_OVR1_SECURE_SECURE_SHIFT (0x00000000U)
8815 #define CSL_DSS_OVR1_SECURE_SECURE_MAX (0x00000001U)
8816 
8817 #define CSL_DSS_OVR1_SECURE_SECURE_VAL_SECUREDIS (0x0U)
8818 #define CSL_DSS_OVR1_SECURE_SECURE_VAL_SECUREEN (0x1U)
8819 
8820 #define CSL_DSS_OVR1_SECURE_RESERVED_MASK (0xFFFFFFFEU)
8821 #define CSL_DSS_OVR1_SECURE_RESERVED_SHIFT (0x00000001U)
8822 #define CSL_DSS_OVR1_SECURE_RESERVED_MAX (0x7FFFFFFFU)
8823 
8824 /**************************************************************************
8825 * Hardware Region : VP1 Registers
8826 **************************************************************************/
8827 
8828 
8829 /**************************************************************************
8830 * Register Overlay Structure
8831 **************************************************************************/
8832 
8833 typedef struct {
8834  volatile uint32_t CONFIG; /* CONFIG */
8835  volatile uint32_t CONTROL; /* CONTROL */
8836  volatile uint32_t CSC_COEF0; /* CSC_COEF0 */
8837  volatile uint32_t CSC_COEF1; /* CSC_COEF1 */
8838  volatile uint32_t CSC_COEF2; /* CSC_COEF2 */
8839  volatile uint32_t DATA_CYCLE_0; /* DATA_CYCLE_0 */
8840  volatile uint32_t DATA_CYCLE_1; /* DATA_CYCLE_1 */
8841  volatile uint32_t DATA_CYCLE_2; /* DATA_CYCLE_2 */
8842  volatile uint8_t Resv_68[36];
8843  volatile uint32_t LINE_NUMBER; /* LINE_NUMBER */
8844  volatile uint8_t Resv_76[4];
8845  volatile uint32_t POL_FREQ; /* POL_FREQ */
8846  volatile uint32_t SIZE_SCREEN; /* SIZE_SCREEN */
8847  volatile uint32_t TIMING_H; /* TIMING_H */
8848  volatile uint32_t TIMING_V; /* TIMING_V */
8849  volatile uint32_t CSC_COEF3; /* CSC_COEF3 */
8850  volatile uint32_t CSC_COEF4; /* CSC_COEF4 */
8851  volatile uint32_t CSC_COEF5; /* CSC_COEF5 */
8852  volatile uint32_t CSC_COEF6; /* CSC_COEF6 */
8853  volatile uint32_t CSC_COEF7; /* CSC_COEF7 */
8854  volatile uint32_t SAFETY_ATTRIBUTES[8U]; /* SAFETY_ATTRIBUTES 0..7 */
8855  volatile uint32_t SAFETY_CAPT_SIGNATURE[8U]; /* SAFETY_CAPT_SIGNATURE 0..7 */
8856  volatile uint32_t SAFETY_POSITION[8U]; /* SAFETY_POSITION 0..7 */
8857  volatile uint32_t SAFETY_REF_SIGNATURE[8U]; /* SAFETY_REF_SIGNATURE 0..7 */
8858  volatile uint32_t SAFETY_SIZE[8U]; /* SAFETY_SIZE 0..7 */
8859  volatile uint32_t SAFETY_LFSR_SEED; /* SAFETY_LFSR_SEED */
8860  volatile uint8_t Resv_288[12];
8861  volatile uint32_t GAMMA_TABLE_0; /* GAMMA_TABLE_0 */
8862  volatile uint32_t GAMMA_TABLE_1; /* GAMMA_TABLE_1 */
8863  volatile uint32_t GAMMA_TABLE_2; /* GAMMA_TABLE_2 */
8864  volatile uint32_t GAMMA_TABLE_3; /* GAMMA_TABLE_3 */
8865  volatile uint32_t GAMMA_TABLE_4; /* GAMMA_TABLE_4 */
8866  volatile uint32_t GAMMA_TABLE_5; /* GAMMA_TABLE_5 */
8867  volatile uint32_t GAMMA_TABLE_6; /* GAMMA_TABLE_6 */
8868  volatile uint32_t GAMMA_TABLE_7; /* GAMMA_TABLE_7 */
8869  volatile uint32_t GAMMA_TABLE_8; /* GAMMA_TABLE_8 */
8870  volatile uint32_t GAMMA_TABLE_9; /* GAMMA_TABLE_9 */
8871  volatile uint32_t GAMMA_TABLE_10; /* GAMMA_TABLE_10 */
8872  volatile uint32_t GAMMA_TABLE_11; /* GAMMA_TABLE_11 */
8873  volatile uint32_t GAMMA_TABLE_12; /* GAMMA_TABLE_12 */
8874  volatile uint32_t GAMMA_TABLE_13; /* GAMMA_TABLE_13 */
8875  volatile uint32_t GAMMA_TABLE_14; /* GAMMA_TABLE_14 */
8876  volatile uint32_t GAMMA_TABLE_15; /* GAMMA_TABLE_15 */
8877  volatile uint32_t DSS_OLDI_CFG; /* DSS_OLDI_CFG */
8878  volatile uint32_t DSS_OLDI_STATUS; /* DSS_OLDI_STATUS */
8879  volatile uint32_t DSS_OLDI_LB; /* DSS_OLDI_LB */
8880  volatile uint8_t Resv_376[12];
8881  volatile uint32_t SECURE; /* SECURE */
8882 } CSL_dss_vp1Regs;
8883 
8884 
8885 /**************************************************************************
8886 * Register Macros
8887 **************************************************************************/
8888 
8889 #define CSL_DSS_VP1_CONFIG (0x00000000U)
8890 #define CSL_DSS_VP1_CONTROL (0x00000004U)
8891 #define CSL_DSS_VP1_CSC_COEF0 (0x00000008U)
8892 #define CSL_DSS_VP1_CSC_COEF1 (0x0000000CU)
8893 #define CSL_DSS_VP1_CSC_COEF2 (0x00000010U)
8894 #define CSL_DSS_VP1_DATA_CYCLE_0 (0x00000014U)
8895 #define CSL_DSS_VP1_DATA_CYCLE_1 (0x00000018U)
8896 #define CSL_DSS_VP1_DATA_CYCLE_2 (0x0000001CU)
8897 #define CSL_DSS_VP1_LINE_NUMBER (0x00000044U)
8898 #define CSL_DSS_VP1_POL_FREQ (0x0000004CU)
8899 #define CSL_DSS_VP1_SIZE_SCREEN (0x00000050U)
8900 #define CSL_DSS_VP1_TIMING_H (0x00000054U)
8901 #define CSL_DSS_VP1_TIMING_V (0x00000058U)
8902 #define CSL_DSS_VP1_CSC_COEF3 (0x0000005CU)
8903 #define CSL_DSS_VP1_CSC_COEF4 (0x00000060U)
8904 #define CSL_DSS_VP1_CSC_COEF5 (0x00000064U)
8905 #define CSL_DSS_VP1_CSC_COEF6 (0x00000068U)
8906 #define CSL_DSS_VP1_CSC_COEF7 (0x0000006CU)
8907 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES(index) (0x00000070U+((uint32_t)(index)*0x4U))
8908 #define CSL_DSS_VP1_SAFETY_CAPT_SIGNATURE(index) (0x00000090U+((uint32_t)(index)*0x4U))
8909 #define CSL_DSS_VP1_SAFETY_POSITION(index) (0x000000B0U+((uint32_t)(index)*0x4U))
8910 #define CSL_DSS_VP1_SAFETY_REF_SIGNATURE(index) (0x000000D0U+((uint32_t)(index)*0x4U))
8911 #define CSL_DSS_VP1_SAFETY_SIZE(index) (0x000000F0U+((uint32_t)(index)*0x4U))
8912 #define CSL_DSS_VP1_SAFETY_LFSR_SEED (0x00000110U)
8913 #define CSL_DSS_VP1_GAMMA_TABLE_0 (0x00000120U)
8914 #define CSL_DSS_VP1_GAMMA_TABLE_1 (0x00000124U)
8915 #define CSL_DSS_VP1_GAMMA_TABLE_2 (0x00000128U)
8916 #define CSL_DSS_VP1_GAMMA_TABLE_3 (0x0000012CU)
8917 #define CSL_DSS_VP1_GAMMA_TABLE_4 (0x00000130U)
8918 #define CSL_DSS_VP1_GAMMA_TABLE_5 (0x00000134U)
8919 #define CSL_DSS_VP1_GAMMA_TABLE_6 (0x00000138U)
8920 #define CSL_DSS_VP1_GAMMA_TABLE_7 (0x0000013CU)
8921 #define CSL_DSS_VP1_GAMMA_TABLE_8 (0x00000140U)
8922 #define CSL_DSS_VP1_GAMMA_TABLE_9 (0x00000144U)
8923 #define CSL_DSS_VP1_GAMMA_TABLE_10 (0x00000148U)
8924 #define CSL_DSS_VP1_GAMMA_TABLE_11 (0x0000014CU)
8925 #define CSL_DSS_VP1_GAMMA_TABLE_12 (0x00000150U)
8926 #define CSL_DSS_VP1_GAMMA_TABLE_13 (0x00000154U)
8927 #define CSL_DSS_VP1_GAMMA_TABLE_14 (0x00000158U)
8928 #define CSL_DSS_VP1_GAMMA_TABLE_15 (0x0000015CU)
8929 #define CSL_DSS_VP1_DSS_OLDI_CFG (0x00000160U)
8930 #define CSL_DSS_VP1_DSS_OLDI_STATUS (0x00000164U)
8931 #define CSL_DSS_VP1_DSS_OLDI_LB (0x00000168U)
8932 #define CSL_DSS_VP1_SECURE (0x00000178U)
8933 
8934 /**************************************************************************
8935 * Field Definition Macros
8936 **************************************************************************/
8937 
8938 
8939 /* CONFIG */
8940 
8941 #define CSL_DSS_VP1_CONFIG_PIXELGATED_MASK (0x00000001U)
8942 #define CSL_DSS_VP1_CONFIG_PIXELGATED_SHIFT (0x00000000U)
8943 #define CSL_DSS_VP1_CONFIG_PIXELGATED_MAX (0x00000001U)
8944 
8945 #define CSL_DSS_VP1_CONFIG_PIXELGATED_VAL_PCLKTOGA (0x0U)
8946 #define CSL_DSS_VP1_CONFIG_PIXELGATED_VAL_PCLKTOGV (0x1U)
8947 
8948 #define CSL_DSS_VP1_CONFIG_DATAENABLEGATED_MASK (0x00000002U)
8949 #define CSL_DSS_VP1_CONFIG_DATAENABLEGATED_SHIFT (0x00000001U)
8950 #define CSL_DSS_VP1_CONFIG_DATAENABLEGATED_MAX (0x00000001U)
8951 
8952 #define CSL_DSS_VP1_CONFIG_DATAENABLEGATED_VAL_DEGDIS (0x0U)
8953 #define CSL_DSS_VP1_CONFIG_DATAENABLEGATED_VAL_DEGENB (0x1U)
8954 
8955 #define CSL_DSS_VP1_CONFIG_GAMMAENABLE_MASK (0x00000004U)
8956 #define CSL_DSS_VP1_CONFIG_GAMMAENABLE_SHIFT (0x00000002U)
8957 #define CSL_DSS_VP1_CONFIG_GAMMAENABLE_MAX (0x00000001U)
8958 
8959 #define CSL_DSS_VP1_CONFIG_GAMMAENABLE_VAL_GAMMADIS (0x0U)
8960 #define CSL_DSS_VP1_CONFIG_GAMMAENABLE_VAL_GAMMAENB (0x1U)
8961 
8962 #define CSL_DSS_VP1_CONFIG_HDMIMODE_MASK (0x00000008U)
8963 #define CSL_DSS_VP1_CONFIG_HDMIMODE_SHIFT (0x00000003U)
8964 #define CSL_DSS_VP1_CONFIG_HDMIMODE_MAX (0x00000001U)
8965 
8966 #define CSL_DSS_VP1_CONFIG_PIXELDATAGATED_MASK (0x00000010U)
8967 #define CSL_DSS_VP1_CONFIG_PIXELDATAGATED_SHIFT (0x00000004U)
8968 #define CSL_DSS_VP1_CONFIG_PIXELDATAGATED_MAX (0x00000001U)
8969 
8970 #define CSL_DSS_VP1_CONFIG_PIXELDATAGATED_VAL_PDGDIS (0x0U)
8971 #define CSL_DSS_VP1_CONFIG_PIXELDATAGATED_VAL_PDGENB (0x1U)
8972 
8973 #define CSL_DSS_VP1_CONFIG_PIXELCLOCKGATED_MASK (0x00000020U)
8974 #define CSL_DSS_VP1_CONFIG_PIXELCLOCKGATED_SHIFT (0x00000005U)
8975 #define CSL_DSS_VP1_CONFIG_PIXELCLOCKGATED_MAX (0x00000001U)
8976 
8977 #define CSL_DSS_VP1_CONFIG_PIXELCLOCKGATED_VAL_PCGDIS (0x0U)
8978 #define CSL_DSS_VP1_CONFIG_PIXELCLOCKGATED_VAL_PCGENB (0x1U)
8979 
8980 #define CSL_DSS_VP1_CONFIG_HSYNCGATED_MASK (0x00000040U)
8981 #define CSL_DSS_VP1_CONFIG_HSYNCGATED_SHIFT (0x00000006U)
8982 #define CSL_DSS_VP1_CONFIG_HSYNCGATED_MAX (0x00000001U)
8983 
8984 #define CSL_DSS_VP1_CONFIG_HSYNCGATED_VAL_HGDIS (0x0U)
8985 #define CSL_DSS_VP1_CONFIG_HSYNCGATED_VAL_HGENB (0x1U)
8986 
8987 #define CSL_DSS_VP1_CONFIG_VSYNCGATED_MASK (0x00000080U)
8988 #define CSL_DSS_VP1_CONFIG_VSYNCGATED_SHIFT (0x00000007U)
8989 #define CSL_DSS_VP1_CONFIG_VSYNCGATED_MAX (0x00000001U)
8990 
8991 #define CSL_DSS_VP1_CONFIG_VSYNCGATED_VAL_VGDIS (0x0U)
8992 #define CSL_DSS_VP1_CONFIG_VSYNCGATED_VAL_VGENB (0x1U)
8993 
8994 #define CSL_DSS_VP1_CONFIG_EXTERNALSYNCEN_MASK (0x00000100U)
8995 #define CSL_DSS_VP1_CONFIG_EXTERNALSYNCEN_SHIFT (0x00000008U)
8996 #define CSL_DSS_VP1_CONFIG_EXTERNALSYNCEN_MAX (0x00000001U)
8997 
8998 #define CSL_DSS_VP1_CONFIG_RESERVED1_MASK (0x00007E00U)
8999 #define CSL_DSS_VP1_CONFIG_RESERVED1_SHIFT (0x00000009U)
9000 #define CSL_DSS_VP1_CONFIG_RESERVED1_MAX (0x0000003FU)
9001 
9002 #define CSL_DSS_VP1_CONFIG_CPR_MASK (0x00008000U)
9003 #define CSL_DSS_VP1_CONFIG_CPR_SHIFT (0x0000000FU)
9004 #define CSL_DSS_VP1_CONFIG_CPR_MAX (0x00000001U)
9005 
9006 #define CSL_DSS_VP1_CONFIG_BUFFERHANDSHAKE_MASK (0x00010000U)
9007 #define CSL_DSS_VP1_CONFIG_BUFFERHANDSHAKE_SHIFT (0x00000010U)
9008 #define CSL_DSS_VP1_CONFIG_BUFFERHANDSHAKE_MAX (0x00000001U)
9009 
9010 #define CSL_DSS_VP1_CONFIG_RESERVED2_MASK (0x000E0000U)
9011 #define CSL_DSS_VP1_CONFIG_RESERVED2_SHIFT (0x00000011U)
9012 #define CSL_DSS_VP1_CONFIG_RESERVED2_MAX (0x00000007U)
9013 
9014 #define CSL_DSS_VP1_CONFIG_BT656ENABLE_MASK (0x00100000U)
9015 #define CSL_DSS_VP1_CONFIG_BT656ENABLE_SHIFT (0x00000014U)
9016 #define CSL_DSS_VP1_CONFIG_BT656ENABLE_MAX (0x00000001U)
9017 
9018 #define CSL_DSS_VP1_CONFIG_BT656ENABLE_VAL_DISABLE (0x0U)
9019 #define CSL_DSS_VP1_CONFIG_BT656ENABLE_VAL_ENABLE (0x1U)
9020 
9021 #define CSL_DSS_VP1_CONFIG_BT1120ENABLE_MASK (0x00200000U)
9022 #define CSL_DSS_VP1_CONFIG_BT1120ENABLE_SHIFT (0x00000015U)
9023 #define CSL_DSS_VP1_CONFIG_BT1120ENABLE_MAX (0x00000001U)
9024 
9025 #define CSL_DSS_VP1_CONFIG_BT1120ENABLE_VAL_DISABLE (0x0U)
9026 #define CSL_DSS_VP1_CONFIG_BT1120ENABLE_VAL_ENABLE (0x1U)
9027 
9028 #define CSL_DSS_VP1_CONFIG_OUTPUTMODEENABLE_MASK (0x00400000U)
9029 #define CSL_DSS_VP1_CONFIG_OUTPUTMODEENABLE_SHIFT (0x00000016U)
9030 #define CSL_DSS_VP1_CONFIG_OUTPUTMODEENABLE_MAX (0x00000001U)
9031 
9032 #define CSL_DSS_VP1_CONFIG_OUTPUTMODEENABLE_VAL_DISABLE (0x0U)
9033 #define CSL_DSS_VP1_CONFIG_OUTPUTMODEENABLE_VAL_ENABLE (0x1U)
9034 
9035 #define CSL_DSS_VP1_CONFIG_FIDFIRST_MASK (0x00800000U)
9036 #define CSL_DSS_VP1_CONFIG_FIDFIRST_SHIFT (0x00000017U)
9037 #define CSL_DSS_VP1_CONFIG_FIDFIRST_MAX (0x00000001U)
9038 
9039 #define CSL_DSS_VP1_CONFIG_FIDFIRST_VAL_EVEN (0x0U)
9040 #define CSL_DSS_VP1_CONFIG_FIDFIRST_VAL_ODD (0x1U)
9041 
9042 #define CSL_DSS_VP1_CONFIG_COLORCONVENABLE_MASK (0x01000000U)
9043 #define CSL_DSS_VP1_CONFIG_COLORCONVENABLE_SHIFT (0x00000018U)
9044 #define CSL_DSS_VP1_CONFIG_COLORCONVENABLE_MAX (0x00000001U)
9045 
9046 #define CSL_DSS_VP1_CONFIG_COLORCONVENABLE_VAL_COLSPCDIS (0x0U)
9047 #define CSL_DSS_VP1_CONFIG_COLORCONVENABLE_VAL_COLSPCENB (0x1U)
9048 
9049 #define CSL_DSS_VP1_CONFIG_FULLRANGE_MASK (0x02000000U)
9050 #define CSL_DSS_VP1_CONFIG_FULLRANGE_SHIFT (0x00000019U)
9051 #define CSL_DSS_VP1_CONFIG_FULLRANGE_MAX (0x00000001U)
9052 
9053 #define CSL_DSS_VP1_CONFIG_FULLRANGE_VAL_LIMRANGE (0x0U)
9054 #define CSL_DSS_VP1_CONFIG_FULLRANGE_VAL_FULLRANGE (0x1U)
9055 
9056 #define CSL_DSS_VP1_CONFIG_COLORCONVPOS_MASK (0x04000000U)
9057 #define CSL_DSS_VP1_CONFIG_COLORCONVPOS_SHIFT (0x0000001AU)
9058 #define CSL_DSS_VP1_CONFIG_COLORCONVPOS_MAX (0x00000001U)
9059 
9060 #define CSL_DSS_VP1_CONFIG_COLORCONVPOS_VAL_AFTERGAMMA (0x0U)
9061 #define CSL_DSS_VP1_CONFIG_COLORCONVPOS_VAL_BEFOREGAMMA (0x1U)
9062 
9063 #define CSL_DSS_VP1_CONFIG_RESERVED3_MASK (0xF8000000U)
9064 #define CSL_DSS_VP1_CONFIG_RESERVED3_SHIFT (0x0000001BU)
9065 #define CSL_DSS_VP1_CONFIG_RESERVED3_MAX (0x0000001FU)
9066 
9067 /* CONTROL */
9068 
9069 #define CSL_DSS_VP1_CONTROL_ENABLE_MASK (0x00000001U)
9070 #define CSL_DSS_VP1_CONTROL_ENABLE_SHIFT (0x00000000U)
9071 #define CSL_DSS_VP1_CONTROL_ENABLE_MAX (0x00000001U)
9072 
9073 #define CSL_DSS_VP1_CONTROL_ENABLE_VAL_LCDOPDIS (0x0U)
9074 #define CSL_DSS_VP1_CONTROL_ENABLE_VAL_LCDOPENB (0x1U)
9075 
9076 #define CSL_DSS_VP1_CONTROL_VPPROGLINENUMBERMODULO_MASK (0x00000002U)
9077 #define CSL_DSS_VP1_CONTROL_VPPROGLINENUMBERMODULO_SHIFT (0x00000001U)
9078 #define CSL_DSS_VP1_CONTROL_VPPROGLINENUMBERMODULO_MAX (0x00000001U)
9079 
9080 #define CSL_DSS_VP1_CONTROL_VPPROGLINENUMBERMODULO_VAL_MODDIS (0x0U)
9081 #define CSL_DSS_VP1_CONTROL_VPPROGLINENUMBERMODULO_VAL_MODEN (0x1U)
9082 
9083 #define CSL_DSS_VP1_CONTROL_MONOCOLOR_MASK (0x00000004U)
9084 #define CSL_DSS_VP1_CONTROL_MONOCOLOR_SHIFT (0x00000002U)
9085 #define CSL_DSS_VP1_CONTROL_MONOCOLOR_MAX (0x00000001U)
9086 
9087 #define CSL_DSS_VP1_CONTROL_STN_MASK (0x00000008U)
9088 #define CSL_DSS_VP1_CONTROL_STN_SHIFT (0x00000003U)
9089 #define CSL_DSS_VP1_CONTROL_STN_MAX (0x00000001U)
9090 
9091 #define CSL_DSS_VP1_CONTROL_M8B_MASK (0x00000010U)
9092 #define CSL_DSS_VP1_CONTROL_M8B_SHIFT (0x00000004U)
9093 #define CSL_DSS_VP1_CONTROL_M8B_MAX (0x00000001U)
9094 
9095 #define CSL_DSS_VP1_CONTROL_GOBIT_MASK (0x00000020U)
9096 #define CSL_DSS_VP1_CONTROL_GOBIT_SHIFT (0x00000005U)
9097 #define CSL_DSS_VP1_CONTROL_GOBIT_MAX (0x00000001U)
9098 
9099 #define CSL_DSS_VP1_CONTROL_GOBIT_VAL_HFUISR (0x0U)
9100 #define CSL_DSS_VP1_CONTROL_GOBIT_VAL_UFPSR (0x1U)
9101 
9102 #define CSL_DSS_VP1_CONTROL_DPIENABLE_MASK (0x00000040U)
9103 #define CSL_DSS_VP1_CONTROL_DPIENABLE_SHIFT (0x00000006U)
9104 #define CSL_DSS_VP1_CONTROL_DPIENABLE_MAX (0x00000001U)
9105 
9106 #define CSL_DSS_VP1_CONTROL_DPIENABLE_VAL_DPIOPDIS (0x0U)
9107 #define CSL_DSS_VP1_CONTROL_DPIENABLE_VAL_DPIOPENB (0x1U)
9108 
9109 #define CSL_DSS_VP1_CONTROL_STDITHERENABLE_MASK (0x00000080U)
9110 #define CSL_DSS_VP1_CONTROL_STDITHERENABLE_SHIFT (0x00000007U)
9111 #define CSL_DSS_VP1_CONTROL_STDITHERENABLE_MAX (0x00000001U)
9112 
9113 #define CSL_DSS_VP1_CONTROL_STDITHERENABLE_VAL_STDITHDIS (0x0U)
9114 #define CSL_DSS_VP1_CONTROL_STDITHERENABLE_VAL_STDITHENB (0x1U)
9115 
9116 #define CSL_DSS_VP1_CONTROL_DATALINES_MASK (0x00000700U)
9117 #define CSL_DSS_VP1_CONTROL_DATALINES_SHIFT (0x00000008U)
9118 #define CSL_DSS_VP1_CONTROL_DATALINES_MAX (0x00000007U)
9119 
9120 #define CSL_DSS_VP1_CONTROL_DATALINES_VAL_OALSB12B (0x0U)
9121 #define CSL_DSS_VP1_CONTROL_DATALINES_VAL_OALSB16B (0x1U)
9122 #define CSL_DSS_VP1_CONTROL_DATALINES_VAL_OALSB18B (0x2U)
9123 #define CSL_DSS_VP1_CONTROL_DATALINES_VAL_OALSB24B (0x3U)
9124 #define CSL_DSS_VP1_CONTROL_DATALINES_VAL_OALSB30B (0x4U)
9125 #define CSL_DSS_VP1_CONTROL_DATALINES_VAL_OALSB36B (0x5U)
9126 
9127 #define CSL_DSS_VP1_CONTROL_STALLMODE_MASK (0x00000800U)
9128 #define CSL_DSS_VP1_CONTROL_STALLMODE_SHIFT (0x0000000BU)
9129 #define CSL_DSS_VP1_CONTROL_STALLMODE_MAX (0x00000001U)
9130 
9131 #define CSL_DSS_VP1_CONTROL_STALLMODE_VAL_STALLDIS (0x0U)
9132 #define CSL_DSS_VP1_CONTROL_STALLMODE_VAL_STALLENB (0x1U)
9133 
9134 #define CSL_DSS_VP1_CONTROL_STALLMODETYPE_MASK (0x00001000U)
9135 #define CSL_DSS_VP1_CONTROL_STALLMODETYPE_SHIFT (0x0000000CU)
9136 #define CSL_DSS_VP1_CONTROL_STALLMODETYPE_MAX (0x00000001U)
9137 
9138 #define CSL_DSS_VP1_CONTROL_STALLMODETYPE_VAL_COMMANDMODE (0x0U)
9139 #define CSL_DSS_VP1_CONTROL_STALLMODETYPE_VAL_VIDEOMODE (0x1U)
9140 
9141 #define CSL_DSS_VP1_CONTROL_RESERVED3_MASK (0x00002000U)
9142 #define CSL_DSS_VP1_CONTROL_RESERVED3_SHIFT (0x0000000DU)
9143 #define CSL_DSS_VP1_CONTROL_RESERVED3_MAX (0x00000001U)
9144 
9145 #define CSL_DSS_VP1_CONTROL_HT_MASK (0x0001C000U)
9146 #define CSL_DSS_VP1_CONTROL_HT_SHIFT (0x0000000EU)
9147 #define CSL_DSS_VP1_CONTROL_HT_MAX (0x00000007U)
9148 
9149 #define CSL_DSS_VP1_CONTROL_RESERVED1_MASK (0x000E0000U)
9150 #define CSL_DSS_VP1_CONTROL_RESERVED1_SHIFT (0x00000011U)
9151 #define CSL_DSS_VP1_CONTROL_RESERVED1_MAX (0x00000007U)
9152 
9153 #define CSL_DSS_VP1_CONTROL_TDMENABLE_MASK (0x00100000U)
9154 #define CSL_DSS_VP1_CONTROL_TDMENABLE_SHIFT (0x00000014U)
9155 #define CSL_DSS_VP1_CONTROL_TDMENABLE_MAX (0x00000001U)
9156 
9157 #define CSL_DSS_VP1_CONTROL_TDMENABLE_VAL_TDMDIS (0x0U)
9158 #define CSL_DSS_VP1_CONTROL_TDMENABLE_VAL_TDMENB (0x1U)
9159 
9160 #define CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_MASK (0x00600000U)
9161 #define CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_SHIFT (0x00000015U)
9162 #define CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_MAX (0x00000003U)
9163 
9164 #define CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_8BPARAINT (0x0U)
9165 #define CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_9BPARAINT (0x1U)
9166 #define CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_12BPARAINT (0x2U)
9167 #define CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_16BPARAINT (0x3U)
9168 
9169 #define CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_MASK (0x01800000U)
9170 #define CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_SHIFT (0x00000017U)
9171 #define CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_MAX (0x00000003U)
9172 
9173 #define CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_1CYCPERPIX (0x0U)
9174 #define CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_2CYCPERPIX (0x1U)
9175 #define CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPERPIX (0x2U)
9176 #define CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPER2PIX (0x3U)
9177 
9178 #define CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_MASK (0x06000000U)
9179 #define CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_SHIFT (0x00000019U)
9180 #define CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_MAX (0x00000003U)
9181 
9182 #define CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_LOWLEVEL (0x0U)
9183 #define CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_HIGHLEVEL (0x1U)
9184 #define CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_UNCHANGED (0x2U)
9185 #define CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_RES (0x3U)
9186 
9187 #define CSL_DSS_VP1_CONTROL_RESERVED_MASK (0x38000000U)
9188 #define CSL_DSS_VP1_CONTROL_RESERVED_SHIFT (0x0000001BU)
9189 #define CSL_DSS_VP1_CONTROL_RESERVED_MAX (0x00000007U)
9190 
9191 #define CSL_DSS_VP1_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_MASK (0xC0000000U)
9192 #define CSL_DSS_VP1_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_SHIFT (0x0000001EU)
9193 #define CSL_DSS_VP1_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_MAX (0x00000003U)
9194 
9195 #define CSL_DSS_VP1_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_ONEFRAME (0x0U)
9196 #define CSL_DSS_VP1_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_TWOFRAMES (0x1U)
9197 #define CSL_DSS_VP1_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_FOURFRAMES (0x2U)
9198 #define CSL_DSS_VP1_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_RESERVED (0x3U)
9199 
9200 /* CSC_COEF0 */
9201 
9202 #define CSL_DSS_VP1_CSC_COEF0_C00_MASK (0x000007FFU)
9203 #define CSL_DSS_VP1_CSC_COEF0_C00_SHIFT (0x00000000U)
9204 #define CSL_DSS_VP1_CSC_COEF0_C00_MAX (0x000007FFU)
9205 
9206 #define CSL_DSS_VP1_CSC_COEF0_RESERVED_53_MASK (0x0000F800U)
9207 #define CSL_DSS_VP1_CSC_COEF0_RESERVED_53_SHIFT (0x0000000BU)
9208 #define CSL_DSS_VP1_CSC_COEF0_RESERVED_53_MAX (0x0000001FU)
9209 
9210 #define CSL_DSS_VP1_CSC_COEF0_C01_MASK (0x07FF0000U)
9211 #define CSL_DSS_VP1_CSC_COEF0_C01_SHIFT (0x00000010U)
9212 #define CSL_DSS_VP1_CSC_COEF0_C01_MAX (0x000007FFU)
9213 
9214 #define CSL_DSS_VP1_CSC_COEF0_RESERVED_52_MASK (0xF8000000U)
9215 #define CSL_DSS_VP1_CSC_COEF0_RESERVED_52_SHIFT (0x0000001BU)
9216 #define CSL_DSS_VP1_CSC_COEF0_RESERVED_52_MAX (0x0000001FU)
9217 
9218 /* CSC_COEF1 */
9219 
9220 #define CSL_DSS_VP1_CSC_COEF1_C02_MASK (0x000007FFU)
9221 #define CSL_DSS_VP1_CSC_COEF1_C02_SHIFT (0x00000000U)
9222 #define CSL_DSS_VP1_CSC_COEF1_C02_MAX (0x000007FFU)
9223 
9224 #define CSL_DSS_VP1_CSC_COEF1_RESERVED_55_MASK (0x0000F800U)
9225 #define CSL_DSS_VP1_CSC_COEF1_RESERVED_55_SHIFT (0x0000000BU)
9226 #define CSL_DSS_VP1_CSC_COEF1_RESERVED_55_MAX (0x0000001FU)
9227 
9228 #define CSL_DSS_VP1_CSC_COEF1_C10_MASK (0x07FF0000U)
9229 #define CSL_DSS_VP1_CSC_COEF1_C10_SHIFT (0x00000010U)
9230 #define CSL_DSS_VP1_CSC_COEF1_C10_MAX (0x000007FFU)
9231 
9232 #define CSL_DSS_VP1_CSC_COEF1_RESERVED_54_MASK (0xF8000000U)
9233 #define CSL_DSS_VP1_CSC_COEF1_RESERVED_54_SHIFT (0x0000001BU)
9234 #define CSL_DSS_VP1_CSC_COEF1_RESERVED_54_MAX (0x0000001FU)
9235 
9236 /* CSC_COEF2 */
9237 
9238 #define CSL_DSS_VP1_CSC_COEF2_C11_MASK (0x000007FFU)
9239 #define CSL_DSS_VP1_CSC_COEF2_C11_SHIFT (0x00000000U)
9240 #define CSL_DSS_VP1_CSC_COEF2_C11_MAX (0x000007FFU)
9241 
9242 #define CSL_DSS_VP1_CSC_COEF2_RESERVED_57_MASK (0x0000F800U)
9243 #define CSL_DSS_VP1_CSC_COEF2_RESERVED_57_SHIFT (0x0000000BU)
9244 #define CSL_DSS_VP1_CSC_COEF2_RESERVED_57_MAX (0x0000001FU)
9245 
9246 #define CSL_DSS_VP1_CSC_COEF2_C12_MASK (0x07FF0000U)
9247 #define CSL_DSS_VP1_CSC_COEF2_C12_SHIFT (0x00000010U)
9248 #define CSL_DSS_VP1_CSC_COEF2_C12_MAX (0x000007FFU)
9249 
9250 #define CSL_DSS_VP1_CSC_COEF2_RESERVED_56_MASK (0xF8000000U)
9251 #define CSL_DSS_VP1_CSC_COEF2_RESERVED_56_SHIFT (0x0000001BU)
9252 #define CSL_DSS_VP1_CSC_COEF2_RESERVED_56_MAX (0x0000001FU)
9253 
9254 /* DATA_CYCLE_0 */
9255 
9256 #define CSL_DSS_VP1_DATA_CYCLE_0_NBBITSPIXEL1_MASK (0x0000001FU)
9257 #define CSL_DSS_VP1_DATA_CYCLE_0_NBBITSPIXEL1_SHIFT (0x00000000U)
9258 #define CSL_DSS_VP1_DATA_CYCLE_0_NBBITSPIXEL1_MAX (0x0000001FU)
9259 
9260 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_4_MASK (0x000000E0U)
9261 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_4_SHIFT (0x00000005U)
9262 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_4_MAX (0x00000007U)
9263 
9264 #define CSL_DSS_VP1_DATA_CYCLE_0_BITALIGNMENTPIXEL1_MASK (0x00000F00U)
9265 #define CSL_DSS_VP1_DATA_CYCLE_0_BITALIGNMENTPIXEL1_SHIFT (0x00000008U)
9266 #define CSL_DSS_VP1_DATA_CYCLE_0_BITALIGNMENTPIXEL1_MAX (0x0000000FU)
9267 
9268 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_3_MASK (0x0000F000U)
9269 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_3_SHIFT (0x0000000CU)
9270 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_3_MAX (0x0000000FU)
9271 
9272 #define CSL_DSS_VP1_DATA_CYCLE_0_NBBITSPIXEL2_MASK (0x001F0000U)
9273 #define CSL_DSS_VP1_DATA_CYCLE_0_NBBITSPIXEL2_SHIFT (0x00000010U)
9274 #define CSL_DSS_VP1_DATA_CYCLE_0_NBBITSPIXEL2_MAX (0x0000001FU)
9275 
9276 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_6_MASK (0x00E00000U)
9277 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_6_SHIFT (0x00000015U)
9278 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_6_MAX (0x00000007U)
9279 
9280 #define CSL_DSS_VP1_DATA_CYCLE_0_BITALIGNMENTPIXEL2_MASK (0x0F000000U)
9281 #define CSL_DSS_VP1_DATA_CYCLE_0_BITALIGNMENTPIXEL2_SHIFT (0x00000018U)
9282 #define CSL_DSS_VP1_DATA_CYCLE_0_BITALIGNMENTPIXEL2_MAX (0x0000000FU)
9283 
9284 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_5_MASK (0xF0000000U)
9285 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_5_SHIFT (0x0000001CU)
9286 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_5_MAX (0x0000000FU)
9287 
9288 /* DATA_CYCLE_1 */
9289 
9290 #define CSL_DSS_VP1_DATA_CYCLE_1_NBBITSPIXEL1_MASK (0x0000001FU)
9291 #define CSL_DSS_VP1_DATA_CYCLE_1_NBBITSPIXEL1_SHIFT (0x00000000U)
9292 #define CSL_DSS_VP1_DATA_CYCLE_1_NBBITSPIXEL1_MAX (0x0000001FU)
9293 
9294 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_4_MASK (0x000000E0U)
9295 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_4_SHIFT (0x00000005U)
9296 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_4_MAX (0x00000007U)
9297 
9298 #define CSL_DSS_VP1_DATA_CYCLE_1_BITALIGNMENTPIXEL1_MASK (0x00000F00U)
9299 #define CSL_DSS_VP1_DATA_CYCLE_1_BITALIGNMENTPIXEL1_SHIFT (0x00000008U)
9300 #define CSL_DSS_VP1_DATA_CYCLE_1_BITALIGNMENTPIXEL1_MAX (0x0000000FU)
9301 
9302 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_3_MASK (0x0000F000U)
9303 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_3_SHIFT (0x0000000CU)
9304 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_3_MAX (0x0000000FU)
9305 
9306 #define CSL_DSS_VP1_DATA_CYCLE_1_NBBITSPIXEL2_MASK (0x001F0000U)
9307 #define CSL_DSS_VP1_DATA_CYCLE_1_NBBITSPIXEL2_SHIFT (0x00000010U)
9308 #define CSL_DSS_VP1_DATA_CYCLE_1_NBBITSPIXEL2_MAX (0x0000001FU)
9309 
9310 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_6_MASK (0x00E00000U)
9311 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_6_SHIFT (0x00000015U)
9312 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_6_MAX (0x00000007U)
9313 
9314 #define CSL_DSS_VP1_DATA_CYCLE_1_BITALIGNMENTPIXEL2_MASK (0x0F000000U)
9315 #define CSL_DSS_VP1_DATA_CYCLE_1_BITALIGNMENTPIXEL2_SHIFT (0x00000018U)
9316 #define CSL_DSS_VP1_DATA_CYCLE_1_BITALIGNMENTPIXEL2_MAX (0x0000000FU)
9317 
9318 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_5_MASK (0xF0000000U)
9319 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_5_SHIFT (0x0000001CU)
9320 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_5_MAX (0x0000000FU)
9321 
9322 /* DATA_CYCLE_2 */
9323 
9324 #define CSL_DSS_VP1_DATA_CYCLE_2_NBBITSPIXEL1_MASK (0x0000001FU)
9325 #define CSL_DSS_VP1_DATA_CYCLE_2_NBBITSPIXEL1_SHIFT (0x00000000U)
9326 #define CSL_DSS_VP1_DATA_CYCLE_2_NBBITSPIXEL1_MAX (0x0000001FU)
9327 
9328 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_4_MASK (0x000000E0U)
9329 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_4_SHIFT (0x00000005U)
9330 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_4_MAX (0x00000007U)
9331 
9332 #define CSL_DSS_VP1_DATA_CYCLE_2_BITALIGNMENTPIXEL1_MASK (0x00000F00U)
9333 #define CSL_DSS_VP1_DATA_CYCLE_2_BITALIGNMENTPIXEL1_SHIFT (0x00000008U)
9334 #define CSL_DSS_VP1_DATA_CYCLE_2_BITALIGNMENTPIXEL1_MAX (0x0000000FU)
9335 
9336 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_3_MASK (0x0000F000U)
9337 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_3_SHIFT (0x0000000CU)
9338 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_3_MAX (0x0000000FU)
9339 
9340 #define CSL_DSS_VP1_DATA_CYCLE_2_NBBITSPIXEL2_MASK (0x001F0000U)
9341 #define CSL_DSS_VP1_DATA_CYCLE_2_NBBITSPIXEL2_SHIFT (0x00000010U)
9342 #define CSL_DSS_VP1_DATA_CYCLE_2_NBBITSPIXEL2_MAX (0x0000001FU)
9343 
9344 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_6_MASK (0x00E00000U)
9345 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_6_SHIFT (0x00000015U)
9346 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_6_MAX (0x00000007U)
9347 
9348 #define CSL_DSS_VP1_DATA_CYCLE_2_BITALIGNMENTPIXEL2_MASK (0x0F000000U)
9349 #define CSL_DSS_VP1_DATA_CYCLE_2_BITALIGNMENTPIXEL2_SHIFT (0x00000018U)
9350 #define CSL_DSS_VP1_DATA_CYCLE_2_BITALIGNMENTPIXEL2_MAX (0x0000000FU)
9351 
9352 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_5_MASK (0xF0000000U)
9353 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_5_SHIFT (0x0000001CU)
9354 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_5_MAX (0x0000000FU)
9355 
9356 /* LINE_NUMBER */
9357 
9358 #define CSL_DSS_VP1_LINE_NUMBER_LINENUMBER_MASK (0x00003FFFU)
9359 #define CSL_DSS_VP1_LINE_NUMBER_LINENUMBER_SHIFT (0x00000000U)
9360 #define CSL_DSS_VP1_LINE_NUMBER_LINENUMBER_MAX (0x00003FFFU)
9361 
9362 #define CSL_DSS_VP1_LINE_NUMBER_RESERVED_MASK (0xFFFFC000U)
9363 #define CSL_DSS_VP1_LINE_NUMBER_RESERVED_SHIFT (0x0000000EU)
9364 #define CSL_DSS_VP1_LINE_NUMBER_RESERVED_MAX (0x0003FFFFU)
9365 
9366 /* POL_FREQ */
9367 
9368 #define CSL_DSS_VP1_POL_FREQ_ACB_MASK (0x000000FFU)
9369 #define CSL_DSS_VP1_POL_FREQ_ACB_SHIFT (0x00000000U)
9370 #define CSL_DSS_VP1_POL_FREQ_ACB_MAX (0x000000FFU)
9371 
9372 #define CSL_DSS_VP1_POL_FREQ_ACBI_MASK (0x00000F00U)
9373 #define CSL_DSS_VP1_POL_FREQ_ACBI_SHIFT (0x00000008U)
9374 #define CSL_DSS_VP1_POL_FREQ_ACBI_MAX (0x0000000FU)
9375 
9376 #define CSL_DSS_VP1_POL_FREQ_IVS_MASK (0x00001000U)
9377 #define CSL_DSS_VP1_POL_FREQ_IVS_SHIFT (0x0000000CU)
9378 #define CSL_DSS_VP1_POL_FREQ_IVS_MAX (0x00000001U)
9379 
9380 #define CSL_DSS_VP1_POL_FREQ_IVS_VAL_FCKPINAH (0x0U)
9381 #define CSL_DSS_VP1_POL_FREQ_IVS_VAL_FCKPINAL (0x1U)
9382 
9383 #define CSL_DSS_VP1_POL_FREQ_IHS_MASK (0x00002000U)
9384 #define CSL_DSS_VP1_POL_FREQ_IHS_SHIFT (0x0000000DU)
9385 #define CSL_DSS_VP1_POL_FREQ_IHS_MAX (0x00000001U)
9386 
9387 #define CSL_DSS_VP1_POL_FREQ_IHS_VAL_LCKPINAH (0x0U)
9388 #define CSL_DSS_VP1_POL_FREQ_IHS_VAL_LCKPINAL (0x1U)
9389 
9390 #define CSL_DSS_VP1_POL_FREQ_IPC_MASK (0x00004000U)
9391 #define CSL_DSS_VP1_POL_FREQ_IPC_SHIFT (0x0000000EU)
9392 #define CSL_DSS_VP1_POL_FREQ_IPC_MAX (0x00000001U)
9393 
9394 #define CSL_DSS_VP1_POL_FREQ_IPC_VAL_DRPCK (0x0U)
9395 #define CSL_DSS_VP1_POL_FREQ_IPC_VAL_DFPCK (0x1U)
9396 
9397 #define CSL_DSS_VP1_POL_FREQ_IEO_MASK (0x00008000U)
9398 #define CSL_DSS_VP1_POL_FREQ_IEO_SHIFT (0x0000000FU)
9399 #define CSL_DSS_VP1_POL_FREQ_IEO_MAX (0x00000001U)
9400 
9401 #define CSL_DSS_VP1_POL_FREQ_IEO_VAL_ACBAHIGH (0x0U)
9402 #define CSL_DSS_VP1_POL_FREQ_IEO_VAL_ACBALOW (0x1U)
9403 
9404 #define CSL_DSS_VP1_POL_FREQ_RF_MASK (0x00010000U)
9405 #define CSL_DSS_VP1_POL_FREQ_RF_SHIFT (0x00000010U)
9406 #define CSL_DSS_VP1_POL_FREQ_RF_MAX (0x00000001U)
9407 
9408 #define CSL_DSS_VP1_POL_FREQ_RF_VAL_DFEDPCK (0x0U)
9409 #define CSL_DSS_VP1_POL_FREQ_RF_VAL_DRIEDPCK (0x1U)
9410 
9411 #define CSL_DSS_VP1_POL_FREQ_ONOFF_MASK (0x00020000U)
9412 #define CSL_DSS_VP1_POL_FREQ_ONOFF_SHIFT (0x00000011U)
9413 #define CSL_DSS_VP1_POL_FREQ_ONOFF_MAX (0x00000001U)
9414 
9415 #define CSL_DSS_VP1_POL_FREQ_ONOFF_VAL_DOPEDPCK (0x0U)
9416 #define CSL_DSS_VP1_POL_FREQ_ONOFF_VAL_DBIT16 (0x1U)
9417 
9418 #define CSL_DSS_VP1_POL_FREQ_ALIGN_MASK (0x00040000U)
9419 #define CSL_DSS_VP1_POL_FREQ_ALIGN_SHIFT (0x00000012U)
9420 #define CSL_DSS_VP1_POL_FREQ_ALIGN_MAX (0x00000001U)
9421 
9422 #define CSL_DSS_VP1_POL_FREQ_ALIGN_VAL_NOTALIGNED (0x0U)
9423 #define CSL_DSS_VP1_POL_FREQ_ALIGN_VAL_ALIGNED (0x1U)
9424 
9425 #define CSL_DSS_VP1_POL_FREQ_RESERVED_MASK (0xFFF80000U)
9426 #define CSL_DSS_VP1_POL_FREQ_RESERVED_SHIFT (0x00000013U)
9427 #define CSL_DSS_VP1_POL_FREQ_RESERVED_MAX (0x00001FFFU)
9428 
9429 /* SIZE_SCREEN */
9430 
9431 #define CSL_DSS_VP1_SIZE_SCREEN_PPL_MASK (0x00003FFFU)
9432 #define CSL_DSS_VP1_SIZE_SCREEN_PPL_SHIFT (0x00000000U)
9433 #define CSL_DSS_VP1_SIZE_SCREEN_PPL_MAX (0x00003FFFU)
9434 
9435 #define CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_MASK (0x0000C000U)
9436 #define CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_SHIFT (0x0000000EU)
9437 #define CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_MAX (0x00000003U)
9438 
9439 #define CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_SAME (0x0U)
9440 #define CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_PLUSONE (0x1U)
9441 #define CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_MINUSONE (0x2U)
9442 
9443 #define CSL_DSS_VP1_SIZE_SCREEN_LPP_MASK (0x3FFF0000U)
9444 #define CSL_DSS_VP1_SIZE_SCREEN_LPP_SHIFT (0x00000010U)
9445 #define CSL_DSS_VP1_SIZE_SCREEN_LPP_MAX (0x00003FFFU)
9446 
9447 /* TIMING_H */
9448 
9449 #define CSL_DSS_VP1_TIMING_H_HSW_MASK (0x000000FFU)
9450 #define CSL_DSS_VP1_TIMING_H_HSW_SHIFT (0x00000000U)
9451 #define CSL_DSS_VP1_TIMING_H_HSW_MAX (0x000000FFU)
9452 
9453 #define CSL_DSS_VP1_TIMING_H_HFP_MASK (0x000FFF00U)
9454 #define CSL_DSS_VP1_TIMING_H_HFP_SHIFT (0x00000008U)
9455 #define CSL_DSS_VP1_TIMING_H_HFP_MAX (0x00000FFFU)
9456 
9457 #define CSL_DSS_VP1_TIMING_H_HBP_MASK (0xFFF00000U)
9458 #define CSL_DSS_VP1_TIMING_H_HBP_SHIFT (0x00000014U)
9459 #define CSL_DSS_VP1_TIMING_H_HBP_MAX (0x00000FFFU)
9460 
9461 /* TIMING_V */
9462 
9463 #define CSL_DSS_VP1_TIMING_V_VSW_MASK (0x000000FFU)
9464 #define CSL_DSS_VP1_TIMING_V_VSW_SHIFT (0x00000000U)
9465 #define CSL_DSS_VP1_TIMING_V_VSW_MAX (0x000000FFU)
9466 
9467 #define CSL_DSS_VP1_TIMING_V_VFP_MASK (0x000FFF00U)
9468 #define CSL_DSS_VP1_TIMING_V_VFP_SHIFT (0x00000008U)
9469 #define CSL_DSS_VP1_TIMING_V_VFP_MAX (0x00000FFFU)
9470 
9471 #define CSL_DSS_VP1_TIMING_V_VBP_MASK (0xFFF00000U)
9472 #define CSL_DSS_VP1_TIMING_V_VBP_SHIFT (0x00000014U)
9473 #define CSL_DSS_VP1_TIMING_V_VBP_MAX (0x00000FFFU)
9474 
9475 /* CSC_COEF3 */
9476 
9477 #define CSL_DSS_VP1_CSC_COEF3_C20_MASK (0x000007FFU)
9478 #define CSL_DSS_VP1_CSC_COEF3_C20_SHIFT (0x00000000U)
9479 #define CSL_DSS_VP1_CSC_COEF3_C20_MAX (0x000007FFU)
9480 
9481 #define CSL_DSS_VP1_CSC_COEF3_RESERVED_59_MASK (0x0000F800U)
9482 #define CSL_DSS_VP1_CSC_COEF3_RESERVED_59_SHIFT (0x0000000BU)
9483 #define CSL_DSS_VP1_CSC_COEF3_RESERVED_59_MAX (0x0000001FU)
9484 
9485 #define CSL_DSS_VP1_CSC_COEF3_C21_MASK (0x07FF0000U)
9486 #define CSL_DSS_VP1_CSC_COEF3_C21_SHIFT (0x00000010U)
9487 #define CSL_DSS_VP1_CSC_COEF3_C21_MAX (0x000007FFU)
9488 
9489 #define CSL_DSS_VP1_CSC_COEF3_RESERVED_58_MASK (0xF8000000U)
9490 #define CSL_DSS_VP1_CSC_COEF3_RESERVED_58_SHIFT (0x0000001BU)
9491 #define CSL_DSS_VP1_CSC_COEF3_RESERVED_58_MAX (0x0000001FU)
9492 
9493 /* CSC_COEF4 */
9494 
9495 #define CSL_DSS_VP1_CSC_COEF4_C22_MASK (0x000007FFU)
9496 #define CSL_DSS_VP1_CSC_COEF4_C22_SHIFT (0x00000000U)
9497 #define CSL_DSS_VP1_CSC_COEF4_C22_MAX (0x000007FFU)
9498 
9499 #define CSL_DSS_VP1_CSC_COEF4_RESERVED_60_MASK (0xFFFFF800U)
9500 #define CSL_DSS_VP1_CSC_COEF4_RESERVED_60_SHIFT (0x0000000BU)
9501 #define CSL_DSS_VP1_CSC_COEF4_RESERVED_60_MAX (0x001FFFFFU)
9502 
9503 /* CSC_COEF5 */
9504 
9505 #define CSL_DSS_VP1_CSC_COEF5_RESERVED_MASK (0x00000007U)
9506 #define CSL_DSS_VP1_CSC_COEF5_RESERVED_SHIFT (0x00000000U)
9507 #define CSL_DSS_VP1_CSC_COEF5_RESERVED_MAX (0x00000007U)
9508 
9509 #define CSL_DSS_VP1_CSC_COEF5_PREOFFSET1_MASK (0x0000FFF8U)
9510 #define CSL_DSS_VP1_CSC_COEF5_PREOFFSET1_SHIFT (0x00000003U)
9511 #define CSL_DSS_VP1_CSC_COEF5_PREOFFSET1_MAX (0x00001FFFU)
9512 
9513 #define CSL_DSS_VP1_CSC_COEF5_RESERVED1_MASK (0x00070000U)
9514 #define CSL_DSS_VP1_CSC_COEF5_RESERVED1_SHIFT (0x00000010U)
9515 #define CSL_DSS_VP1_CSC_COEF5_RESERVED1_MAX (0x00000007U)
9516 
9517 #define CSL_DSS_VP1_CSC_COEF5_PREOFFSET2_MASK (0xFFF80000U)
9518 #define CSL_DSS_VP1_CSC_COEF5_PREOFFSET2_SHIFT (0x00000013U)
9519 #define CSL_DSS_VP1_CSC_COEF5_PREOFFSET2_MAX (0x00001FFFU)
9520 
9521 /* CSC_COEF6 */
9522 
9523 #define CSL_DSS_VP1_CSC_COEF6_RESERVED_MASK (0x00000007U)
9524 #define CSL_DSS_VP1_CSC_COEF6_RESERVED_SHIFT (0x00000000U)
9525 #define CSL_DSS_VP1_CSC_COEF6_RESERVED_MAX (0x00000007U)
9526 
9527 #define CSL_DSS_VP1_CSC_COEF6_PREOFFSET3_MASK (0x0000FFF8U)
9528 #define CSL_DSS_VP1_CSC_COEF6_PREOFFSET3_SHIFT (0x00000003U)
9529 #define CSL_DSS_VP1_CSC_COEF6_PREOFFSET3_MAX (0x00001FFFU)
9530 
9531 #define CSL_DSS_VP1_CSC_COEF6_RESERVED1_MASK (0x00070000U)
9532 #define CSL_DSS_VP1_CSC_COEF6_RESERVED1_SHIFT (0x00000010U)
9533 #define CSL_DSS_VP1_CSC_COEF6_RESERVED1_MAX (0x00000007U)
9534 
9535 #define CSL_DSS_VP1_CSC_COEF6_POSTOFFSET1_MASK (0xFFF80000U)
9536 #define CSL_DSS_VP1_CSC_COEF6_POSTOFFSET1_SHIFT (0x00000013U)
9537 #define CSL_DSS_VP1_CSC_COEF6_POSTOFFSET1_MAX (0x00001FFFU)
9538 
9539 /* CSC_COEF7 */
9540 
9541 #define CSL_DSS_VP1_CSC_COEF7_RESERVED_MASK (0x00000007U)
9542 #define CSL_DSS_VP1_CSC_COEF7_RESERVED_SHIFT (0x00000000U)
9543 #define CSL_DSS_VP1_CSC_COEF7_RESERVED_MAX (0x00000007U)
9544 
9545 #define CSL_DSS_VP1_CSC_COEF7_POSTOFFSET2_MASK (0x0000FFF8U)
9546 #define CSL_DSS_VP1_CSC_COEF7_POSTOFFSET2_SHIFT (0x00000003U)
9547 #define CSL_DSS_VP1_CSC_COEF7_POSTOFFSET2_MAX (0x00001FFFU)
9548 
9549 #define CSL_DSS_VP1_CSC_COEF7_RESERVED1_MASK (0x00070000U)
9550 #define CSL_DSS_VP1_CSC_COEF7_RESERVED1_SHIFT (0x00000010U)
9551 #define CSL_DSS_VP1_CSC_COEF7_RESERVED1_MAX (0x00000007U)
9552 
9553 #define CSL_DSS_VP1_CSC_COEF7_POSTOFFSET3_MASK (0xFFF80000U)
9554 #define CSL_DSS_VP1_CSC_COEF7_POSTOFFSET3_SHIFT (0x00000013U)
9555 #define CSL_DSS_VP1_CSC_COEF7_POSTOFFSET3_MAX (0x00001FFFU)
9556 
9557 /* SAFETY_ATTRIBUTES */
9558 
9559 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_ENABLE_MASK (0x00000001U)
9560 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
9561 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_ENABLE_MAX (0x00000001U)
9562 
9563 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_CAPTUREMODE_MASK (0x00000002U)
9564 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_CAPTUREMODE_SHIFT (0x00000001U)
9565 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_CAPTUREMODE_MAX (0x00000001U)
9566 
9567 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_FRAMEFREEZE (0x0U)
9568 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_DATACHECK (0x1U)
9569 
9570 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_SEEDSELECT_MASK (0x00000004U)
9571 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_SEEDSELECT_SHIFT (0x00000002U)
9572 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_SEEDSELECT_MAX (0x00000001U)
9573 
9574 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_DISABLE (0x0U)
9575 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_ENABLE (0x1U)
9576 
9577 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_THRESHOLD_MASK (0x000007F8U)
9578 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_THRESHOLD_SHIFT (0x00000003U)
9579 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_THRESHOLD_MAX (0x000000FFU)
9580 
9581 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_FRAMESKIP_MASK (0x00001800U)
9582 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_FRAMESKIP_SHIFT (0x0000000BU)
9583 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_FRAMESKIP_MAX (0x00000003U)
9584 
9585 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_NOSKIP (0x0U)
9586 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_EVEN (0x1U)
9587 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_ODD (0x2U)
9588 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_RESERVED (0x3U)
9589 
9590 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_RESERVED_MASK (0xFFFFE000U)
9591 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_RESERVED_SHIFT (0x0000000DU)
9592 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_RESERVED_MAX (0x0007FFFFU)
9593 
9594 /* SAFETY_CAPT_SIGNATURE */
9595 
9596 #define CSL_DSS_VP1_SAFETY_CAPT_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
9597 #define CSL_DSS_VP1_SAFETY_CAPT_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
9598 #define CSL_DSS_VP1_SAFETY_CAPT_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
9599 
9600 /* SAFETY_POSITION */
9601 
9602 #define CSL_DSS_VP1_SAFETY_POSITION_POSX_MASK (0x00003FFFU)
9603 #define CSL_DSS_VP1_SAFETY_POSITION_POSX_SHIFT (0x00000000U)
9604 #define CSL_DSS_VP1_SAFETY_POSITION_POSX_MAX (0x00003FFFU)
9605 
9606 #define CSL_DSS_VP1_SAFETY_POSITION_POSY_MASK (0x3FFF0000U)
9607 #define CSL_DSS_VP1_SAFETY_POSITION_POSY_SHIFT (0x00000010U)
9608 #define CSL_DSS_VP1_SAFETY_POSITION_POSY_MAX (0x00003FFFU)
9609 
9610 /* SAFETY_REF_SIGNATURE */
9611 
9612 #define CSL_DSS_VP1_SAFETY_REF_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
9613 #define CSL_DSS_VP1_SAFETY_REF_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
9614 #define CSL_DSS_VP1_SAFETY_REF_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
9615 
9616 /* SAFETY_SIZE */
9617 
9618 #define CSL_DSS_VP1_SAFETY_SIZE_SIZEX_MASK (0x00003FFFU)
9619 #define CSL_DSS_VP1_SAFETY_SIZE_SIZEX_SHIFT (0x00000000U)
9620 #define CSL_DSS_VP1_SAFETY_SIZE_SIZEX_MAX (0x00003FFFU)
9621 
9622 #define CSL_DSS_VP1_SAFETY_SIZE_SIZEY_MASK (0x3FFF0000U)
9623 #define CSL_DSS_VP1_SAFETY_SIZE_SIZEY_SHIFT (0x00000010U)
9624 #define CSL_DSS_VP1_SAFETY_SIZE_SIZEY_MAX (0x00003FFFU)
9625 
9626 /* SAFETY_LFSR_SEED */
9627 
9628 #define CSL_DSS_VP1_SAFETY_LFSR_SEED_SEED_MASK (0xFFFFFFFFU)
9629 #define CSL_DSS_VP1_SAFETY_LFSR_SEED_SEED_SHIFT (0x00000000U)
9630 #define CSL_DSS_VP1_SAFETY_LFSR_SEED_SEED_MAX (0xFFFFFFFFU)
9631 
9632 /* GAMMA_TABLE_0 */
9633 
9634 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_B_MASK (0x000003FFU)
9635 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_B_SHIFT (0x00000000U)
9636 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_B_MAX (0x000003FFU)
9637 
9638 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_G_MASK (0x000FFC00U)
9639 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_G_SHIFT (0x0000000AU)
9640 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_G_MAX (0x000003FFU)
9641 
9642 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_R_MASK (0x3FF00000U)
9643 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_R_SHIFT (0x00000014U)
9644 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_R_MAX (0x000003FFU)
9645 
9646 #define CSL_DSS_VP1_GAMMA_TABLE_0_INDEX_MASK (0x80000000U)
9647 #define CSL_DSS_VP1_GAMMA_TABLE_0_INDEX_SHIFT (0x0000001FU)
9648 #define CSL_DSS_VP1_GAMMA_TABLE_0_INDEX_MAX (0x00000001U)
9649 
9650 /* GAMMA_TABLE_1 */
9651 
9652 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_B_MASK (0x000003FFU)
9653 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_B_SHIFT (0x00000000U)
9654 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_B_MAX (0x000003FFU)
9655 
9656 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_G_MASK (0x000FFC00U)
9657 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_G_SHIFT (0x0000000AU)
9658 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_G_MAX (0x000003FFU)
9659 
9660 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_R_MASK (0x3FF00000U)
9661 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_R_SHIFT (0x00000014U)
9662 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_R_MAX (0x000003FFU)
9663 
9664 #define CSL_DSS_VP1_GAMMA_TABLE_1_INDEX_MASK (0x80000000U)
9665 #define CSL_DSS_VP1_GAMMA_TABLE_1_INDEX_SHIFT (0x0000001FU)
9666 #define CSL_DSS_VP1_GAMMA_TABLE_1_INDEX_MAX (0x00000001U)
9667 
9668 /* GAMMA_TABLE_2 */
9669 
9670 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_B_MASK (0x000003FFU)
9671 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_B_SHIFT (0x00000000U)
9672 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_B_MAX (0x000003FFU)
9673 
9674 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_G_MASK (0x000FFC00U)
9675 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_G_SHIFT (0x0000000AU)
9676 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_G_MAX (0x000003FFU)
9677 
9678 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_R_MASK (0x3FF00000U)
9679 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_R_SHIFT (0x00000014U)
9680 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_R_MAX (0x000003FFU)
9681 
9682 #define CSL_DSS_VP1_GAMMA_TABLE_2_INDEX_MASK (0x80000000U)
9683 #define CSL_DSS_VP1_GAMMA_TABLE_2_INDEX_SHIFT (0x0000001FU)
9684 #define CSL_DSS_VP1_GAMMA_TABLE_2_INDEX_MAX (0x00000001U)
9685 
9686 /* GAMMA_TABLE_3 */
9687 
9688 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_B_MASK (0x000003FFU)
9689 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_B_SHIFT (0x00000000U)
9690 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_B_MAX (0x000003FFU)
9691 
9692 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_G_MASK (0x000FFC00U)
9693 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_G_SHIFT (0x0000000AU)
9694 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_G_MAX (0x000003FFU)
9695 
9696 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_R_MASK (0x3FF00000U)
9697 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_R_SHIFT (0x00000014U)
9698 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_R_MAX (0x000003FFU)
9699 
9700 #define CSL_DSS_VP1_GAMMA_TABLE_3_INDEX_MASK (0x80000000U)
9701 #define CSL_DSS_VP1_GAMMA_TABLE_3_INDEX_SHIFT (0x0000001FU)
9702 #define CSL_DSS_VP1_GAMMA_TABLE_3_INDEX_MAX (0x00000001U)
9703 
9704 /* GAMMA_TABLE_4 */
9705 
9706 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_B_MASK (0x000003FFU)
9707 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_B_SHIFT (0x00000000U)
9708 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_B_MAX (0x000003FFU)
9709 
9710 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_G_MASK (0x000FFC00U)
9711 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_G_SHIFT (0x0000000AU)
9712 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_G_MAX (0x000003FFU)
9713 
9714 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_R_MASK (0x3FF00000U)
9715 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_R_SHIFT (0x00000014U)
9716 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_R_MAX (0x000003FFU)
9717 
9718 #define CSL_DSS_VP1_GAMMA_TABLE_4_INDEX_MASK (0x80000000U)
9719 #define CSL_DSS_VP1_GAMMA_TABLE_4_INDEX_SHIFT (0x0000001FU)
9720 #define CSL_DSS_VP1_GAMMA_TABLE_4_INDEX_MAX (0x00000001U)
9721 
9722 /* GAMMA_TABLE_5 */
9723 
9724 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_B_MASK (0x000003FFU)
9725 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_B_SHIFT (0x00000000U)
9726 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_B_MAX (0x000003FFU)
9727 
9728 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_G_MASK (0x000FFC00U)
9729 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_G_SHIFT (0x0000000AU)
9730 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_G_MAX (0x000003FFU)
9731 
9732 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_R_MASK (0x3FF00000U)
9733 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_R_SHIFT (0x00000014U)
9734 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_R_MAX (0x000003FFU)
9735 
9736 #define CSL_DSS_VP1_GAMMA_TABLE_5_INDEX_MASK (0x80000000U)
9737 #define CSL_DSS_VP1_GAMMA_TABLE_5_INDEX_SHIFT (0x0000001FU)
9738 #define CSL_DSS_VP1_GAMMA_TABLE_5_INDEX_MAX (0x00000001U)
9739 
9740 /* GAMMA_TABLE_6 */
9741 
9742 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_B_MASK (0x000003FFU)
9743 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_B_SHIFT (0x00000000U)
9744 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_B_MAX (0x000003FFU)
9745 
9746 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_G_MASK (0x000FFC00U)
9747 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_G_SHIFT (0x0000000AU)
9748 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_G_MAX (0x000003FFU)
9749 
9750 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_R_MASK (0x3FF00000U)
9751 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_R_SHIFT (0x00000014U)
9752 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_R_MAX (0x000003FFU)
9753 
9754 #define CSL_DSS_VP1_GAMMA_TABLE_6_INDEX_MASK (0x80000000U)
9755 #define CSL_DSS_VP1_GAMMA_TABLE_6_INDEX_SHIFT (0x0000001FU)
9756 #define CSL_DSS_VP1_GAMMA_TABLE_6_INDEX_MAX (0x00000001U)
9757 
9758 /* GAMMA_TABLE_7 */
9759 
9760 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_B_MASK (0x000003FFU)
9761 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_B_SHIFT (0x00000000U)
9762 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_B_MAX (0x000003FFU)
9763 
9764 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_G_MASK (0x000FFC00U)
9765 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_G_SHIFT (0x0000000AU)
9766 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_G_MAX (0x000003FFU)
9767 
9768 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_R_MASK (0x3FF00000U)
9769 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_R_SHIFT (0x00000014U)
9770 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_R_MAX (0x000003FFU)
9771 
9772 #define CSL_DSS_VP1_GAMMA_TABLE_7_INDEX_MASK (0x80000000U)
9773 #define CSL_DSS_VP1_GAMMA_TABLE_7_INDEX_SHIFT (0x0000001FU)
9774 #define CSL_DSS_VP1_GAMMA_TABLE_7_INDEX_MAX (0x00000001U)
9775 
9776 /* GAMMA_TABLE_8 */
9777 
9778 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_B_MASK (0x000003FFU)
9779 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_B_SHIFT (0x00000000U)
9780 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_B_MAX (0x000003FFU)
9781 
9782 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_G_MASK (0x000FFC00U)
9783 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_G_SHIFT (0x0000000AU)
9784 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_G_MAX (0x000003FFU)
9785 
9786 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_R_MASK (0x3FF00000U)
9787 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_R_SHIFT (0x00000014U)
9788 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_R_MAX (0x000003FFU)
9789 
9790 #define CSL_DSS_VP1_GAMMA_TABLE_8_INDEX_MASK (0x80000000U)
9791 #define CSL_DSS_VP1_GAMMA_TABLE_8_INDEX_SHIFT (0x0000001FU)
9792 #define CSL_DSS_VP1_GAMMA_TABLE_8_INDEX_MAX (0x00000001U)
9793 
9794 /* GAMMA_TABLE_9 */
9795 
9796 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_B_MASK (0x000003FFU)
9797 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_B_SHIFT (0x00000000U)
9798 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_B_MAX (0x000003FFU)
9799 
9800 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_G_MASK (0x000FFC00U)
9801 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_G_SHIFT (0x0000000AU)
9802 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_G_MAX (0x000003FFU)
9803 
9804 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_R_MASK (0x3FF00000U)
9805 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_R_SHIFT (0x00000014U)
9806 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_R_MAX (0x000003FFU)
9807 
9808 #define CSL_DSS_VP1_GAMMA_TABLE_9_INDEX_MASK (0x80000000U)
9809 #define CSL_DSS_VP1_GAMMA_TABLE_9_INDEX_SHIFT (0x0000001FU)
9810 #define CSL_DSS_VP1_GAMMA_TABLE_9_INDEX_MAX (0x00000001U)
9811 
9812 /* GAMMA_TABLE_10 */
9813 
9814 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_B_MASK (0x000003FFU)
9815 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_B_SHIFT (0x00000000U)
9816 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_B_MAX (0x000003FFU)
9817 
9818 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_G_MASK (0x000FFC00U)
9819 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_G_SHIFT (0x0000000AU)
9820 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_G_MAX (0x000003FFU)
9821 
9822 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_R_MASK (0x3FF00000U)
9823 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_R_SHIFT (0x00000014U)
9824 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_R_MAX (0x000003FFU)
9825 
9826 #define CSL_DSS_VP1_GAMMA_TABLE_10_INDEX_MASK (0x80000000U)
9827 #define CSL_DSS_VP1_GAMMA_TABLE_10_INDEX_SHIFT (0x0000001FU)
9828 #define CSL_DSS_VP1_GAMMA_TABLE_10_INDEX_MAX (0x00000001U)
9829 
9830 /* GAMMA_TABLE_11 */
9831 
9832 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_B_MASK (0x000003FFU)
9833 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_B_SHIFT (0x00000000U)
9834 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_B_MAX (0x000003FFU)
9835 
9836 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_G_MASK (0x000FFC00U)
9837 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_G_SHIFT (0x0000000AU)
9838 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_G_MAX (0x000003FFU)
9839 
9840 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_R_MASK (0x3FF00000U)
9841 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_R_SHIFT (0x00000014U)
9842 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_R_MAX (0x000003FFU)
9843 
9844 #define CSL_DSS_VP1_GAMMA_TABLE_11_INDEX_MASK (0x80000000U)
9845 #define CSL_DSS_VP1_GAMMA_TABLE_11_INDEX_SHIFT (0x0000001FU)
9846 #define CSL_DSS_VP1_GAMMA_TABLE_11_INDEX_MAX (0x00000001U)
9847 
9848 /* GAMMA_TABLE_12 */
9849 
9850 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_B_MASK (0x000003FFU)
9851 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_B_SHIFT (0x00000000U)
9852 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_B_MAX (0x000003FFU)
9853 
9854 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_G_MASK (0x000FFC00U)
9855 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_G_SHIFT (0x0000000AU)
9856 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_G_MAX (0x000003FFU)
9857 
9858 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_R_MASK (0x3FF00000U)
9859 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_R_SHIFT (0x00000014U)
9860 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_R_MAX (0x000003FFU)
9861 
9862 #define CSL_DSS_VP1_GAMMA_TABLE_12_INDEX_MASK (0x80000000U)
9863 #define CSL_DSS_VP1_GAMMA_TABLE_12_INDEX_SHIFT (0x0000001FU)
9864 #define CSL_DSS_VP1_GAMMA_TABLE_12_INDEX_MAX (0x00000001U)
9865 
9866 /* GAMMA_TABLE_13 */
9867 
9868 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_B_MASK (0x000003FFU)
9869 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_B_SHIFT (0x00000000U)
9870 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_B_MAX (0x000003FFU)
9871 
9872 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_G_MASK (0x000FFC00U)
9873 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_G_SHIFT (0x0000000AU)
9874 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_G_MAX (0x000003FFU)
9875 
9876 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_R_MASK (0x3FF00000U)
9877 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_R_SHIFT (0x00000014U)
9878 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_R_MAX (0x000003FFU)
9879 
9880 #define CSL_DSS_VP1_GAMMA_TABLE_13_INDEX_MASK (0x80000000U)
9881 #define CSL_DSS_VP1_GAMMA_TABLE_13_INDEX_SHIFT (0x0000001FU)
9882 #define CSL_DSS_VP1_GAMMA_TABLE_13_INDEX_MAX (0x00000001U)
9883 
9884 /* GAMMA_TABLE_14 */
9885 
9886 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_B_MASK (0x000003FFU)
9887 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_B_SHIFT (0x00000000U)
9888 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_B_MAX (0x000003FFU)
9889 
9890 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_G_MASK (0x000FFC00U)
9891 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_G_SHIFT (0x0000000AU)
9892 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_G_MAX (0x000003FFU)
9893 
9894 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_R_MASK (0x3FF00000U)
9895 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_R_SHIFT (0x00000014U)
9896 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_R_MAX (0x000003FFU)
9897 
9898 #define CSL_DSS_VP1_GAMMA_TABLE_14_INDEX_MASK (0x80000000U)
9899 #define CSL_DSS_VP1_GAMMA_TABLE_14_INDEX_SHIFT (0x0000001FU)
9900 #define CSL_DSS_VP1_GAMMA_TABLE_14_INDEX_MAX (0x00000001U)
9901 
9902 /* GAMMA_TABLE_15 */
9903 
9904 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_B_MASK (0x000003FFU)
9905 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_B_SHIFT (0x00000000U)
9906 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_B_MAX (0x000003FFU)
9907 
9908 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_G_MASK (0x000FFC00U)
9909 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_G_SHIFT (0x0000000AU)
9910 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_G_MAX (0x000003FFU)
9911 
9912 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_R_MASK (0x3FF00000U)
9913 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_R_SHIFT (0x00000014U)
9914 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_R_MAX (0x000003FFU)
9915 
9916 #define CSL_DSS_VP1_GAMMA_TABLE_15_INDEX_MASK (0x80000000U)
9917 #define CSL_DSS_VP1_GAMMA_TABLE_15_INDEX_SHIFT (0x0000001FU)
9918 #define CSL_DSS_VP1_GAMMA_TABLE_15_INDEX_MAX (0x00000001U)
9919 
9920 /* DSS_OLDI_CFG */
9921 
9922 #define CSL_DSS_VP1_DSS_OLDI_CFG_RESERVED1_MASK (0x00003FFFU)
9923 #define CSL_DSS_VP1_DSS_OLDI_CFG_RESERVED1_SHIFT (0x00000000U)
9924 #define CSL_DSS_VP1_DSS_OLDI_CFG_RESERVED1_MAX (0x00003FFFU)
9925 
9926 #define CSL_DSS_VP1_DSS_OLDI_CFG_RESERVED_MASK (0xFFFFC000U)
9927 #define CSL_DSS_VP1_DSS_OLDI_CFG_RESERVED_SHIFT (0x0000000EU)
9928 #define CSL_DSS_VP1_DSS_OLDI_CFG_RESERVED_MAX (0x0003FFFFU)
9929 
9930 /* DSS_OLDI_STATUS */
9931 
9932 #define CSL_DSS_VP1_DSS_OLDI_STATUS_RESERVED_MASK (0xFFFFFFFFU)
9933 #define CSL_DSS_VP1_DSS_OLDI_STATUS_RESERVED_SHIFT (0x00000000U)
9934 #define CSL_DSS_VP1_DSS_OLDI_STATUS_RESERVED_MAX (0xFFFFFFFFU)
9935 
9936 /* DSS_OLDI_LB */
9937 
9938 #define CSL_DSS_VP1_DSS_OLDI_LB_RESERVED_MASK (0xFFFFFFFFU)
9939 #define CSL_DSS_VP1_DSS_OLDI_LB_RESERVED_SHIFT (0x00000000U)
9940 #define CSL_DSS_VP1_DSS_OLDI_LB_RESERVED_MAX (0xFFFFFFFFU)
9941 
9942 /* SECURE */
9943 
9944 #define CSL_DSS_VP1_SECURE_SECURE_MASK (0x00000001U)
9945 #define CSL_DSS_VP1_SECURE_SECURE_SHIFT (0x00000000U)
9946 #define CSL_DSS_VP1_SECURE_SECURE_MAX (0x00000001U)
9947 
9948 #define CSL_DSS_VP1_SECURE_SECURE_VAL_SECUREDIS (0x0U)
9949 #define CSL_DSS_VP1_SECURE_SECURE_VAL_SECUREEN (0x1U)
9950 
9951 #define CSL_DSS_VP1_SECURE_RESERVED_MASK (0xFFFFFFFEU)
9952 #define CSL_DSS_VP1_SECURE_RESERVED_SHIFT (0x00000001U)
9953 #define CSL_DSS_VP1_SECURE_RESERVED_MAX (0x7FFFFFFFU)
9954 
9955 /**************************************************************************
9956 * Hardware Region : OVR2 Registers
9957 **************************************************************************/
9958 
9959 
9960 /**************************************************************************
9961 * Register Overlay Structure
9962 **************************************************************************/
9963 
9964 typedef struct {
9965  volatile uint32_t CONFIG; /* CONFIG */
9966  volatile uint32_t VIRTUALVP; /* VIRTUALVP */
9967  volatile uint32_t DEFAULT_COLOR; /* DEFAULT_COLOR */
9968  volatile uint32_t DEFAULT_COLOR2; /* DEFAULT_COLOR2 */
9969  volatile uint32_t TRANS_COLOR_MAX; /* TRANS_COLOR_MAX */
9970  volatile uint32_t TRANS_COLOR_MAX2; /* TRANS_COLOR_MAX2 */
9971  volatile uint32_t TRANS_COLOR_MIN; /* TRANS_COLOR_MIN */
9972  volatile uint32_t TRANS_COLOR_MIN2; /* TRANS_COLOR_MIN2 */
9973  volatile uint32_t ATTRIBUTES[5U]; /* ATTRIBUTES 0..4 */
9974  volatile uint32_t ATTRIBUTES2[5U]; /* ATTRIBUTES2 0..4 */
9975  volatile uint32_t SECURE; /* SECURE */
9977 
9978 
9979 /**************************************************************************
9980 * Register Macros
9981 **************************************************************************/
9982 
9983 #define CSL_DSS_OVR2_CONFIG (0x00000000U)
9984 #define CSL_DSS_OVR2_VIRTUALVP (0x00000004U)
9985 #define CSL_DSS_OVR2_DEFAULT_COLOR (0x00000008U)
9986 #define CSL_DSS_OVR2_DEFAULT_COLOR2 (0x0000000CU)
9987 #define CSL_DSS_OVR2_TRANS_COLOR_MAX (0x00000010U)
9988 #define CSL_DSS_OVR2_TRANS_COLOR_MAX2 (0x00000014U)
9989 #define CSL_DSS_OVR2_TRANS_COLOR_MIN (0x00000018U)
9990 #define CSL_DSS_OVR2_TRANS_COLOR_MIN2 (0x0000001CU)
9991 #define CSL_DSS_OVR2_ATTRIBUTES(index) (0x00000020U+((uint32_t)(index)*0x4U))
9992 #define CSL_DSS_OVR2_ATTRIBUTES2(index) (0x00000034U+((uint32_t)(index)*0x4U))
9993 #define CSL_DSS_OVR2_SECURE (0x00000048U)
9994 
9995 /**************************************************************************
9996 * Field Definition Macros
9997 **************************************************************************/
9998 
9999 
10000 /* CONFIG */
10001 
10002 #define CSL_DSS_OVR2_CONFIG_RESERVED6_MASK (0x00000001U)
10003 #define CSL_DSS_OVR2_CONFIG_RESERVED6_SHIFT (0x00000000U)
10004 #define CSL_DSS_OVR2_CONFIG_RESERVED6_MAX (0x00000001U)
10005 
10006 #define CSL_DSS_OVR2_CONFIG_COLORBAREN_MASK (0x00000002U)
10007 #define CSL_DSS_OVR2_CONFIG_COLORBAREN_SHIFT (0x00000001U)
10008 #define CSL_DSS_OVR2_CONFIG_COLORBAREN_MAX (0x00000001U)
10009 
10010 #define CSL_DSS_OVR2_CONFIG_COLORBAREN_VAL_COLORBARDIS (0x0U)
10011 #define CSL_DSS_OVR2_CONFIG_COLORBAREN_VAL_COLORBAREN (0x1U)
10012 
10013 #define CSL_DSS_OVR2_CONFIG_RESERVED_MASK (0x000003FCU)
10014 #define CSL_DSS_OVR2_CONFIG_RESERVED_SHIFT (0x00000002U)
10015 #define CSL_DSS_OVR2_CONFIG_RESERVED_MAX (0x000000FFU)
10016 
10017 #define CSL_DSS_OVR2_CONFIG_TCKLCDENABLE_MASK (0x00000400U)
10018 #define CSL_DSS_OVR2_CONFIG_TCKLCDENABLE_SHIFT (0x0000000AU)
10019 #define CSL_DSS_OVR2_CONFIG_TCKLCDENABLE_MAX (0x00000001U)
10020 
10021 #define CSL_DSS_OVR2_CONFIG_TCKLCDENABLE_VAL_DISTCK (0x0U)
10022 #define CSL_DSS_OVR2_CONFIG_TCKLCDENABLE_VAL_ENBTCK (0x1U)
10023 
10024 #define CSL_DSS_OVR2_CONFIG_TCKLCDSELECTION_MASK (0x00000800U)
10025 #define CSL_DSS_OVR2_CONFIG_TCKLCDSELECTION_SHIFT (0x0000000BU)
10026 #define CSL_DSS_OVR2_CONFIG_TCKLCDSELECTION_MAX (0x00000001U)
10027 
10028 #define CSL_DSS_OVR2_CONFIG_TCKLCDSELECTION_VAL_GDTK (0x0U)
10029 #define CSL_DSS_OVR2_CONFIG_TCKLCDSELECTION_VAL_VSTK (0x1U)
10030 
10031 #define CSL_DSS_OVR2_CONFIG_RESERVED2_MASK (0x00001000U)
10032 #define CSL_DSS_OVR2_CONFIG_RESERVED2_SHIFT (0x0000000CU)
10033 #define CSL_DSS_OVR2_CONFIG_RESERVED2_MAX (0x00000001U)
10034 
10035 #define CSL_DSS_OVR2_CONFIG_RESERVED3_MASK (0x00002000U)
10036 #define CSL_DSS_OVR2_CONFIG_RESERVED3_SHIFT (0x0000000DU)
10037 #define CSL_DSS_OVR2_CONFIG_RESERVED3_MAX (0x00000001U)
10038 
10039 #define CSL_DSS_OVR2_CONFIG_RESERVED1_MASK (0xFFFFC000U)
10040 #define CSL_DSS_OVR2_CONFIG_RESERVED1_SHIFT (0x0000000EU)
10041 #define CSL_DSS_OVR2_CONFIG_RESERVED1_MAX (0x0003FFFFU)
10042 
10043 /* VIRTUALVP */
10044 
10045 #define CSL_DSS_OVR2_VIRTUALVP_PPL_MASK (0x00003FFFU)
10046 #define CSL_DSS_OVR2_VIRTUALVP_PPL_SHIFT (0x00000000U)
10047 #define CSL_DSS_OVR2_VIRTUALVP_PPL_MAX (0x00003FFFU)
10048 
10049 #define CSL_DSS_OVR2_VIRTUALVP_LPP_MASK (0x3FFF0000U)
10050 #define CSL_DSS_OVR2_VIRTUALVP_LPP_SHIFT (0x00000010U)
10051 #define CSL_DSS_OVR2_VIRTUALVP_LPP_MAX (0x00003FFFU)
10052 
10053 #define CSL_DSS_OVR2_VIRTUALVP_ENABLE_MASK (0x80000000U)
10054 #define CSL_DSS_OVR2_VIRTUALVP_ENABLE_SHIFT (0x0000001FU)
10055 #define CSL_DSS_OVR2_VIRTUALVP_ENABLE_MAX (0x00000001U)
10056 
10057 /* DEFAULT_COLOR */
10058 
10059 #define CSL_DSS_OVR2_DEFAULT_COLOR_DEFAULTCOLOR_MASK (0xFFFFFFFFU)
10060 #define CSL_DSS_OVR2_DEFAULT_COLOR_DEFAULTCOLOR_SHIFT (0x00000000U)
10061 #define CSL_DSS_OVR2_DEFAULT_COLOR_DEFAULTCOLOR_MAX (0xFFFFFFFFU)
10062 
10063 /* DEFAULT_COLOR2 */
10064 
10065 #define CSL_DSS_OVR2_DEFAULT_COLOR2_DEFAULTCOLOR_MASK (0x0000FFFFU)
10066 #define CSL_DSS_OVR2_DEFAULT_COLOR2_DEFAULTCOLOR_SHIFT (0x00000000U)
10067 #define CSL_DSS_OVR2_DEFAULT_COLOR2_DEFAULTCOLOR_MAX (0x0000FFFFU)
10068 
10069 #define CSL_DSS_OVR2_DEFAULT_COLOR2_RESERVED_MASK (0xFFFF0000U)
10070 #define CSL_DSS_OVR2_DEFAULT_COLOR2_RESERVED_SHIFT (0x00000010U)
10071 #define CSL_DSS_OVR2_DEFAULT_COLOR2_RESERVED_MAX (0x0000FFFFU)
10072 
10073 /* TRANS_COLOR_MAX */
10074 
10075 #define CSL_DSS_OVR2_TRANS_COLOR_MAX_TRANSCOLORKEY_MASK (0xFFFFFFFFU)
10076 #define CSL_DSS_OVR2_TRANS_COLOR_MAX_TRANSCOLORKEY_SHIFT (0x00000000U)
10077 #define CSL_DSS_OVR2_TRANS_COLOR_MAX_TRANSCOLORKEY_MAX (0xFFFFFFFFU)
10078 
10079 /* TRANS_COLOR_MAX2 */
10080 
10081 #define CSL_DSS_OVR2_TRANS_COLOR_MAX2_TRANSCOLORKEY_MASK (0x0000000FU)
10082 #define CSL_DSS_OVR2_TRANS_COLOR_MAX2_TRANSCOLORKEY_SHIFT (0x00000000U)
10083 #define CSL_DSS_OVR2_TRANS_COLOR_MAX2_TRANSCOLORKEY_MAX (0x0000000FU)
10084 
10085 #define CSL_DSS_OVR2_TRANS_COLOR_MAX2_RESERVED_MASK (0xFFFFFFF0U)
10086 #define CSL_DSS_OVR2_TRANS_COLOR_MAX2_RESERVED_SHIFT (0x00000004U)
10087 #define CSL_DSS_OVR2_TRANS_COLOR_MAX2_RESERVED_MAX (0x0FFFFFFFU)
10088 
10089 /* TRANS_COLOR_MIN */
10090 
10091 #define CSL_DSS_OVR2_TRANS_COLOR_MIN_TRANSCOLORKEY_MASK (0xFFFFFFFFU)
10092 #define CSL_DSS_OVR2_TRANS_COLOR_MIN_TRANSCOLORKEY_SHIFT (0x00000000U)
10093 #define CSL_DSS_OVR2_TRANS_COLOR_MIN_TRANSCOLORKEY_MAX (0xFFFFFFFFU)
10094 
10095 /* TRANS_COLOR_MIN2 */
10096 
10097 #define CSL_DSS_OVR2_TRANS_COLOR_MIN2_TRANSCOLORKEY_MASK (0x0000000FU)
10098 #define CSL_DSS_OVR2_TRANS_COLOR_MIN2_TRANSCOLORKEY_SHIFT (0x00000000U)
10099 #define CSL_DSS_OVR2_TRANS_COLOR_MIN2_TRANSCOLORKEY_MAX (0x0000000FU)
10100 
10101 #define CSL_DSS_OVR2_TRANS_COLOR_MIN2_RESERVED_MASK (0xFFFFFFF0U)
10102 #define CSL_DSS_OVR2_TRANS_COLOR_MIN2_RESERVED_SHIFT (0x00000004U)
10103 #define CSL_DSS_OVR2_TRANS_COLOR_MIN2_RESERVED_MAX (0x0FFFFFFFU)
10104 
10105 /* ATTRIBUTES */
10106 
10107 #define CSL_DSS_OVR2_ATTRIBUTES_ENABLE_MASK (0x00000001U)
10108 #define CSL_DSS_OVR2_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
10109 #define CSL_DSS_OVR2_ATTRIBUTES_ENABLE_MAX (0x00000001U)
10110 
10111 #define CSL_DSS_OVR2_ATTRIBUTES_CHANNELIN_MASK (0x0000001EU)
10112 #define CSL_DSS_OVR2_ATTRIBUTES_CHANNELIN_SHIFT (0x00000001U)
10113 #define CSL_DSS_OVR2_ATTRIBUTES_CHANNELIN_MAX (0x0000000FU)
10114 
10115 #define CSL_DSS_OVR2_ATTRIBUTES_CHANNELIN_VAL_VID1 (0x0U)
10116 #define CSL_DSS_OVR2_ATTRIBUTES_CHANNELIN_VAL_VIDL1 (0x1U)
10117 #define CSL_DSS_OVR2_ATTRIBUTES_CHANNELIN_VAL_VID2 (0x2U)
10118 #define CSL_DSS_OVR2_ATTRIBUTES_CHANNELIN_VAL_VIDL2 (0x3U)
10119 #define CSL_DSS_OVR2_ATTRIBUTES_CHANNELIN_VAL_VIRTCH (0x4U)
10120 
10121 /* ATTRIBUTES2 */
10122 
10123 #define CSL_DSS_OVR2_ATTRIBUTES2_POSX_MASK (0x00003FFFU)
10124 #define CSL_DSS_OVR2_ATTRIBUTES2_POSX_SHIFT (0x00000000U)
10125 #define CSL_DSS_OVR2_ATTRIBUTES2_POSX_MAX (0x00003FFFU)
10126 
10127 #define CSL_DSS_OVR2_ATTRIBUTES2_POSY_MASK (0x3FFF0000U)
10128 #define CSL_DSS_OVR2_ATTRIBUTES2_POSY_SHIFT (0x00000010U)
10129 #define CSL_DSS_OVR2_ATTRIBUTES2_POSY_MAX (0x00003FFFU)
10130 
10131 /* SECURE */
10132 
10133 #define CSL_DSS_OVR2_SECURE_SECURE_MASK (0x00000001U)
10134 #define CSL_DSS_OVR2_SECURE_SECURE_SHIFT (0x00000000U)
10135 #define CSL_DSS_OVR2_SECURE_SECURE_MAX (0x00000001U)
10136 
10137 #define CSL_DSS_OVR2_SECURE_SECURE_VAL_SECUREDIS (0x0U)
10138 #define CSL_DSS_OVR2_SECURE_SECURE_VAL_SECUREEN (0x1U)
10139 
10140 #define CSL_DSS_OVR2_SECURE_RESERVED_MASK (0xFFFFFFFEU)
10141 #define CSL_DSS_OVR2_SECURE_RESERVED_SHIFT (0x00000001U)
10142 #define CSL_DSS_OVR2_SECURE_RESERVED_MAX (0x7FFFFFFFU)
10143 
10144 /**************************************************************************
10145 * Hardware Region : VP2 Registers
10146 **************************************************************************/
10147 
10148 
10149 /**************************************************************************
10150 * Register Overlay Structure
10151 **************************************************************************/
10152 
10153 typedef struct {
10154  volatile uint32_t CONFIG; /* CONFIG */
10155  volatile uint32_t CONTROL; /* CONTROL */
10156  volatile uint32_t CSC_COEF0; /* CSC_COEF0 */
10157  volatile uint32_t CSC_COEF1; /* CSC_COEF1 */
10158  volatile uint32_t CSC_COEF2; /* CSC_COEF2 */
10159  volatile uint32_t DATA_CYCLE_0; /* DATA_CYCLE_0 */
10160  volatile uint32_t DATA_CYCLE_1; /* DATA_CYCLE_1 */
10161  volatile uint32_t DATA_CYCLE_2; /* DATA_CYCLE_2 */
10162  volatile uint8_t Resv_68[36];
10163  volatile uint32_t LINE_NUMBER; /* LINE_NUMBER */
10164  volatile uint8_t Resv_76[4];
10165  volatile uint32_t POL_FREQ; /* POL_FREQ */
10166  volatile uint32_t SIZE_SCREEN; /* SIZE_SCREEN */
10167  volatile uint32_t TIMING_H; /* TIMING_H */
10168  volatile uint32_t TIMING_V; /* TIMING_V */
10169  volatile uint32_t CSC_COEF3; /* CSC_COEF3 */
10170  volatile uint32_t CSC_COEF4; /* CSC_COEF4 */
10171  volatile uint32_t CSC_COEF5; /* CSC_COEF5 */
10172  volatile uint32_t CSC_COEF6; /* CSC_COEF6 */
10173  volatile uint32_t CSC_COEF7; /* CSC_COEF7 */
10174  volatile uint32_t SAFETY_ATTRIBUTES[8U]; /* SAFETY_ATTRIBUTES 0..7 */
10175  volatile uint32_t SAFETY_CAPT_SIGNATURE[8U]; /* SAFETY_CAPT_SIGNATURE 0..7 */
10176  volatile uint32_t SAFETY_POSITION[8U]; /* SAFETY_POSITION 0..7 */
10177  volatile uint32_t SAFETY_REF_SIGNATURE[8U]; /* SAFETY_REF_SIGNATURE 0..7 */
10178  volatile uint32_t SAFETY_SIZE[8U]; /* SAFETY_SIZE 0..7 */
10179  volatile uint32_t SAFETY_LFSR_SEED; /* SAFETY_LFSR_SEED */
10180  volatile uint8_t Resv_288[12];
10181  volatile uint32_t GAMMA_TABLE_0; /* GAMMA_TABLE_0 */
10182  volatile uint32_t GAMMA_TABLE_1; /* GAMMA_TABLE_1 */
10183  volatile uint32_t GAMMA_TABLE_2; /* GAMMA_TABLE_2 */
10184  volatile uint32_t GAMMA_TABLE_3; /* GAMMA_TABLE_3 */
10185  volatile uint32_t GAMMA_TABLE_4; /* GAMMA_TABLE_4 */
10186  volatile uint32_t GAMMA_TABLE_5; /* GAMMA_TABLE_5 */
10187  volatile uint32_t GAMMA_TABLE_6; /* GAMMA_TABLE_6 */
10188  volatile uint32_t GAMMA_TABLE_7; /* GAMMA_TABLE_7 */
10189  volatile uint32_t GAMMA_TABLE_8; /* GAMMA_TABLE_8 */
10190  volatile uint32_t GAMMA_TABLE_9; /* GAMMA_TABLE_9 */
10191  volatile uint32_t GAMMA_TABLE_10; /* GAMMA_TABLE_10 */
10192  volatile uint32_t GAMMA_TABLE_11; /* GAMMA_TABLE_11 */
10193  volatile uint32_t GAMMA_TABLE_12; /* GAMMA_TABLE_12 */
10194  volatile uint32_t GAMMA_TABLE_13; /* GAMMA_TABLE_13 */
10195  volatile uint32_t GAMMA_TABLE_14; /* GAMMA_TABLE_14 */
10196  volatile uint32_t GAMMA_TABLE_15; /* GAMMA_TABLE_15 */
10197  volatile uint32_t DSS_OLDI_CFG; /* DSS_OLDI_CFG */
10198  volatile uint32_t DSS_OLDI_STATUS; /* DSS_OLDI_STATUS */
10199  volatile uint32_t DSS_OLDI_LB; /* DSS_OLDI_LB */
10200  volatile uint8_t Resv_376[12];
10201  volatile uint32_t SECURE; /* SECURE */
10202 } CSL_dss_vp2Regs;
10203 
10204 
10205 /**************************************************************************
10206 * Register Macros
10207 **************************************************************************/
10208 
10209 #define CSL_DSS_VP2_CONFIG (0x00000000U)
10210 #define CSL_DSS_VP2_CONTROL (0x00000004U)
10211 #define CSL_DSS_VP2_CSC_COEF0 (0x00000008U)
10212 #define CSL_DSS_VP2_CSC_COEF1 (0x0000000CU)
10213 #define CSL_DSS_VP2_CSC_COEF2 (0x00000010U)
10214 #define CSL_DSS_VP2_DATA_CYCLE_0 (0x00000014U)
10215 #define CSL_DSS_VP2_DATA_CYCLE_1 (0x00000018U)
10216 #define CSL_DSS_VP2_DATA_CYCLE_2 (0x0000001CU)
10217 #define CSL_DSS_VP2_LINE_NUMBER (0x00000044U)
10218 #define CSL_DSS_VP2_POL_FREQ (0x0000004CU)
10219 #define CSL_DSS_VP2_SIZE_SCREEN (0x00000050U)
10220 #define CSL_DSS_VP2_TIMING_H (0x00000054U)
10221 #define CSL_DSS_VP2_TIMING_V (0x00000058U)
10222 #define CSL_DSS_VP2_CSC_COEF3 (0x0000005CU)
10223 #define CSL_DSS_VP2_CSC_COEF4 (0x00000060U)
10224 #define CSL_DSS_VP2_CSC_COEF5 (0x00000064U)
10225 #define CSL_DSS_VP2_CSC_COEF6 (0x00000068U)
10226 #define CSL_DSS_VP2_CSC_COEF7 (0x0000006CU)
10227 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES(index) (0x00000070U+((uint32_t)(index)*0x4U))
10228 #define CSL_DSS_VP2_SAFETY_CAPT_SIGNATURE(index) (0x00000090U+((uint32_t)(index)*0x4U))
10229 #define CSL_DSS_VP2_SAFETY_POSITION(index) (0x000000B0U+((uint32_t)(index)*0x4U))
10230 #define CSL_DSS_VP2_SAFETY_REF_SIGNATURE(index) (0x000000D0U+((uint32_t)(index)*0x4U))
10231 #define CSL_DSS_VP2_SAFETY_SIZE(index) (0x000000F0U+((uint32_t)(index)*0x4U))
10232 #define CSL_DSS_VP2_SAFETY_LFSR_SEED (0x00000110U)
10233 #define CSL_DSS_VP2_GAMMA_TABLE_0 (0x00000120U)
10234 #define CSL_DSS_VP2_GAMMA_TABLE_1 (0x00000124U)
10235 #define CSL_DSS_VP2_GAMMA_TABLE_2 (0x00000128U)
10236 #define CSL_DSS_VP2_GAMMA_TABLE_3 (0x0000012CU)
10237 #define CSL_DSS_VP2_GAMMA_TABLE_4 (0x00000130U)
10238 #define CSL_DSS_VP2_GAMMA_TABLE_5 (0x00000134U)
10239 #define CSL_DSS_VP2_GAMMA_TABLE_6 (0x00000138U)
10240 #define CSL_DSS_VP2_GAMMA_TABLE_7 (0x0000013CU)
10241 #define CSL_DSS_VP2_GAMMA_TABLE_8 (0x00000140U)
10242 #define CSL_DSS_VP2_GAMMA_TABLE_9 (0x00000144U)
10243 #define CSL_DSS_VP2_GAMMA_TABLE_10 (0x00000148U)
10244 #define CSL_DSS_VP2_GAMMA_TABLE_11 (0x0000014CU)
10245 #define CSL_DSS_VP2_GAMMA_TABLE_12 (0x00000150U)
10246 #define CSL_DSS_VP2_GAMMA_TABLE_13 (0x00000154U)
10247 #define CSL_DSS_VP2_GAMMA_TABLE_14 (0x00000158U)
10248 #define CSL_DSS_VP2_GAMMA_TABLE_15 (0x0000015CU)
10249 #define CSL_DSS_VP2_DSS_OLDI_CFG (0x00000160U)
10250 #define CSL_DSS_VP2_DSS_OLDI_STATUS (0x00000164U)
10251 #define CSL_DSS_VP2_DSS_OLDI_LB (0x00000168U)
10252 #define CSL_DSS_VP2_SECURE (0x00000178U)
10253 
10254 /**************************************************************************
10255 * Field Definition Macros
10256 **************************************************************************/
10257 
10258 
10259 /* CONFIG */
10260 
10261 #define CSL_DSS_VP2_CONFIG_PIXELGATED_MASK (0x00000001U)
10262 #define CSL_DSS_VP2_CONFIG_PIXELGATED_SHIFT (0x00000000U)
10263 #define CSL_DSS_VP2_CONFIG_PIXELGATED_MAX (0x00000001U)
10264 
10265 #define CSL_DSS_VP2_CONFIG_PIXELGATED_VAL_PCLKTOGA (0x0U)
10266 #define CSL_DSS_VP2_CONFIG_PIXELGATED_VAL_PCLKTOGV (0x1U)
10267 
10268 #define CSL_DSS_VP2_CONFIG_DATAENABLEGATED_MASK (0x00000002U)
10269 #define CSL_DSS_VP2_CONFIG_DATAENABLEGATED_SHIFT (0x00000001U)
10270 #define CSL_DSS_VP2_CONFIG_DATAENABLEGATED_MAX (0x00000001U)
10271 
10272 #define CSL_DSS_VP2_CONFIG_DATAENABLEGATED_VAL_DEGDIS (0x0U)
10273 #define CSL_DSS_VP2_CONFIG_DATAENABLEGATED_VAL_DEGENB (0x1U)
10274 
10275 #define CSL_DSS_VP2_CONFIG_GAMMAENABLE_MASK (0x00000004U)
10276 #define CSL_DSS_VP2_CONFIG_GAMMAENABLE_SHIFT (0x00000002U)
10277 #define CSL_DSS_VP2_CONFIG_GAMMAENABLE_MAX (0x00000001U)
10278 
10279 #define CSL_DSS_VP2_CONFIG_GAMMAENABLE_VAL_GAMMADIS (0x0U)
10280 #define CSL_DSS_VP2_CONFIG_GAMMAENABLE_VAL_GAMMAENB (0x1U)
10281 
10282 #define CSL_DSS_VP2_CONFIG_HDMIMODE_MASK (0x00000008U)
10283 #define CSL_DSS_VP2_CONFIG_HDMIMODE_SHIFT (0x00000003U)
10284 #define CSL_DSS_VP2_CONFIG_HDMIMODE_MAX (0x00000001U)
10285 
10286 #define CSL_DSS_VP2_CONFIG_PIXELDATAGATED_MASK (0x00000010U)
10287 #define CSL_DSS_VP2_CONFIG_PIXELDATAGATED_SHIFT (0x00000004U)
10288 #define CSL_DSS_VP2_CONFIG_PIXELDATAGATED_MAX (0x00000001U)
10289 
10290 #define CSL_DSS_VP2_CONFIG_PIXELDATAGATED_VAL_PDGDIS (0x0U)
10291 #define CSL_DSS_VP2_CONFIG_PIXELDATAGATED_VAL_PDGENB (0x1U)
10292 
10293 #define CSL_DSS_VP2_CONFIG_PIXELCLOCKGATED_MASK (0x00000020U)
10294 #define CSL_DSS_VP2_CONFIG_PIXELCLOCKGATED_SHIFT (0x00000005U)
10295 #define CSL_DSS_VP2_CONFIG_PIXELCLOCKGATED_MAX (0x00000001U)
10296 
10297 #define CSL_DSS_VP2_CONFIG_PIXELCLOCKGATED_VAL_PCGDIS (0x0U)
10298 #define CSL_DSS_VP2_CONFIG_PIXELCLOCKGATED_VAL_PCGENB (0x1U)
10299 
10300 #define CSL_DSS_VP2_CONFIG_HSYNCGATED_MASK (0x00000040U)
10301 #define CSL_DSS_VP2_CONFIG_HSYNCGATED_SHIFT (0x00000006U)
10302 #define CSL_DSS_VP2_CONFIG_HSYNCGATED_MAX (0x00000001U)
10303 
10304 #define CSL_DSS_VP2_CONFIG_HSYNCGATED_VAL_HGDIS (0x0U)
10305 #define CSL_DSS_VP2_CONFIG_HSYNCGATED_VAL_HGENB (0x1U)
10306 
10307 #define CSL_DSS_VP2_CONFIG_VSYNCGATED_MASK (0x00000080U)
10308 #define CSL_DSS_VP2_CONFIG_VSYNCGATED_SHIFT (0x00000007U)
10309 #define CSL_DSS_VP2_CONFIG_VSYNCGATED_MAX (0x00000001U)
10310 
10311 #define CSL_DSS_VP2_CONFIG_VSYNCGATED_VAL_VGDIS (0x0U)
10312 #define CSL_DSS_VP2_CONFIG_VSYNCGATED_VAL_VGENB (0x1U)
10313 
10314 #define CSL_DSS_VP2_CONFIG_EXTERNALSYNCEN_MASK (0x00000100U)
10315 #define CSL_DSS_VP2_CONFIG_EXTERNALSYNCEN_SHIFT (0x00000008U)
10316 #define CSL_DSS_VP2_CONFIG_EXTERNALSYNCEN_MAX (0x00000001U)
10317 
10318 #define CSL_DSS_VP2_CONFIG_RESERVED1_MASK (0x00007E00U)
10319 #define CSL_DSS_VP2_CONFIG_RESERVED1_SHIFT (0x00000009U)
10320 #define CSL_DSS_VP2_CONFIG_RESERVED1_MAX (0x0000003FU)
10321 
10322 #define CSL_DSS_VP2_CONFIG_CPR_MASK (0x00008000U)
10323 #define CSL_DSS_VP2_CONFIG_CPR_SHIFT (0x0000000FU)
10324 #define CSL_DSS_VP2_CONFIG_CPR_MAX (0x00000001U)
10325 
10326 #define CSL_DSS_VP2_CONFIG_BUFFERHANDSHAKE_MASK (0x00010000U)
10327 #define CSL_DSS_VP2_CONFIG_BUFFERHANDSHAKE_SHIFT (0x00000010U)
10328 #define CSL_DSS_VP2_CONFIG_BUFFERHANDSHAKE_MAX (0x00000001U)
10329 
10330 #define CSL_DSS_VP2_CONFIG_RESERVED2_MASK (0x000E0000U)
10331 #define CSL_DSS_VP2_CONFIG_RESERVED2_SHIFT (0x00000011U)
10332 #define CSL_DSS_VP2_CONFIG_RESERVED2_MAX (0x00000007U)
10333 
10334 #define CSL_DSS_VP2_CONFIG_BT656ENABLE_MASK (0x00100000U)
10335 #define CSL_DSS_VP2_CONFIG_BT656ENABLE_SHIFT (0x00000014U)
10336 #define CSL_DSS_VP2_CONFIG_BT656ENABLE_MAX (0x00000001U)
10337 
10338 #define CSL_DSS_VP2_CONFIG_BT656ENABLE_VAL_DISABLE (0x0U)
10339 #define CSL_DSS_VP2_CONFIG_BT656ENABLE_VAL_ENABLE (0x1U)
10340 
10341 #define CSL_DSS_VP2_CONFIG_BT1120ENABLE_MASK (0x00200000U)
10342 #define CSL_DSS_VP2_CONFIG_BT1120ENABLE_SHIFT (0x00000015U)
10343 #define CSL_DSS_VP2_CONFIG_BT1120ENABLE_MAX (0x00000001U)
10344 
10345 #define CSL_DSS_VP2_CONFIG_BT1120ENABLE_VAL_DISABLE (0x0U)
10346 #define CSL_DSS_VP2_CONFIG_BT1120ENABLE_VAL_ENABLE (0x1U)
10347 
10348 #define CSL_DSS_VP2_CONFIG_OUTPUTMODEENABLE_MASK (0x00400000U)
10349 #define CSL_DSS_VP2_CONFIG_OUTPUTMODEENABLE_SHIFT (0x00000016U)
10350 #define CSL_DSS_VP2_CONFIG_OUTPUTMODEENABLE_MAX (0x00000001U)
10351 
10352 #define CSL_DSS_VP2_CONFIG_OUTPUTMODEENABLE_VAL_DISABLE (0x0U)
10353 #define CSL_DSS_VP2_CONFIG_OUTPUTMODEENABLE_VAL_ENABLE (0x1U)
10354 
10355 #define CSL_DSS_VP2_CONFIG_FIDFIRST_MASK (0x00800000U)
10356 #define CSL_DSS_VP2_CONFIG_FIDFIRST_SHIFT (0x00000017U)
10357 #define CSL_DSS_VP2_CONFIG_FIDFIRST_MAX (0x00000001U)
10358 
10359 #define CSL_DSS_VP2_CONFIG_FIDFIRST_VAL_EVEN (0x0U)
10360 #define CSL_DSS_VP2_CONFIG_FIDFIRST_VAL_ODD (0x1U)
10361 
10362 #define CSL_DSS_VP2_CONFIG_COLORCONVENABLE_MASK (0x01000000U)
10363 #define CSL_DSS_VP2_CONFIG_COLORCONVENABLE_SHIFT (0x00000018U)
10364 #define CSL_DSS_VP2_CONFIG_COLORCONVENABLE_MAX (0x00000001U)
10365 
10366 #define CSL_DSS_VP2_CONFIG_COLORCONVENABLE_VAL_COLSPCDIS (0x0U)
10367 #define CSL_DSS_VP2_CONFIG_COLORCONVENABLE_VAL_COLSPCENB (0x1U)
10368 
10369 #define CSL_DSS_VP2_CONFIG_FULLRANGE_MASK (0x02000000U)
10370 #define CSL_DSS_VP2_CONFIG_FULLRANGE_SHIFT (0x00000019U)
10371 #define CSL_DSS_VP2_CONFIG_FULLRANGE_MAX (0x00000001U)
10372 
10373 #define CSL_DSS_VP2_CONFIG_FULLRANGE_VAL_LIMRANGE (0x0U)
10374 #define CSL_DSS_VP2_CONFIG_FULLRANGE_VAL_FULLRANGE (0x1U)
10375 
10376 #define CSL_DSS_VP2_CONFIG_COLORCONVPOS_MASK (0x04000000U)
10377 #define CSL_DSS_VP2_CONFIG_COLORCONVPOS_SHIFT (0x0000001AU)
10378 #define CSL_DSS_VP2_CONFIG_COLORCONVPOS_MAX (0x00000001U)
10379 
10380 #define CSL_DSS_VP2_CONFIG_COLORCONVPOS_VAL_AFTERGAMMA (0x0U)
10381 #define CSL_DSS_VP2_CONFIG_COLORCONVPOS_VAL_BEFOREGAMMA (0x1U)
10382 
10383 #define CSL_DSS_VP2_CONFIG_RESERVED3_MASK (0xF8000000U)
10384 #define CSL_DSS_VP2_CONFIG_RESERVED3_SHIFT (0x0000001BU)
10385 #define CSL_DSS_VP2_CONFIG_RESERVED3_MAX (0x0000001FU)
10386 
10387 /* CONTROL */
10388 
10389 #define CSL_DSS_VP2_CONTROL_ENABLE_MASK (0x00000001U)
10390 #define CSL_DSS_VP2_CONTROL_ENABLE_SHIFT (0x00000000U)
10391 #define CSL_DSS_VP2_CONTROL_ENABLE_MAX (0x00000001U)
10392 
10393 #define CSL_DSS_VP2_CONTROL_ENABLE_VAL_LCDOPDIS (0x0U)
10394 #define CSL_DSS_VP2_CONTROL_ENABLE_VAL_LCDOPENB (0x1U)
10395 
10396 #define CSL_DSS_VP2_CONTROL_VPPROGLINENUMBERMODULO_MASK (0x00000002U)
10397 #define CSL_DSS_VP2_CONTROL_VPPROGLINENUMBERMODULO_SHIFT (0x00000001U)
10398 #define CSL_DSS_VP2_CONTROL_VPPROGLINENUMBERMODULO_MAX (0x00000001U)
10399 
10400 #define CSL_DSS_VP2_CONTROL_VPPROGLINENUMBERMODULO_VAL_MODDIS (0x0U)
10401 #define CSL_DSS_VP2_CONTROL_VPPROGLINENUMBERMODULO_VAL_MODEN (0x1U)
10402 
10403 #define CSL_DSS_VP2_CONTROL_MONOCOLOR_MASK (0x00000004U)
10404 #define CSL_DSS_VP2_CONTROL_MONOCOLOR_SHIFT (0x00000002U)
10405 #define CSL_DSS_VP2_CONTROL_MONOCOLOR_MAX (0x00000001U)
10406 
10407 #define CSL_DSS_VP2_CONTROL_STN_MASK (0x00000008U)
10408 #define CSL_DSS_VP2_CONTROL_STN_SHIFT (0x00000003U)
10409 #define CSL_DSS_VP2_CONTROL_STN_MAX (0x00000001U)
10410 
10411 #define CSL_DSS_VP2_CONTROL_M8B_MASK (0x00000010U)
10412 #define CSL_DSS_VP2_CONTROL_M8B_SHIFT (0x00000004U)
10413 #define CSL_DSS_VP2_CONTROL_M8B_MAX (0x00000001U)
10414 
10415 #define CSL_DSS_VP2_CONTROL_GOBIT_MASK (0x00000020U)
10416 #define CSL_DSS_VP2_CONTROL_GOBIT_SHIFT (0x00000005U)
10417 #define CSL_DSS_VP2_CONTROL_GOBIT_MAX (0x00000001U)
10418 
10419 #define CSL_DSS_VP2_CONTROL_GOBIT_VAL_HFUISR (0x0U)
10420 #define CSL_DSS_VP2_CONTROL_GOBIT_VAL_UFPSR (0x1U)
10421 
10422 #define CSL_DSS_VP2_CONTROL_DPIENABLE_MASK (0x00000040U)
10423 #define CSL_DSS_VP2_CONTROL_DPIENABLE_SHIFT (0x00000006U)
10424 #define CSL_DSS_VP2_CONTROL_DPIENABLE_MAX (0x00000001U)
10425 
10426 #define CSL_DSS_VP2_CONTROL_DPIENABLE_VAL_DPIOPDIS (0x0U)
10427 #define CSL_DSS_VP2_CONTROL_DPIENABLE_VAL_DPIOPENB (0x1U)
10428 
10429 #define CSL_DSS_VP2_CONTROL_STDITHERENABLE_MASK (0x00000080U)
10430 #define CSL_DSS_VP2_CONTROL_STDITHERENABLE_SHIFT (0x00000007U)
10431 #define CSL_DSS_VP2_CONTROL_STDITHERENABLE_MAX (0x00000001U)
10432 
10433 #define CSL_DSS_VP2_CONTROL_STDITHERENABLE_VAL_STDITHDIS (0x0U)
10434 #define CSL_DSS_VP2_CONTROL_STDITHERENABLE_VAL_STDITHENB (0x1U)
10435 
10436 #define CSL_DSS_VP2_CONTROL_DATALINES_MASK (0x00000700U)
10437 #define CSL_DSS_VP2_CONTROL_DATALINES_SHIFT (0x00000008U)
10438 #define CSL_DSS_VP2_CONTROL_DATALINES_MAX (0x00000007U)
10439 
10440 #define CSL_DSS_VP2_CONTROL_DATALINES_VAL_OALSB12B (0x0U)
10441 #define CSL_DSS_VP2_CONTROL_DATALINES_VAL_OALSB16B (0x1U)
10442 #define CSL_DSS_VP2_CONTROL_DATALINES_VAL_OALSB18B (0x2U)
10443 #define CSL_DSS_VP2_CONTROL_DATALINES_VAL_OALSB24B (0x3U)
10444 #define CSL_DSS_VP2_CONTROL_DATALINES_VAL_OALSB30B (0x4U)
10445 #define CSL_DSS_VP2_CONTROL_DATALINES_VAL_OALSB36B (0x5U)
10446 
10447 #define CSL_DSS_VP2_CONTROL_STALLMODE_MASK (0x00000800U)
10448 #define CSL_DSS_VP2_CONTROL_STALLMODE_SHIFT (0x0000000BU)
10449 #define CSL_DSS_VP2_CONTROL_STALLMODE_MAX (0x00000001U)
10450 
10451 #define CSL_DSS_VP2_CONTROL_STALLMODE_VAL_STALLDIS (0x0U)
10452 #define CSL_DSS_VP2_CONTROL_STALLMODE_VAL_STALLENB (0x1U)
10453 
10454 #define CSL_DSS_VP2_CONTROL_STALLMODETYPE_MASK (0x00001000U)
10455 #define CSL_DSS_VP2_CONTROL_STALLMODETYPE_SHIFT (0x0000000CU)
10456 #define CSL_DSS_VP2_CONTROL_STALLMODETYPE_MAX (0x00000001U)
10457 
10458 #define CSL_DSS_VP2_CONTROL_STALLMODETYPE_VAL_COMMANDMODE (0x0U)
10459 #define CSL_DSS_VP2_CONTROL_STALLMODETYPE_VAL_VIDEOMODE (0x1U)
10460 
10461 #define CSL_DSS_VP2_CONTROL_RESERVED3_MASK (0x00002000U)
10462 #define CSL_DSS_VP2_CONTROL_RESERVED3_SHIFT (0x0000000DU)
10463 #define CSL_DSS_VP2_CONTROL_RESERVED3_MAX (0x00000001U)
10464 
10465 #define CSL_DSS_VP2_CONTROL_HT_MASK (0x0001C000U)
10466 #define CSL_DSS_VP2_CONTROL_HT_SHIFT (0x0000000EU)
10467 #define CSL_DSS_VP2_CONTROL_HT_MAX (0x00000007U)
10468 
10469 #define CSL_DSS_VP2_CONTROL_RESERVED1_MASK (0x000E0000U)
10470 #define CSL_DSS_VP2_CONTROL_RESERVED1_SHIFT (0x00000011U)
10471 #define CSL_DSS_VP2_CONTROL_RESERVED1_MAX (0x00000007U)
10472 
10473 #define CSL_DSS_VP2_CONTROL_TDMENABLE_MASK (0x00100000U)
10474 #define CSL_DSS_VP2_CONTROL_TDMENABLE_SHIFT (0x00000014U)
10475 #define CSL_DSS_VP2_CONTROL_TDMENABLE_MAX (0x00000001U)
10476 
10477 #define CSL_DSS_VP2_CONTROL_TDMENABLE_VAL_TDMDIS (0x0U)
10478 #define CSL_DSS_VP2_CONTROL_TDMENABLE_VAL_TDMENB (0x1U)
10479 
10480 #define CSL_DSS_VP2_CONTROL_TDMPARALLELMODE_MASK (0x00600000U)
10481 #define CSL_DSS_VP2_CONTROL_TDMPARALLELMODE_SHIFT (0x00000015U)
10482 #define CSL_DSS_VP2_CONTROL_TDMPARALLELMODE_MAX (0x00000003U)
10483 
10484 #define CSL_DSS_VP2_CONTROL_TDMPARALLELMODE_VAL_8BPARAINT (0x0U)
10485 #define CSL_DSS_VP2_CONTROL_TDMPARALLELMODE_VAL_9BPARAINT (0x1U)
10486 #define CSL_DSS_VP2_CONTROL_TDMPARALLELMODE_VAL_12BPARAINT (0x2U)
10487 #define CSL_DSS_VP2_CONTROL_TDMPARALLELMODE_VAL_16BPARAINT (0x3U)
10488 
10489 #define CSL_DSS_VP2_CONTROL_TDMCYCLEFORMAT_MASK (0x01800000U)
10490 #define CSL_DSS_VP2_CONTROL_TDMCYCLEFORMAT_SHIFT (0x00000017U)
10491 #define CSL_DSS_VP2_CONTROL_TDMCYCLEFORMAT_MAX (0x00000003U)
10492 
10493 #define CSL_DSS_VP2_CONTROL_TDMCYCLEFORMAT_VAL_1CYCPERPIX (0x0U)
10494 #define CSL_DSS_VP2_CONTROL_TDMCYCLEFORMAT_VAL_2CYCPERPIX (0x1U)
10495 #define CSL_DSS_VP2_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPERPIX (0x2U)
10496 #define CSL_DSS_VP2_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPER2PIX (0x3U)
10497 
10498 #define CSL_DSS_VP2_CONTROL_TDMUNUSEDBITS_MASK (0x06000000U)
10499 #define CSL_DSS_VP2_CONTROL_TDMUNUSEDBITS_SHIFT (0x00000019U)
10500 #define CSL_DSS_VP2_CONTROL_TDMUNUSEDBITS_MAX (0x00000003U)
10501 
10502 #define CSL_DSS_VP2_CONTROL_TDMUNUSEDBITS_VAL_LOWLEVEL (0x0U)
10503 #define CSL_DSS_VP2_CONTROL_TDMUNUSEDBITS_VAL_HIGHLEVEL (0x1U)
10504 #define CSL_DSS_VP2_CONTROL_TDMUNUSEDBITS_VAL_UNCHANGED (0x2U)
10505 #define CSL_DSS_VP2_CONTROL_TDMUNUSEDBITS_VAL_RES (0x3U)
10506 
10507 #define CSL_DSS_VP2_CONTROL_RESERVED_MASK (0x38000000U)
10508 #define CSL_DSS_VP2_CONTROL_RESERVED_SHIFT (0x0000001BU)
10509 #define CSL_DSS_VP2_CONTROL_RESERVED_MAX (0x00000007U)
10510 
10511 #define CSL_DSS_VP2_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_MASK (0xC0000000U)
10512 #define CSL_DSS_VP2_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_SHIFT (0x0000001EU)
10513 #define CSL_DSS_VP2_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_MAX (0x00000003U)
10514 
10515 #define CSL_DSS_VP2_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_ONEFRAME (0x0U)
10516 #define CSL_DSS_VP2_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_TWOFRAMES (0x1U)
10517 #define CSL_DSS_VP2_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_FOURFRAMES (0x2U)
10518 #define CSL_DSS_VP2_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_RESERVED (0x3U)
10519 
10520 /* CSC_COEF0 */
10521 
10522 #define CSL_DSS_VP2_CSC_COEF0_C00_MASK (0x000007FFU)
10523 #define CSL_DSS_VP2_CSC_COEF0_C00_SHIFT (0x00000000U)
10524 #define CSL_DSS_VP2_CSC_COEF0_C00_MAX (0x000007FFU)
10525 
10526 #define CSL_DSS_VP2_CSC_COEF0_RESERVED_53_MASK (0x0000F800U)
10527 #define CSL_DSS_VP2_CSC_COEF0_RESERVED_53_SHIFT (0x0000000BU)
10528 #define CSL_DSS_VP2_CSC_COEF0_RESERVED_53_MAX (0x0000001FU)
10529 
10530 #define CSL_DSS_VP2_CSC_COEF0_C01_MASK (0x07FF0000U)
10531 #define CSL_DSS_VP2_CSC_COEF0_C01_SHIFT (0x00000010U)
10532 #define CSL_DSS_VP2_CSC_COEF0_C01_MAX (0x000007FFU)
10533 
10534 #define CSL_DSS_VP2_CSC_COEF0_RESERVED_52_MASK (0xF8000000U)
10535 #define CSL_DSS_VP2_CSC_COEF0_RESERVED_52_SHIFT (0x0000001BU)
10536 #define CSL_DSS_VP2_CSC_COEF0_RESERVED_52_MAX (0x0000001FU)
10537 
10538 /* CSC_COEF1 */
10539 
10540 #define CSL_DSS_VP2_CSC_COEF1_C02_MASK (0x000007FFU)
10541 #define CSL_DSS_VP2_CSC_COEF1_C02_SHIFT (0x00000000U)
10542 #define CSL_DSS_VP2_CSC_COEF1_C02_MAX (0x000007FFU)
10543 
10544 #define CSL_DSS_VP2_CSC_COEF1_RESERVED_55_MASK (0x0000F800U)
10545 #define CSL_DSS_VP2_CSC_COEF1_RESERVED_55_SHIFT (0x0000000BU)
10546 #define CSL_DSS_VP2_CSC_COEF1_RESERVED_55_MAX (0x0000001FU)
10547 
10548 #define CSL_DSS_VP2_CSC_COEF1_C10_MASK (0x07FF0000U)
10549 #define CSL_DSS_VP2_CSC_COEF1_C10_SHIFT (0x00000010U)
10550 #define CSL_DSS_VP2_CSC_COEF1_C10_MAX (0x000007FFU)
10551 
10552 #define CSL_DSS_VP2_CSC_COEF1_RESERVED_54_MASK (0xF8000000U)
10553 #define CSL_DSS_VP2_CSC_COEF1_RESERVED_54_SHIFT (0x0000001BU)
10554 #define CSL_DSS_VP2_CSC_COEF1_RESERVED_54_MAX (0x0000001FU)
10555 
10556 /* CSC_COEF2 */
10557 
10558 #define CSL_DSS_VP2_CSC_COEF2_C11_MASK (0x000007FFU)
10559 #define CSL_DSS_VP2_CSC_COEF2_C11_SHIFT (0x00000000U)
10560 #define CSL_DSS_VP2_CSC_COEF2_C11_MAX (0x000007FFU)
10561 
10562 #define CSL_DSS_VP2_CSC_COEF2_RESERVED_57_MASK (0x0000F800U)
10563 #define CSL_DSS_VP2_CSC_COEF2_RESERVED_57_SHIFT (0x0000000BU)
10564 #define CSL_DSS_VP2_CSC_COEF2_RESERVED_57_MAX (0x0000001FU)
10565 
10566 #define CSL_DSS_VP2_CSC_COEF2_C12_MASK (0x07FF0000U)
10567 #define CSL_DSS_VP2_CSC_COEF2_C12_SHIFT (0x00000010U)
10568 #define CSL_DSS_VP2_CSC_COEF2_C12_MAX (0x000007FFU)
10569 
10570 #define CSL_DSS_VP2_CSC_COEF2_RESERVED_56_MASK (0xF8000000U)
10571 #define CSL_DSS_VP2_CSC_COEF2_RESERVED_56_SHIFT (0x0000001BU)
10572 #define CSL_DSS_VP2_CSC_COEF2_RESERVED_56_MAX (0x0000001FU)
10573 
10574 /* DATA_CYCLE_0 */
10575 
10576 #define CSL_DSS_VP2_DATA_CYCLE_0_NBBITSPIXEL1_MASK (0x0000001FU)
10577 #define CSL_DSS_VP2_DATA_CYCLE_0_NBBITSPIXEL1_SHIFT (0x00000000U)
10578 #define CSL_DSS_VP2_DATA_CYCLE_0_NBBITSPIXEL1_MAX (0x0000001FU)
10579 
10580 #define CSL_DSS_VP2_DATA_CYCLE_0_RESERVED_4_MASK (0x000000E0U)
10581 #define CSL_DSS_VP2_DATA_CYCLE_0_RESERVED_4_SHIFT (0x00000005U)
10582 #define CSL_DSS_VP2_DATA_CYCLE_0_RESERVED_4_MAX (0x00000007U)
10583 
10584 #define CSL_DSS_VP2_DATA_CYCLE_0_BITALIGNMENTPIXEL1_MASK (0x00000F00U)
10585 #define CSL_DSS_VP2_DATA_CYCLE_0_BITALIGNMENTPIXEL1_SHIFT (0x00000008U)
10586 #define CSL_DSS_VP2_DATA_CYCLE_0_BITALIGNMENTPIXEL1_MAX (0x0000000FU)
10587 
10588 #define CSL_DSS_VP2_DATA_CYCLE_0_RESERVED_3_MASK (0x0000F000U)
10589 #define CSL_DSS_VP2_DATA_CYCLE_0_RESERVED_3_SHIFT (0x0000000CU)
10590 #define CSL_DSS_VP2_DATA_CYCLE_0_RESERVED_3_MAX (0x0000000FU)
10591 
10592 #define CSL_DSS_VP2_DATA_CYCLE_0_NBBITSPIXEL2_MASK (0x001F0000U)
10593 #define CSL_DSS_VP2_DATA_CYCLE_0_NBBITSPIXEL2_SHIFT (0x00000010U)
10594 #define CSL_DSS_VP2_DATA_CYCLE_0_NBBITSPIXEL2_MAX (0x0000001FU)
10595 
10596 #define CSL_DSS_VP2_DATA_CYCLE_0_RESERVED_6_MASK (0x00E00000U)
10597 #define CSL_DSS_VP2_DATA_CYCLE_0_RESERVED_6_SHIFT (0x00000015U)
10598 #define CSL_DSS_VP2_DATA_CYCLE_0_RESERVED_6_MAX (0x00000007U)
10599 
10600 #define CSL_DSS_VP2_DATA_CYCLE_0_BITALIGNMENTPIXEL2_MASK (0x0F000000U)
10601 #define CSL_DSS_VP2_DATA_CYCLE_0_BITALIGNMENTPIXEL2_SHIFT (0x00000018U)
10602 #define CSL_DSS_VP2_DATA_CYCLE_0_BITALIGNMENTPIXEL2_MAX (0x0000000FU)
10603 
10604 #define CSL_DSS_VP2_DATA_CYCLE_0_RESERVED_5_MASK (0xF0000000U)
10605 #define CSL_DSS_VP2_DATA_CYCLE_0_RESERVED_5_SHIFT (0x0000001CU)
10606 #define CSL_DSS_VP2_DATA_CYCLE_0_RESERVED_5_MAX (0x0000000FU)
10607 
10608 /* DATA_CYCLE_1 */
10609 
10610 #define CSL_DSS_VP2_DATA_CYCLE_1_NBBITSPIXEL1_MASK (0x0000001FU)
10611 #define CSL_DSS_VP2_DATA_CYCLE_1_NBBITSPIXEL1_SHIFT (0x00000000U)
10612 #define CSL_DSS_VP2_DATA_CYCLE_1_NBBITSPIXEL1_MAX (0x0000001FU)
10613 
10614 #define CSL_DSS_VP2_DATA_CYCLE_1_RESERVED_4_MASK (0x000000E0U)
10615 #define CSL_DSS_VP2_DATA_CYCLE_1_RESERVED_4_SHIFT (0x00000005U)
10616 #define CSL_DSS_VP2_DATA_CYCLE_1_RESERVED_4_MAX (0x00000007U)
10617 
10618 #define CSL_DSS_VP2_DATA_CYCLE_1_BITALIGNMENTPIXEL1_MASK (0x00000F00U)
10619 #define CSL_DSS_VP2_DATA_CYCLE_1_BITALIGNMENTPIXEL1_SHIFT (0x00000008U)
10620 #define CSL_DSS_VP2_DATA_CYCLE_1_BITALIGNMENTPIXEL1_MAX (0x0000000FU)
10621 
10622 #define CSL_DSS_VP2_DATA_CYCLE_1_RESERVED_3_MASK (0x0000F000U)
10623 #define CSL_DSS_VP2_DATA_CYCLE_1_RESERVED_3_SHIFT (0x0000000CU)
10624 #define CSL_DSS_VP2_DATA_CYCLE_1_RESERVED_3_MAX (0x0000000FU)
10625 
10626 #define CSL_DSS_VP2_DATA_CYCLE_1_NBBITSPIXEL2_MASK (0x001F0000U)
10627 #define CSL_DSS_VP2_DATA_CYCLE_1_NBBITSPIXEL2_SHIFT (0x00000010U)
10628 #define CSL_DSS_VP2_DATA_CYCLE_1_NBBITSPIXEL2_MAX (0x0000001FU)
10629 
10630 #define CSL_DSS_VP2_DATA_CYCLE_1_RESERVED_6_MASK (0x00E00000U)
10631 #define CSL_DSS_VP2_DATA_CYCLE_1_RESERVED_6_SHIFT (0x00000015U)
10632 #define CSL_DSS_VP2_DATA_CYCLE_1_RESERVED_6_MAX (0x00000007U)
10633 
10634 #define CSL_DSS_VP2_DATA_CYCLE_1_BITALIGNMENTPIXEL2_MASK (0x0F000000U)
10635 #define CSL_DSS_VP2_DATA_CYCLE_1_BITALIGNMENTPIXEL2_SHIFT (0x00000018U)
10636 #define CSL_DSS_VP2_DATA_CYCLE_1_BITALIGNMENTPIXEL2_MAX (0x0000000FU)
10637 
10638 #define CSL_DSS_VP2_DATA_CYCLE_1_RESERVED_5_MASK (0xF0000000U)
10639 #define CSL_DSS_VP2_DATA_CYCLE_1_RESERVED_5_SHIFT (0x0000001CU)
10640 #define CSL_DSS_VP2_DATA_CYCLE_1_RESERVED_5_MAX (0x0000000FU)
10641 
10642 /* DATA_CYCLE_2 */
10643 
10644 #define CSL_DSS_VP2_DATA_CYCLE_2_NBBITSPIXEL1_MASK (0x0000001FU)
10645 #define CSL_DSS_VP2_DATA_CYCLE_2_NBBITSPIXEL1_SHIFT (0x00000000U)
10646 #define CSL_DSS_VP2_DATA_CYCLE_2_NBBITSPIXEL1_MAX (0x0000001FU)
10647 
10648 #define CSL_DSS_VP2_DATA_CYCLE_2_RESERVED_4_MASK (0x000000E0U)
10649 #define CSL_DSS_VP2_DATA_CYCLE_2_RESERVED_4_SHIFT (0x00000005U)
10650 #define CSL_DSS_VP2_DATA_CYCLE_2_RESERVED_4_MAX (0x00000007U)
10651 
10652 #define CSL_DSS_VP2_DATA_CYCLE_2_BITALIGNMENTPIXEL1_MASK (0x00000F00U)
10653 #define CSL_DSS_VP2_DATA_CYCLE_2_BITALIGNMENTPIXEL1_SHIFT (0x00000008U)
10654 #define CSL_DSS_VP2_DATA_CYCLE_2_BITALIGNMENTPIXEL1_MAX (0x0000000FU)
10655 
10656 #define CSL_DSS_VP2_DATA_CYCLE_2_RESERVED_3_MASK (0x0000F000U)
10657 #define CSL_DSS_VP2_DATA_CYCLE_2_RESERVED_3_SHIFT (0x0000000CU)
10658 #define CSL_DSS_VP2_DATA_CYCLE_2_RESERVED_3_MAX (0x0000000FU)
10659 
10660 #define CSL_DSS_VP2_DATA_CYCLE_2_NBBITSPIXEL2_MASK (0x001F0000U)
10661 #define CSL_DSS_VP2_DATA_CYCLE_2_NBBITSPIXEL2_SHIFT (0x00000010U)
10662 #define CSL_DSS_VP2_DATA_CYCLE_2_NBBITSPIXEL2_MAX (0x0000001FU)
10663 
10664 #define CSL_DSS_VP2_DATA_CYCLE_2_RESERVED_6_MASK (0x00E00000U)
10665 #define CSL_DSS_VP2_DATA_CYCLE_2_RESERVED_6_SHIFT (0x00000015U)
10666 #define CSL_DSS_VP2_DATA_CYCLE_2_RESERVED_6_MAX (0x00000007U)
10667 
10668 #define CSL_DSS_VP2_DATA_CYCLE_2_BITALIGNMENTPIXEL2_MASK (0x0F000000U)
10669 #define CSL_DSS_VP2_DATA_CYCLE_2_BITALIGNMENTPIXEL2_SHIFT (0x00000018U)
10670 #define CSL_DSS_VP2_DATA_CYCLE_2_BITALIGNMENTPIXEL2_MAX (0x0000000FU)
10671 
10672 #define CSL_DSS_VP2_DATA_CYCLE_2_RESERVED_5_MASK (0xF0000000U)
10673 #define CSL_DSS_VP2_DATA_CYCLE_2_RESERVED_5_SHIFT (0x0000001CU)
10674 #define CSL_DSS_VP2_DATA_CYCLE_2_RESERVED_5_MAX (0x0000000FU)
10675 
10676 /* LINE_NUMBER */
10677 
10678 #define CSL_DSS_VP2_LINE_NUMBER_LINENUMBER_MASK (0x00003FFFU)
10679 #define CSL_DSS_VP2_LINE_NUMBER_LINENUMBER_SHIFT (0x00000000U)
10680 #define CSL_DSS_VP2_LINE_NUMBER_LINENUMBER_MAX (0x00003FFFU)
10681 
10682 #define CSL_DSS_VP2_LINE_NUMBER_RESERVED_MASK (0xFFFFC000U)
10683 #define CSL_DSS_VP2_LINE_NUMBER_RESERVED_SHIFT (0x0000000EU)
10684 #define CSL_DSS_VP2_LINE_NUMBER_RESERVED_MAX (0x0003FFFFU)
10685 
10686 /* POL_FREQ */
10687 
10688 #define CSL_DSS_VP2_POL_FREQ_ACB_MASK (0x000000FFU)
10689 #define CSL_DSS_VP2_POL_FREQ_ACB_SHIFT (0x00000000U)
10690 #define CSL_DSS_VP2_POL_FREQ_ACB_MAX (0x000000FFU)
10691 
10692 #define CSL_DSS_VP2_POL_FREQ_ACBI_MASK (0x00000F00U)
10693 #define CSL_DSS_VP2_POL_FREQ_ACBI_SHIFT (0x00000008U)
10694 #define CSL_DSS_VP2_POL_FREQ_ACBI_MAX (0x0000000FU)
10695 
10696 #define CSL_DSS_VP2_POL_FREQ_IVS_MASK (0x00001000U)
10697 #define CSL_DSS_VP2_POL_FREQ_IVS_SHIFT (0x0000000CU)
10698 #define CSL_DSS_VP2_POL_FREQ_IVS_MAX (0x00000001U)
10699 
10700 #define CSL_DSS_VP2_POL_FREQ_IVS_VAL_FCKPINAH (0x0U)
10701 #define CSL_DSS_VP2_POL_FREQ_IVS_VAL_FCKPINAL (0x1U)
10702 
10703 #define CSL_DSS_VP2_POL_FREQ_IHS_MASK (0x00002000U)
10704 #define CSL_DSS_VP2_POL_FREQ_IHS_SHIFT (0x0000000DU)
10705 #define CSL_DSS_VP2_POL_FREQ_IHS_MAX (0x00000001U)
10706 
10707 #define CSL_DSS_VP2_POL_FREQ_IHS_VAL_LCKPINAH (0x0U)
10708 #define CSL_DSS_VP2_POL_FREQ_IHS_VAL_LCKPINAL (0x1U)
10709 
10710 #define CSL_DSS_VP2_POL_FREQ_IPC_MASK (0x00004000U)
10711 #define CSL_DSS_VP2_POL_FREQ_IPC_SHIFT (0x0000000EU)
10712 #define CSL_DSS_VP2_POL_FREQ_IPC_MAX (0x00000001U)
10713 
10714 #define CSL_DSS_VP2_POL_FREQ_IPC_VAL_DRPCK (0x0U)
10715 #define CSL_DSS_VP2_POL_FREQ_IPC_VAL_DFPCK (0x1U)
10716 
10717 #define CSL_DSS_VP2_POL_FREQ_IEO_MASK (0x00008000U)
10718 #define CSL_DSS_VP2_POL_FREQ_IEO_SHIFT (0x0000000FU)
10719 #define CSL_DSS_VP2_POL_FREQ_IEO_MAX (0x00000001U)
10720 
10721 #define CSL_DSS_VP2_POL_FREQ_IEO_VAL_ACBAHIGH (0x0U)
10722 #define CSL_DSS_VP2_POL_FREQ_IEO_VAL_ACBALOW (0x1U)
10723 
10724 #define CSL_DSS_VP2_POL_FREQ_RF_MASK (0x00010000U)
10725 #define CSL_DSS_VP2_POL_FREQ_RF_SHIFT (0x00000010U)
10726 #define CSL_DSS_VP2_POL_FREQ_RF_MAX (0x00000001U)
10727 
10728 #define CSL_DSS_VP2_POL_FREQ_RF_VAL_DFEDPCK (0x0U)
10729 #define CSL_DSS_VP2_POL_FREQ_RF_VAL_DRIEDPCK (0x1U)
10730 
10731 #define CSL_DSS_VP2_POL_FREQ_ONOFF_MASK (0x00020000U)
10732 #define CSL_DSS_VP2_POL_FREQ_ONOFF_SHIFT (0x00000011U)
10733 #define CSL_DSS_VP2_POL_FREQ_ONOFF_MAX (0x00000001U)
10734 
10735 #define CSL_DSS_VP2_POL_FREQ_ONOFF_VAL_DOPEDPCK (0x0U)
10736 #define CSL_DSS_VP2_POL_FREQ_ONOFF_VAL_DBIT16 (0x1U)
10737 
10738 #define CSL_DSS_VP2_POL_FREQ_ALIGN_MASK (0x00040000U)
10739 #define CSL_DSS_VP2_POL_FREQ_ALIGN_SHIFT (0x00000012U)
10740 #define CSL_DSS_VP2_POL_FREQ_ALIGN_MAX (0x00000001U)
10741 
10742 #define CSL_DSS_VP2_POL_FREQ_ALIGN_VAL_NOTALIGNED (0x0U)
10743 #define CSL_DSS_VP2_POL_FREQ_ALIGN_VAL_ALIGNED (0x1U)
10744 
10745 #define CSL_DSS_VP2_POL_FREQ_RESERVED_MASK (0xFFF80000U)
10746 #define CSL_DSS_VP2_POL_FREQ_RESERVED_SHIFT (0x00000013U)
10747 #define CSL_DSS_VP2_POL_FREQ_RESERVED_MAX (0x00001FFFU)
10748 
10749 /* SIZE_SCREEN */
10750 
10751 #define CSL_DSS_VP2_SIZE_SCREEN_PPL_MASK (0x00003FFFU)
10752 #define CSL_DSS_VP2_SIZE_SCREEN_PPL_SHIFT (0x00000000U)
10753 #define CSL_DSS_VP2_SIZE_SCREEN_PPL_MAX (0x00003FFFU)
10754 
10755 #define CSL_DSS_VP2_SIZE_SCREEN_DELTA_LPP_MASK (0x0000C000U)
10756 #define CSL_DSS_VP2_SIZE_SCREEN_DELTA_LPP_SHIFT (0x0000000EU)
10757 #define CSL_DSS_VP2_SIZE_SCREEN_DELTA_LPP_MAX (0x00000003U)
10758 
10759 #define CSL_DSS_VP2_SIZE_SCREEN_DELTA_LPP_VAL_SAME (0x0U)
10760 #define CSL_DSS_VP2_SIZE_SCREEN_DELTA_LPP_VAL_PLUSONE (0x1U)
10761 #define CSL_DSS_VP2_SIZE_SCREEN_DELTA_LPP_VAL_MINUSONE (0x2U)
10762 
10763 #define CSL_DSS_VP2_SIZE_SCREEN_LPP_MASK (0x3FFF0000U)
10764 #define CSL_DSS_VP2_SIZE_SCREEN_LPP_SHIFT (0x00000010U)
10765 #define CSL_DSS_VP2_SIZE_SCREEN_LPP_MAX (0x00003FFFU)
10766 
10767 /* TIMING_H */
10768 
10769 #define CSL_DSS_VP2_TIMING_H_HSW_MASK (0x000000FFU)
10770 #define CSL_DSS_VP2_TIMING_H_HSW_SHIFT (0x00000000U)
10771 #define CSL_DSS_VP2_TIMING_H_HSW_MAX (0x000000FFU)
10772 
10773 #define CSL_DSS_VP2_TIMING_H_HFP_MASK (0x000FFF00U)
10774 #define CSL_DSS_VP2_TIMING_H_HFP_SHIFT (0x00000008U)
10775 #define CSL_DSS_VP2_TIMING_H_HFP_MAX (0x00000FFFU)
10776 
10777 #define CSL_DSS_VP2_TIMING_H_HBP_MASK (0xFFF00000U)
10778 #define CSL_DSS_VP2_TIMING_H_HBP_SHIFT (0x00000014U)
10779 #define CSL_DSS_VP2_TIMING_H_HBP_MAX (0x00000FFFU)
10780 
10781 /* TIMING_V */
10782 
10783 #define CSL_DSS_VP2_TIMING_V_VSW_MASK (0x000000FFU)
10784 #define CSL_DSS_VP2_TIMING_V_VSW_SHIFT (0x00000000U)
10785 #define CSL_DSS_VP2_TIMING_V_VSW_MAX (0x000000FFU)
10786 
10787 #define CSL_DSS_VP2_TIMING_V_VFP_MASK (0x000FFF00U)
10788 #define CSL_DSS_VP2_TIMING_V_VFP_SHIFT (0x00000008U)
10789 #define CSL_DSS_VP2_TIMING_V_VFP_MAX (0x00000FFFU)
10790 
10791 #define CSL_DSS_VP2_TIMING_V_VBP_MASK (0xFFF00000U)
10792 #define CSL_DSS_VP2_TIMING_V_VBP_SHIFT (0x00000014U)
10793 #define CSL_DSS_VP2_TIMING_V_VBP_MAX (0x00000FFFU)
10794 
10795 /* CSC_COEF3 */
10796 
10797 #define CSL_DSS_VP2_CSC_COEF3_C20_MASK (0x000007FFU)
10798 #define CSL_DSS_VP2_CSC_COEF3_C20_SHIFT (0x00000000U)
10799 #define CSL_DSS_VP2_CSC_COEF3_C20_MAX (0x000007FFU)
10800 
10801 #define CSL_DSS_VP2_CSC_COEF3_RESERVED_59_MASK (0x0000F800U)
10802 #define CSL_DSS_VP2_CSC_COEF3_RESERVED_59_SHIFT (0x0000000BU)
10803 #define CSL_DSS_VP2_CSC_COEF3_RESERVED_59_MAX (0x0000001FU)
10804 
10805 #define CSL_DSS_VP2_CSC_COEF3_C21_MASK (0x07FF0000U)
10806 #define CSL_DSS_VP2_CSC_COEF3_C21_SHIFT (0x00000010U)
10807 #define CSL_DSS_VP2_CSC_COEF3_C21_MAX (0x000007FFU)
10808 
10809 #define CSL_DSS_VP2_CSC_COEF3_RESERVED_58_MASK (0xF8000000U)
10810 #define CSL_DSS_VP2_CSC_COEF3_RESERVED_58_SHIFT (0x0000001BU)
10811 #define CSL_DSS_VP2_CSC_COEF3_RESERVED_58_MAX (0x0000001FU)
10812 
10813 /* CSC_COEF4 */
10814 
10815 #define CSL_DSS_VP2_CSC_COEF4_C22_MASK (0x000007FFU)
10816 #define CSL_DSS_VP2_CSC_COEF4_C22_SHIFT (0x00000000U)
10817 #define CSL_DSS_VP2_CSC_COEF4_C22_MAX (0x000007FFU)
10818 
10819 #define CSL_DSS_VP2_CSC_COEF4_RESERVED_60_MASK (0xFFFFF800U)
10820 #define CSL_DSS_VP2_CSC_COEF4_RESERVED_60_SHIFT (0x0000000BU)
10821 #define CSL_DSS_VP2_CSC_COEF4_RESERVED_60_MAX (0x001FFFFFU)
10822 
10823 /* CSC_COEF5 */
10824 
10825 #define CSL_DSS_VP2_CSC_COEF5_RESERVED_MASK (0x00000007U)
10826 #define CSL_DSS_VP2_CSC_COEF5_RESERVED_SHIFT (0x00000000U)
10827 #define CSL_DSS_VP2_CSC_COEF5_RESERVED_MAX (0x00000007U)
10828 
10829 #define CSL_DSS_VP2_CSC_COEF5_PREOFFSET1_MASK (0x0000FFF8U)
10830 #define CSL_DSS_VP2_CSC_COEF5_PREOFFSET1_SHIFT (0x00000003U)
10831 #define CSL_DSS_VP2_CSC_COEF5_PREOFFSET1_MAX (0x00001FFFU)
10832 
10833 #define CSL_DSS_VP2_CSC_COEF5_RESERVED1_MASK (0x00070000U)
10834 #define CSL_DSS_VP2_CSC_COEF5_RESERVED1_SHIFT (0x00000010U)
10835 #define CSL_DSS_VP2_CSC_COEF5_RESERVED1_MAX (0x00000007U)
10836 
10837 #define CSL_DSS_VP2_CSC_COEF5_PREOFFSET2_MASK (0xFFF80000U)
10838 #define CSL_DSS_VP2_CSC_COEF5_PREOFFSET2_SHIFT (0x00000013U)
10839 #define CSL_DSS_VP2_CSC_COEF5_PREOFFSET2_MAX (0x00001FFFU)
10840 
10841 /* CSC_COEF6 */
10842 
10843 #define CSL_DSS_VP2_CSC_COEF6_RESERVED_MASK (0x00000007U)
10844 #define CSL_DSS_VP2_CSC_COEF6_RESERVED_SHIFT (0x00000000U)
10845 #define CSL_DSS_VP2_CSC_COEF6_RESERVED_MAX (0x00000007U)
10846 
10847 #define CSL_DSS_VP2_CSC_COEF6_PREOFFSET3_MASK (0x0000FFF8U)
10848 #define CSL_DSS_VP2_CSC_COEF6_PREOFFSET3_SHIFT (0x00000003U)
10849 #define CSL_DSS_VP2_CSC_COEF6_PREOFFSET3_MAX (0x00001FFFU)
10850 
10851 #define CSL_DSS_VP2_CSC_COEF6_RESERVED1_MASK (0x00070000U)
10852 #define CSL_DSS_VP2_CSC_COEF6_RESERVED1_SHIFT (0x00000010U)
10853 #define CSL_DSS_VP2_CSC_COEF6_RESERVED1_MAX (0x00000007U)
10854 
10855 #define CSL_DSS_VP2_CSC_COEF6_POSTOFFSET1_MASK (0xFFF80000U)
10856 #define CSL_DSS_VP2_CSC_COEF6_POSTOFFSET1_SHIFT (0x00000013U)
10857 #define CSL_DSS_VP2_CSC_COEF6_POSTOFFSET1_MAX (0x00001FFFU)
10858 
10859 /* CSC_COEF7 */
10860 
10861 #define CSL_DSS_VP2_CSC_COEF7_RESERVED_MASK (0x00000007U)
10862 #define CSL_DSS_VP2_CSC_COEF7_RESERVED_SHIFT (0x00000000U)
10863 #define CSL_DSS_VP2_CSC_COEF7_RESERVED_MAX (0x00000007U)
10864 
10865 #define CSL_DSS_VP2_CSC_COEF7_POSTOFFSET2_MASK (0x0000FFF8U)
10866 #define CSL_DSS_VP2_CSC_COEF7_POSTOFFSET2_SHIFT (0x00000003U)
10867 #define CSL_DSS_VP2_CSC_COEF7_POSTOFFSET2_MAX (0x00001FFFU)
10868 
10869 #define CSL_DSS_VP2_CSC_COEF7_RESERVED1_MASK (0x00070000U)
10870 #define CSL_DSS_VP2_CSC_COEF7_RESERVED1_SHIFT (0x00000010U)
10871 #define CSL_DSS_VP2_CSC_COEF7_RESERVED1_MAX (0x00000007U)
10872 
10873 #define CSL_DSS_VP2_CSC_COEF7_POSTOFFSET3_MASK (0xFFF80000U)
10874 #define CSL_DSS_VP2_CSC_COEF7_POSTOFFSET3_SHIFT (0x00000013U)
10875 #define CSL_DSS_VP2_CSC_COEF7_POSTOFFSET3_MAX (0x00001FFFU)
10876 
10877 /* SAFETY_ATTRIBUTES */
10878 
10879 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_ENABLE_MASK (0x00000001U)
10880 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
10881 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_ENABLE_MAX (0x00000001U)
10882 
10883 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_CAPTUREMODE_MASK (0x00000002U)
10884 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_CAPTUREMODE_SHIFT (0x00000001U)
10885 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_CAPTUREMODE_MAX (0x00000001U)
10886 
10887 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_FRAMEFREEZE (0x0U)
10888 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_DATACHECK (0x1U)
10889 
10890 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_SEEDSELECT_MASK (0x00000004U)
10891 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_SEEDSELECT_SHIFT (0x00000002U)
10892 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_SEEDSELECT_MAX (0x00000001U)
10893 
10894 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_DISABLE (0x0U)
10895 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_ENABLE (0x1U)
10896 
10897 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_THRESHOLD_MASK (0x000007F8U)
10898 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_THRESHOLD_SHIFT (0x00000003U)
10899 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_THRESHOLD_MAX (0x000000FFU)
10900 
10901 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_FRAMESKIP_MASK (0x00001800U)
10902 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_FRAMESKIP_SHIFT (0x0000000BU)
10903 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_FRAMESKIP_MAX (0x00000003U)
10904 
10905 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_NOSKIP (0x0U)
10906 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_EVEN (0x1U)
10907 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_ODD (0x2U)
10908 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_RESERVED (0x3U)
10909 
10910 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_RESERVED_MASK (0xFFFFE000U)
10911 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_RESERVED_SHIFT (0x0000000DU)
10912 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_RESERVED_MAX (0x0007FFFFU)
10913 
10914 /* SAFETY_CAPT_SIGNATURE */
10915 
10916 #define CSL_DSS_VP2_SAFETY_CAPT_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
10917 #define CSL_DSS_VP2_SAFETY_CAPT_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
10918 #define CSL_DSS_VP2_SAFETY_CAPT_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
10919 
10920 /* SAFETY_POSITION */
10921 
10922 #define CSL_DSS_VP2_SAFETY_POSITION_POSX_MASK (0x00003FFFU)
10923 #define CSL_DSS_VP2_SAFETY_POSITION_POSX_SHIFT (0x00000000U)
10924 #define CSL_DSS_VP2_SAFETY_POSITION_POSX_MAX (0x00003FFFU)
10925 
10926 #define CSL_DSS_VP2_SAFETY_POSITION_POSY_MASK (0x3FFF0000U)
10927 #define CSL_DSS_VP2_SAFETY_POSITION_POSY_SHIFT (0x00000010U)
10928 #define CSL_DSS_VP2_SAFETY_POSITION_POSY_MAX (0x00003FFFU)
10929 
10930 /* SAFETY_REF_SIGNATURE */
10931 
10932 #define CSL_DSS_VP2_SAFETY_REF_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
10933 #define CSL_DSS_VP2_SAFETY_REF_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
10934 #define CSL_DSS_VP2_SAFETY_REF_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
10935 
10936 /* SAFETY_SIZE */
10937 
10938 #define CSL_DSS_VP2_SAFETY_SIZE_SIZEX_MASK (0x00003FFFU)
10939 #define CSL_DSS_VP2_SAFETY_SIZE_SIZEX_SHIFT (0x00000000U)
10940 #define CSL_DSS_VP2_SAFETY_SIZE_SIZEX_MAX (0x00003FFFU)
10941 
10942 #define CSL_DSS_VP2_SAFETY_SIZE_SIZEY_MASK (0x3FFF0000U)
10943 #define CSL_DSS_VP2_SAFETY_SIZE_SIZEY_SHIFT (0x00000010U)
10944 #define CSL_DSS_VP2_SAFETY_SIZE_SIZEY_MAX (0x00003FFFU)
10945 
10946 /* SAFETY_LFSR_SEED */
10947 
10948 #define CSL_DSS_VP2_SAFETY_LFSR_SEED_SEED_MASK (0xFFFFFFFFU)
10949 #define CSL_DSS_VP2_SAFETY_LFSR_SEED_SEED_SHIFT (0x00000000U)
10950 #define CSL_DSS_VP2_SAFETY_LFSR_SEED_SEED_MAX (0xFFFFFFFFU)
10951 
10952 /* GAMMA_TABLE_0 */
10953 
10954 #define CSL_DSS_VP2_GAMMA_TABLE_0_VALUE_B_MASK (0x000003FFU)
10955 #define CSL_DSS_VP2_GAMMA_TABLE_0_VALUE_B_SHIFT (0x00000000U)
10956 #define CSL_DSS_VP2_GAMMA_TABLE_0_VALUE_B_MAX (0x000003FFU)
10957 
10958 #define CSL_DSS_VP2_GAMMA_TABLE_0_VALUE_G_MASK (0x000FFC00U)
10959 #define CSL_DSS_VP2_GAMMA_TABLE_0_VALUE_G_SHIFT (0x0000000AU)
10960 #define CSL_DSS_VP2_GAMMA_TABLE_0_VALUE_G_MAX (0x000003FFU)
10961 
10962 #define CSL_DSS_VP2_GAMMA_TABLE_0_VALUE_R_MASK (0x3FF00000U)
10963 #define CSL_DSS_VP2_GAMMA_TABLE_0_VALUE_R_SHIFT (0x00000014U)
10964 #define CSL_DSS_VP2_GAMMA_TABLE_0_VALUE_R_MAX (0x000003FFU)
10965 
10966 #define CSL_DSS_VP2_GAMMA_TABLE_0_INDEX_MASK (0x80000000U)
10967 #define CSL_DSS_VP2_GAMMA_TABLE_0_INDEX_SHIFT (0x0000001FU)
10968 #define CSL_DSS_VP2_GAMMA_TABLE_0_INDEX_MAX (0x00000001U)
10969 
10970 /* GAMMA_TABLE_1 */
10971 
10972 #define CSL_DSS_VP2_GAMMA_TABLE_1_VALUE_B_MASK (0x000003FFU)
10973 #define CSL_DSS_VP2_GAMMA_TABLE_1_VALUE_B_SHIFT (0x00000000U)
10974 #define CSL_DSS_VP2_GAMMA_TABLE_1_VALUE_B_MAX (0x000003FFU)
10975 
10976 #define CSL_DSS_VP2_GAMMA_TABLE_1_VALUE_G_MASK (0x000FFC00U)
10977 #define CSL_DSS_VP2_GAMMA_TABLE_1_VALUE_G_SHIFT (0x0000000AU)
10978 #define CSL_DSS_VP2_GAMMA_TABLE_1_VALUE_G_MAX (0x000003FFU)
10979 
10980 #define CSL_DSS_VP2_GAMMA_TABLE_1_VALUE_R_MASK (0x3FF00000U)
10981 #define CSL_DSS_VP2_GAMMA_TABLE_1_VALUE_R_SHIFT (0x00000014U)
10982 #define CSL_DSS_VP2_GAMMA_TABLE_1_VALUE_R_MAX (0x000003FFU)
10983 
10984 #define CSL_DSS_VP2_GAMMA_TABLE_1_INDEX_MASK (0x80000000U)
10985 #define CSL_DSS_VP2_GAMMA_TABLE_1_INDEX_SHIFT (0x0000001FU)
10986 #define CSL_DSS_VP2_GAMMA_TABLE_1_INDEX_MAX (0x00000001U)
10987 
10988 /* GAMMA_TABLE_2 */
10989 
10990 #define CSL_DSS_VP2_GAMMA_TABLE_2_VALUE_B_MASK (0x000003FFU)
10991 #define CSL_DSS_VP2_GAMMA_TABLE_2_VALUE_B_SHIFT (0x00000000U)
10992 #define CSL_DSS_VP2_GAMMA_TABLE_2_VALUE_B_MAX (0x000003FFU)
10993 
10994 #define CSL_DSS_VP2_GAMMA_TABLE_2_VALUE_G_MASK (0x000FFC00U)
10995 #define CSL_DSS_VP2_GAMMA_TABLE_2_VALUE_G_SHIFT (0x0000000AU)
10996 #define CSL_DSS_VP2_GAMMA_TABLE_2_VALUE_G_MAX (0x000003FFU)
10997 
10998 #define CSL_DSS_VP2_GAMMA_TABLE_2_VALUE_R_MASK (0x3FF00000U)
10999 #define CSL_DSS_VP2_GAMMA_TABLE_2_VALUE_R_SHIFT (0x00000014U)
11000 #define CSL_DSS_VP2_GAMMA_TABLE_2_VALUE_R_MAX (0x000003FFU)
11001 
11002 #define CSL_DSS_VP2_GAMMA_TABLE_2_INDEX_MASK (0x80000000U)
11003 #define CSL_DSS_VP2_GAMMA_TABLE_2_INDEX_SHIFT (0x0000001FU)
11004 #define CSL_DSS_VP2_GAMMA_TABLE_2_INDEX_MAX (0x00000001U)
11005 
11006 /* GAMMA_TABLE_3 */
11007 
11008 #define CSL_DSS_VP2_GAMMA_TABLE_3_VALUE_B_MASK (0x000003FFU)
11009 #define CSL_DSS_VP2_GAMMA_TABLE_3_VALUE_B_SHIFT (0x00000000U)
11010 #define CSL_DSS_VP2_GAMMA_TABLE_3_VALUE_B_MAX (0x000003FFU)
11011 
11012 #define CSL_DSS_VP2_GAMMA_TABLE_3_VALUE_G_MASK (0x000FFC00U)
11013 #define CSL_DSS_VP2_GAMMA_TABLE_3_VALUE_G_SHIFT (0x0000000AU)
11014 #define CSL_DSS_VP2_GAMMA_TABLE_3_VALUE_G_MAX (0x000003FFU)
11015 
11016 #define CSL_DSS_VP2_GAMMA_TABLE_3_VALUE_R_MASK (0x3FF00000U)
11017 #define CSL_DSS_VP2_GAMMA_TABLE_3_VALUE_R_SHIFT (0x00000014U)
11018 #define CSL_DSS_VP2_GAMMA_TABLE_3_VALUE_R_MAX (0x000003FFU)
11019 
11020 #define CSL_DSS_VP2_GAMMA_TABLE_3_INDEX_MASK (0x80000000U)
11021 #define CSL_DSS_VP2_GAMMA_TABLE_3_INDEX_SHIFT (0x0000001FU)
11022 #define CSL_DSS_VP2_GAMMA_TABLE_3_INDEX_MAX (0x00000001U)
11023 
11024 /* GAMMA_TABLE_4 */
11025 
11026 #define CSL_DSS_VP2_GAMMA_TABLE_4_VALUE_B_MASK (0x000003FFU)
11027 #define CSL_DSS_VP2_GAMMA_TABLE_4_VALUE_B_SHIFT (0x00000000U)
11028 #define CSL_DSS_VP2_GAMMA_TABLE_4_VALUE_B_MAX (0x000003FFU)
11029 
11030 #define CSL_DSS_VP2_GAMMA_TABLE_4_VALUE_G_MASK (0x000FFC00U)
11031 #define CSL_DSS_VP2_GAMMA_TABLE_4_VALUE_G_SHIFT (0x0000000AU)
11032 #define CSL_DSS_VP2_GAMMA_TABLE_4_VALUE_G_MAX (0x000003FFU)
11033 
11034 #define CSL_DSS_VP2_GAMMA_TABLE_4_VALUE_R_MASK (0x3FF00000U)
11035 #define CSL_DSS_VP2_GAMMA_TABLE_4_VALUE_R_SHIFT (0x00000014U)
11036 #define CSL_DSS_VP2_GAMMA_TABLE_4_VALUE_R_MAX (0x000003FFU)
11037 
11038 #define CSL_DSS_VP2_GAMMA_TABLE_4_INDEX_MASK (0x80000000U)
11039 #define CSL_DSS_VP2_GAMMA_TABLE_4_INDEX_SHIFT (0x0000001FU)
11040 #define CSL_DSS_VP2_GAMMA_TABLE_4_INDEX_MAX (0x00000001U)
11041 
11042 /* GAMMA_TABLE_5 */
11043 
11044 #define CSL_DSS_VP2_GAMMA_TABLE_5_VALUE_B_MASK (0x000003FFU)
11045 #define CSL_DSS_VP2_GAMMA_TABLE_5_VALUE_B_SHIFT (0x00000000U)
11046 #define CSL_DSS_VP2_GAMMA_TABLE_5_VALUE_B_MAX (0x000003FFU)
11047 
11048 #define CSL_DSS_VP2_GAMMA_TABLE_5_VALUE_G_MASK (0x000FFC00U)
11049 #define CSL_DSS_VP2_GAMMA_TABLE_5_VALUE_G_SHIFT (0x0000000AU)
11050 #define CSL_DSS_VP2_GAMMA_TABLE_5_VALUE_G_MAX (0x000003FFU)
11051 
11052 #define CSL_DSS_VP2_GAMMA_TABLE_5_VALUE_R_MASK (0x3FF00000U)
11053 #define CSL_DSS_VP2_GAMMA_TABLE_5_VALUE_R_SHIFT (0x00000014U)
11054 #define CSL_DSS_VP2_GAMMA_TABLE_5_VALUE_R_MAX (0x000003FFU)
11055 
11056 #define CSL_DSS_VP2_GAMMA_TABLE_5_INDEX_MASK (0x80000000U)
11057 #define CSL_DSS_VP2_GAMMA_TABLE_5_INDEX_SHIFT (0x0000001FU)
11058 #define CSL_DSS_VP2_GAMMA_TABLE_5_INDEX_MAX (0x00000001U)
11059 
11060 /* GAMMA_TABLE_6 */
11061 
11062 #define CSL_DSS_VP2_GAMMA_TABLE_6_VALUE_B_MASK (0x000003FFU)
11063 #define CSL_DSS_VP2_GAMMA_TABLE_6_VALUE_B_SHIFT (0x00000000U)
11064 #define CSL_DSS_VP2_GAMMA_TABLE_6_VALUE_B_MAX (0x000003FFU)
11065 
11066 #define CSL_DSS_VP2_GAMMA_TABLE_6_VALUE_G_MASK (0x000FFC00U)
11067 #define CSL_DSS_VP2_GAMMA_TABLE_6_VALUE_G_SHIFT (0x0000000AU)
11068 #define CSL_DSS_VP2_GAMMA_TABLE_6_VALUE_G_MAX (0x000003FFU)
11069 
11070 #define CSL_DSS_VP2_GAMMA_TABLE_6_VALUE_R_MASK (0x3FF00000U)
11071 #define CSL_DSS_VP2_GAMMA_TABLE_6_VALUE_R_SHIFT (0x00000014U)
11072 #define CSL_DSS_VP2_GAMMA_TABLE_6_VALUE_R_MAX (0x000003FFU)
11073 
11074 #define CSL_DSS_VP2_GAMMA_TABLE_6_INDEX_MASK (0x80000000U)
11075 #define CSL_DSS_VP2_GAMMA_TABLE_6_INDEX_SHIFT (0x0000001FU)
11076 #define CSL_DSS_VP2_GAMMA_TABLE_6_INDEX_MAX (0x00000001U)
11077 
11078 /* GAMMA_TABLE_7 */
11079 
11080 #define CSL_DSS_VP2_GAMMA_TABLE_7_VALUE_B_MASK (0x000003FFU)
11081 #define CSL_DSS_VP2_GAMMA_TABLE_7_VALUE_B_SHIFT (0x00000000U)
11082 #define CSL_DSS_VP2_GAMMA_TABLE_7_VALUE_B_MAX (0x000003FFU)
11083 
11084 #define CSL_DSS_VP2_GAMMA_TABLE_7_VALUE_G_MASK (0x000FFC00U)
11085 #define CSL_DSS_VP2_GAMMA_TABLE_7_VALUE_G_SHIFT (0x0000000AU)
11086 #define CSL_DSS_VP2_GAMMA_TABLE_7_VALUE_G_MAX (0x000003FFU)
11087 
11088 #define CSL_DSS_VP2_GAMMA_TABLE_7_VALUE_R_MASK (0x3FF00000U)
11089 #define CSL_DSS_VP2_GAMMA_TABLE_7_VALUE_R_SHIFT (0x00000014U)
11090 #define CSL_DSS_VP2_GAMMA_TABLE_7_VALUE_R_MAX (0x000003FFU)
11091 
11092 #define CSL_DSS_VP2_GAMMA_TABLE_7_INDEX_MASK (0x80000000U)
11093 #define CSL_DSS_VP2_GAMMA_TABLE_7_INDEX_SHIFT (0x0000001FU)
11094 #define CSL_DSS_VP2_GAMMA_TABLE_7_INDEX_MAX (0x00000001U)
11095 
11096 /* GAMMA_TABLE_8 */
11097 
11098 #define CSL_DSS_VP2_GAMMA_TABLE_8_VALUE_B_MASK (0x000003FFU)
11099 #define CSL_DSS_VP2_GAMMA_TABLE_8_VALUE_B_SHIFT (0x00000000U)
11100 #define CSL_DSS_VP2_GAMMA_TABLE_8_VALUE_B_MAX (0x000003FFU)
11101 
11102 #define CSL_DSS_VP2_GAMMA_TABLE_8_VALUE_G_MASK (0x000FFC00U)
11103 #define CSL_DSS_VP2_GAMMA_TABLE_8_VALUE_G_SHIFT (0x0000000AU)
11104 #define CSL_DSS_VP2_GAMMA_TABLE_8_VALUE_G_MAX (0x000003FFU)
11105 
11106 #define CSL_DSS_VP2_GAMMA_TABLE_8_VALUE_R_MASK (0x3FF00000U)
11107 #define CSL_DSS_VP2_GAMMA_TABLE_8_VALUE_R_SHIFT (0x00000014U)
11108 #define CSL_DSS_VP2_GAMMA_TABLE_8_VALUE_R_MAX (0x000003FFU)
11109 
11110 #define CSL_DSS_VP2_GAMMA_TABLE_8_INDEX_MASK (0x80000000U)
11111 #define CSL_DSS_VP2_GAMMA_TABLE_8_INDEX_SHIFT (0x0000001FU)
11112 #define CSL_DSS_VP2_GAMMA_TABLE_8_INDEX_MAX (0x00000001U)
11113 
11114 /* GAMMA_TABLE_9 */
11115 
11116 #define CSL_DSS_VP2_GAMMA_TABLE_9_VALUE_B_MASK (0x000003FFU)
11117 #define CSL_DSS_VP2_GAMMA_TABLE_9_VALUE_B_SHIFT (0x00000000U)
11118 #define CSL_DSS_VP2_GAMMA_TABLE_9_VALUE_B_MAX (0x000003FFU)
11119 
11120 #define CSL_DSS_VP2_GAMMA_TABLE_9_VALUE_G_MASK (0x000FFC00U)
11121 #define CSL_DSS_VP2_GAMMA_TABLE_9_VALUE_G_SHIFT (0x0000000AU)
11122 #define CSL_DSS_VP2_GAMMA_TABLE_9_VALUE_G_MAX (0x000003FFU)
11123 
11124 #define CSL_DSS_VP2_GAMMA_TABLE_9_VALUE_R_MASK (0x3FF00000U)
11125 #define CSL_DSS_VP2_GAMMA_TABLE_9_VALUE_R_SHIFT (0x00000014U)
11126 #define CSL_DSS_VP2_GAMMA_TABLE_9_VALUE_R_MAX (0x000003FFU)
11127 
11128 #define CSL_DSS_VP2_GAMMA_TABLE_9_INDEX_MASK (0x80000000U)
11129 #define CSL_DSS_VP2_GAMMA_TABLE_9_INDEX_SHIFT (0x0000001FU)
11130 #define CSL_DSS_VP2_GAMMA_TABLE_9_INDEX_MAX (0x00000001U)
11131 
11132 /* GAMMA_TABLE_10 */
11133 
11134 #define CSL_DSS_VP2_GAMMA_TABLE_10_VALUE_B_MASK (0x000003FFU)
11135 #define CSL_DSS_VP2_GAMMA_TABLE_10_VALUE_B_SHIFT (0x00000000U)
11136 #define CSL_DSS_VP2_GAMMA_TABLE_10_VALUE_B_MAX (0x000003FFU)
11137 
11138 #define CSL_DSS_VP2_GAMMA_TABLE_10_VALUE_G_MASK (0x000FFC00U)
11139 #define CSL_DSS_VP2_GAMMA_TABLE_10_VALUE_G_SHIFT (0x0000000AU)
11140 #define CSL_DSS_VP2_GAMMA_TABLE_10_VALUE_G_MAX (0x000003FFU)
11141 
11142 #define CSL_DSS_VP2_GAMMA_TABLE_10_VALUE_R_MASK (0x3FF00000U)
11143 #define CSL_DSS_VP2_GAMMA_TABLE_10_VALUE_R_SHIFT (0x00000014U)
11144 #define CSL_DSS_VP2_GAMMA_TABLE_10_VALUE_R_MAX (0x000003FFU)
11145 
11146 #define CSL_DSS_VP2_GAMMA_TABLE_10_INDEX_MASK (0x80000000U)
11147 #define CSL_DSS_VP2_GAMMA_TABLE_10_INDEX_SHIFT (0x0000001FU)
11148 #define CSL_DSS_VP2_GAMMA_TABLE_10_INDEX_MAX (0x00000001U)
11149 
11150 /* GAMMA_TABLE_11 */
11151 
11152 #define CSL_DSS_VP2_GAMMA_TABLE_11_VALUE_B_MASK (0x000003FFU)
11153 #define CSL_DSS_VP2_GAMMA_TABLE_11_VALUE_B_SHIFT (0x00000000U)
11154 #define CSL_DSS_VP2_GAMMA_TABLE_11_VALUE_B_MAX (0x000003FFU)
11155 
11156 #define CSL_DSS_VP2_GAMMA_TABLE_11_VALUE_G_MASK (0x000FFC00U)
11157 #define CSL_DSS_VP2_GAMMA_TABLE_11_VALUE_G_SHIFT (0x0000000AU)
11158 #define CSL_DSS_VP2_GAMMA_TABLE_11_VALUE_G_MAX (0x000003FFU)
11159 
11160 #define CSL_DSS_VP2_GAMMA_TABLE_11_VALUE_R_MASK (0x3FF00000U)
11161 #define CSL_DSS_VP2_GAMMA_TABLE_11_VALUE_R_SHIFT (0x00000014U)
11162 #define CSL_DSS_VP2_GAMMA_TABLE_11_VALUE_R_MAX (0x000003FFU)
11163 
11164 #define CSL_DSS_VP2_GAMMA_TABLE_11_INDEX_MASK (0x80000000U)
11165 #define CSL_DSS_VP2_GAMMA_TABLE_11_INDEX_SHIFT (0x0000001FU)
11166 #define CSL_DSS_VP2_GAMMA_TABLE_11_INDEX_MAX (0x00000001U)
11167 
11168 /* GAMMA_TABLE_12 */
11169 
11170 #define CSL_DSS_VP2_GAMMA_TABLE_12_VALUE_B_MASK (0x000003FFU)
11171 #define CSL_DSS_VP2_GAMMA_TABLE_12_VALUE_B_SHIFT (0x00000000U)
11172 #define CSL_DSS_VP2_GAMMA_TABLE_12_VALUE_B_MAX (0x000003FFU)
11173 
11174 #define CSL_DSS_VP2_GAMMA_TABLE_12_VALUE_G_MASK (0x000FFC00U)
11175 #define CSL_DSS_VP2_GAMMA_TABLE_12_VALUE_G_SHIFT (0x0000000AU)
11176 #define CSL_DSS_VP2_GAMMA_TABLE_12_VALUE_G_MAX (0x000003FFU)
11177 
11178 #define CSL_DSS_VP2_GAMMA_TABLE_12_VALUE_R_MASK (0x3FF00000U)
11179 #define CSL_DSS_VP2_GAMMA_TABLE_12_VALUE_R_SHIFT (0x00000014U)
11180 #define CSL_DSS_VP2_GAMMA_TABLE_12_VALUE_R_MAX (0x000003FFU)
11181 
11182 #define CSL_DSS_VP2_GAMMA_TABLE_12_INDEX_MASK (0x80000000U)
11183 #define CSL_DSS_VP2_GAMMA_TABLE_12_INDEX_SHIFT (0x0000001FU)
11184 #define CSL_DSS_VP2_GAMMA_TABLE_12_INDEX_MAX (0x00000001U)
11185 
11186 /* GAMMA_TABLE_13 */
11187 
11188 #define CSL_DSS_VP2_GAMMA_TABLE_13_VALUE_B_MASK (0x000003FFU)
11189 #define CSL_DSS_VP2_GAMMA_TABLE_13_VALUE_B_SHIFT (0x00000000U)
11190 #define CSL_DSS_VP2_GAMMA_TABLE_13_VALUE_B_MAX (0x000003FFU)
11191 
11192 #define CSL_DSS_VP2_GAMMA_TABLE_13_VALUE_G_MASK (0x000FFC00U)
11193 #define CSL_DSS_VP2_GAMMA_TABLE_13_VALUE_G_SHIFT (0x0000000AU)
11194 #define CSL_DSS_VP2_GAMMA_TABLE_13_VALUE_G_MAX (0x000003FFU)
11195 
11196 #define CSL_DSS_VP2_GAMMA_TABLE_13_VALUE_R_MASK (0x3FF00000U)
11197 #define CSL_DSS_VP2_GAMMA_TABLE_13_VALUE_R_SHIFT (0x00000014U)
11198 #define CSL_DSS_VP2_GAMMA_TABLE_13_VALUE_R_MAX (0x000003FFU)
11199 
11200 #define CSL_DSS_VP2_GAMMA_TABLE_13_INDEX_MASK (0x80000000U)
11201 #define CSL_DSS_VP2_GAMMA_TABLE_13_INDEX_SHIFT (0x0000001FU)
11202 #define CSL_DSS_VP2_GAMMA_TABLE_13_INDEX_MAX (0x00000001U)
11203 
11204 /* GAMMA_TABLE_14 */
11205 
11206 #define CSL_DSS_VP2_GAMMA_TABLE_14_VALUE_B_MASK (0x000003FFU)
11207 #define CSL_DSS_VP2_GAMMA_TABLE_14_VALUE_B_SHIFT (0x00000000U)
11208 #define CSL_DSS_VP2_GAMMA_TABLE_14_VALUE_B_MAX (0x000003FFU)
11209 
11210 #define CSL_DSS_VP2_GAMMA_TABLE_14_VALUE_G_MASK (0x000FFC00U)
11211 #define CSL_DSS_VP2_GAMMA_TABLE_14_VALUE_G_SHIFT (0x0000000AU)
11212 #define CSL_DSS_VP2_GAMMA_TABLE_14_VALUE_G_MAX (0x000003FFU)
11213 
11214 #define CSL_DSS_VP2_GAMMA_TABLE_14_VALUE_R_MASK (0x3FF00000U)
11215 #define CSL_DSS_VP2_GAMMA_TABLE_14_VALUE_R_SHIFT (0x00000014U)
11216 #define CSL_DSS_VP2_GAMMA_TABLE_14_VALUE_R_MAX (0x000003FFU)
11217 
11218 #define CSL_DSS_VP2_GAMMA_TABLE_14_INDEX_MASK (0x80000000U)
11219 #define CSL_DSS_VP2_GAMMA_TABLE_14_INDEX_SHIFT (0x0000001FU)
11220 #define CSL_DSS_VP2_GAMMA_TABLE_14_INDEX_MAX (0x00000001U)
11221 
11222 /* GAMMA_TABLE_15 */
11223 
11224 #define CSL_DSS_VP2_GAMMA_TABLE_15_VALUE_B_MASK (0x000003FFU)
11225 #define CSL_DSS_VP2_GAMMA_TABLE_15_VALUE_B_SHIFT (0x00000000U)
11226 #define CSL_DSS_VP2_GAMMA_TABLE_15_VALUE_B_MAX (0x000003FFU)
11227 
11228 #define CSL_DSS_VP2_GAMMA_TABLE_15_VALUE_G_MASK (0x000FFC00U)
11229 #define CSL_DSS_VP2_GAMMA_TABLE_15_VALUE_G_SHIFT (0x0000000AU)
11230 #define CSL_DSS_VP2_GAMMA_TABLE_15_VALUE_G_MAX (0x000003FFU)
11231 
11232 #define CSL_DSS_VP2_GAMMA_TABLE_15_VALUE_R_MASK (0x3FF00000U)
11233 #define CSL_DSS_VP2_GAMMA_TABLE_15_VALUE_R_SHIFT (0x00000014U)
11234 #define CSL_DSS_VP2_GAMMA_TABLE_15_VALUE_R_MAX (0x000003FFU)
11235 
11236 #define CSL_DSS_VP2_GAMMA_TABLE_15_INDEX_MASK (0x80000000U)
11237 #define CSL_DSS_VP2_GAMMA_TABLE_15_INDEX_SHIFT (0x0000001FU)
11238 #define CSL_DSS_VP2_GAMMA_TABLE_15_INDEX_MAX (0x00000001U)
11239 
11240 /* DSS_OLDI_CFG */
11241 
11242 #define CSL_DSS_VP2_DSS_OLDI_CFG_RESERVED1_MASK (0x00003FFFU)
11243 #define CSL_DSS_VP2_DSS_OLDI_CFG_RESERVED1_SHIFT (0x00000000U)
11244 #define CSL_DSS_VP2_DSS_OLDI_CFG_RESERVED1_MAX (0x00003FFFU)
11245 
11246 #define CSL_DSS_VP2_DSS_OLDI_CFG_RESERVED_MASK (0xFFFFC000U)
11247 #define CSL_DSS_VP2_DSS_OLDI_CFG_RESERVED_SHIFT (0x0000000EU)
11248 #define CSL_DSS_VP2_DSS_OLDI_CFG_RESERVED_MAX (0x0003FFFFU)
11249 
11250 /* DSS_OLDI_STATUS */
11251 
11252 #define CSL_DSS_VP2_DSS_OLDI_STATUS_RESERVED_MASK (0xFFFFFFFFU)
11253 #define CSL_DSS_VP2_DSS_OLDI_STATUS_RESERVED_SHIFT (0x00000000U)
11254 #define CSL_DSS_VP2_DSS_OLDI_STATUS_RESERVED_MAX (0xFFFFFFFFU)
11255 
11256 /* DSS_OLDI_LB */
11257 
11258 #define CSL_DSS_VP2_DSS_OLDI_LB_RESERVED_MASK (0xFFFFFFFFU)
11259 #define CSL_DSS_VP2_DSS_OLDI_LB_RESERVED_SHIFT (0x00000000U)
11260 #define CSL_DSS_VP2_DSS_OLDI_LB_RESERVED_MAX (0xFFFFFFFFU)
11261 
11262 /* SECURE */
11263 
11264 #define CSL_DSS_VP2_SECURE_SECURE_MASK (0x00000001U)
11265 #define CSL_DSS_VP2_SECURE_SECURE_SHIFT (0x00000000U)
11266 #define CSL_DSS_VP2_SECURE_SECURE_MAX (0x00000001U)
11267 
11268 #define CSL_DSS_VP2_SECURE_SECURE_VAL_SECUREDIS (0x0U)
11269 #define CSL_DSS_VP2_SECURE_SECURE_VAL_SECUREEN (0x1U)
11270 
11271 #define CSL_DSS_VP2_SECURE_RESERVED_MASK (0xFFFFFFFEU)
11272 #define CSL_DSS_VP2_SECURE_RESERVED_SHIFT (0x00000001U)
11273 #define CSL_DSS_VP2_SECURE_RESERVED_MAX (0x7FFFFFFFU)
11274 
11275 /**************************************************************************
11276 * Hardware Region : OVR3 Registers
11277 **************************************************************************/
11278 
11279 
11280 /**************************************************************************
11281 * Register Overlay Structure
11282 **************************************************************************/
11283 
11284 typedef struct {
11285  volatile uint32_t CONFIG; /* CONFIG */
11286  volatile uint32_t VIRTUALVP; /* VIRTUALVP */
11287  volatile uint32_t DEFAULT_COLOR; /* DEFAULT_COLOR */
11288  volatile uint32_t DEFAULT_COLOR2; /* DEFAULT_COLOR2 */
11289  volatile uint32_t TRANS_COLOR_MAX; /* TRANS_COLOR_MAX */
11290  volatile uint32_t TRANS_COLOR_MAX2; /* TRANS_COLOR_MAX2 */
11291  volatile uint32_t TRANS_COLOR_MIN; /* TRANS_COLOR_MIN */
11292  volatile uint32_t TRANS_COLOR_MIN2; /* TRANS_COLOR_MIN2 */
11293  volatile uint32_t ATTRIBUTES[5U]; /* ATTRIBUTES 0..4 */
11294  volatile uint32_t ATTRIBUTES2[5U]; /* ATTRIBUTES2 0..4 */
11295  volatile uint32_t SECURE; /* SECURE */
11297 
11298 
11299 /**************************************************************************
11300 * Register Macros
11301 **************************************************************************/
11302 
11303 #define CSL_DSS_OVR3_CONFIG (0x00000000U)
11304 #define CSL_DSS_OVR3_VIRTUALVP (0x00000004U)
11305 #define CSL_DSS_OVR3_DEFAULT_COLOR (0x00000008U)
11306 #define CSL_DSS_OVR3_DEFAULT_COLOR2 (0x0000000CU)
11307 #define CSL_DSS_OVR3_TRANS_COLOR_MAX (0x00000010U)
11308 #define CSL_DSS_OVR3_TRANS_COLOR_MAX2 (0x00000014U)
11309 #define CSL_DSS_OVR3_TRANS_COLOR_MIN (0x00000018U)
11310 #define CSL_DSS_OVR3_TRANS_COLOR_MIN2 (0x0000001CU)
11311 #define CSL_DSS_OVR3_ATTRIBUTES(index) (0x00000020U+((uint32_t)(index)*0x4U))
11312 #define CSL_DSS_OVR3_ATTRIBUTES2(index) (0x00000034U+((uint32_t)(index)*0x4U))
11313 #define CSL_DSS_OVR3_SECURE (0x00000048U)
11314 
11315 /**************************************************************************
11316 * Field Definition Macros
11317 **************************************************************************/
11318 
11319 
11320 /* CONFIG */
11321 
11322 #define CSL_DSS_OVR3_CONFIG_RESERVED6_MASK (0x00000001U)
11323 #define CSL_DSS_OVR3_CONFIG_RESERVED6_SHIFT (0x00000000U)
11324 #define CSL_DSS_OVR3_CONFIG_RESERVED6_MAX (0x00000001U)
11325 
11326 #define CSL_DSS_OVR3_CONFIG_COLORBAREN_MASK (0x00000002U)
11327 #define CSL_DSS_OVR3_CONFIG_COLORBAREN_SHIFT (0x00000001U)
11328 #define CSL_DSS_OVR3_CONFIG_COLORBAREN_MAX (0x00000001U)
11329 
11330 #define CSL_DSS_OVR3_CONFIG_COLORBAREN_VAL_COLORBARDIS (0x0U)
11331 #define CSL_DSS_OVR3_CONFIG_COLORBAREN_VAL_COLORBAREN (0x1U)
11332 
11333 #define CSL_DSS_OVR3_CONFIG_RESERVED_MASK (0x000003FCU)
11334 #define CSL_DSS_OVR3_CONFIG_RESERVED_SHIFT (0x00000002U)
11335 #define CSL_DSS_OVR3_CONFIG_RESERVED_MAX (0x000000FFU)
11336 
11337 #define CSL_DSS_OVR3_CONFIG_TCKLCDENABLE_MASK (0x00000400U)
11338 #define CSL_DSS_OVR3_CONFIG_TCKLCDENABLE_SHIFT (0x0000000AU)
11339 #define CSL_DSS_OVR3_CONFIG_TCKLCDENABLE_MAX (0x00000001U)
11340 
11341 #define CSL_DSS_OVR3_CONFIG_TCKLCDENABLE_VAL_DISTCK (0x0U)
11342 #define CSL_DSS_OVR3_CONFIG_TCKLCDENABLE_VAL_ENBTCK (0x1U)
11343 
11344 #define CSL_DSS_OVR3_CONFIG_TCKLCDSELECTION_MASK (0x00000800U)
11345 #define CSL_DSS_OVR3_CONFIG_TCKLCDSELECTION_SHIFT (0x0000000BU)
11346 #define CSL_DSS_OVR3_CONFIG_TCKLCDSELECTION_MAX (0x00000001U)
11347 
11348 #define CSL_DSS_OVR3_CONFIG_TCKLCDSELECTION_VAL_GDTK (0x0U)
11349 #define CSL_DSS_OVR3_CONFIG_TCKLCDSELECTION_VAL_VSTK (0x1U)
11350 
11351 #define CSL_DSS_OVR3_CONFIG_RESERVED2_MASK (0x00001000U)
11352 #define CSL_DSS_OVR3_CONFIG_RESERVED2_SHIFT (0x0000000CU)
11353 #define CSL_DSS_OVR3_CONFIG_RESERVED2_MAX (0x00000001U)
11354 
11355 #define CSL_DSS_OVR3_CONFIG_RESERVED3_MASK (0x00002000U)
11356 #define CSL_DSS_OVR3_CONFIG_RESERVED3_SHIFT (0x0000000DU)
11357 #define CSL_DSS_OVR3_CONFIG_RESERVED3_MAX (0x00000001U)
11358 
11359 #define CSL_DSS_OVR3_CONFIG_RESERVED1_MASK (0xFFFFC000U)
11360 #define CSL_DSS_OVR3_CONFIG_RESERVED1_SHIFT (0x0000000EU)
11361 #define CSL_DSS_OVR3_CONFIG_RESERVED1_MAX (0x0003FFFFU)
11362 
11363 /* VIRTUALVP */
11364 
11365 #define CSL_DSS_OVR3_VIRTUALVP_PPL_MASK (0x00003FFFU)
11366 #define CSL_DSS_OVR3_VIRTUALVP_PPL_SHIFT (0x00000000U)
11367 #define CSL_DSS_OVR3_VIRTUALVP_PPL_MAX (0x00003FFFU)
11368 
11369 #define CSL_DSS_OVR3_VIRTUALVP_LPP_MASK (0x3FFF0000U)
11370 #define CSL_DSS_OVR3_VIRTUALVP_LPP_SHIFT (0x00000010U)
11371 #define CSL_DSS_OVR3_VIRTUALVP_LPP_MAX (0x00003FFFU)
11372 
11373 #define CSL_DSS_OVR3_VIRTUALVP_ENABLE_MASK (0x80000000U)
11374 #define CSL_DSS_OVR3_VIRTUALVP_ENABLE_SHIFT (0x0000001FU)
11375 #define CSL_DSS_OVR3_VIRTUALVP_ENABLE_MAX (0x00000001U)
11376 
11377 /* DEFAULT_COLOR */
11378 
11379 #define CSL_DSS_OVR3_DEFAULT_COLOR_DEFAULTCOLOR_MASK (0xFFFFFFFFU)
11380 #define CSL_DSS_OVR3_DEFAULT_COLOR_DEFAULTCOLOR_SHIFT (0x00000000U)
11381 #define CSL_DSS_OVR3_DEFAULT_COLOR_DEFAULTCOLOR_MAX (0xFFFFFFFFU)
11382 
11383 /* DEFAULT_COLOR2 */
11384 
11385 #define CSL_DSS_OVR3_DEFAULT_COLOR2_DEFAULTCOLOR_MASK (0x0000FFFFU)
11386 #define CSL_DSS_OVR3_DEFAULT_COLOR2_DEFAULTCOLOR_SHIFT (0x00000000U)
11387 #define CSL_DSS_OVR3_DEFAULT_COLOR2_DEFAULTCOLOR_MAX (0x0000FFFFU)
11388 
11389 #define CSL_DSS_OVR3_DEFAULT_COLOR2_RESERVED_MASK (0xFFFF0000U)
11390 #define CSL_DSS_OVR3_DEFAULT_COLOR2_RESERVED_SHIFT (0x00000010U)
11391 #define CSL_DSS_OVR3_DEFAULT_COLOR2_RESERVED_MAX (0x0000FFFFU)
11392 
11393 /* TRANS_COLOR_MAX */
11394 
11395 #define CSL_DSS_OVR3_TRANS_COLOR_MAX_TRANSCOLORKEY_MASK (0xFFFFFFFFU)
11396 #define CSL_DSS_OVR3_TRANS_COLOR_MAX_TRANSCOLORKEY_SHIFT (0x00000000U)
11397 #define CSL_DSS_OVR3_TRANS_COLOR_MAX_TRANSCOLORKEY_MAX (0xFFFFFFFFU)
11398 
11399 /* TRANS_COLOR_MAX2 */
11400 
11401 #define CSL_DSS_OVR3_TRANS_COLOR_MAX2_TRANSCOLORKEY_MASK (0x0000000FU)
11402 #define CSL_DSS_OVR3_TRANS_COLOR_MAX2_TRANSCOLORKEY_SHIFT (0x00000000U)
11403 #define CSL_DSS_OVR3_TRANS_COLOR_MAX2_TRANSCOLORKEY_MAX (0x0000000FU)
11404 
11405 #define CSL_DSS_OVR3_TRANS_COLOR_MAX2_RESERVED_MASK (0xFFFFFFF0U)
11406 #define CSL_DSS_OVR3_TRANS_COLOR_MAX2_RESERVED_SHIFT (0x00000004U)
11407 #define CSL_DSS_OVR3_TRANS_COLOR_MAX2_RESERVED_MAX (0x0FFFFFFFU)
11408 
11409 /* TRANS_COLOR_MIN */
11410 
11411 #define CSL_DSS_OVR3_TRANS_COLOR_MIN_TRANSCOLORKEY_MASK (0xFFFFFFFFU)
11412 #define CSL_DSS_OVR3_TRANS_COLOR_MIN_TRANSCOLORKEY_SHIFT (0x00000000U)
11413 #define CSL_DSS_OVR3_TRANS_COLOR_MIN_TRANSCOLORKEY_MAX (0xFFFFFFFFU)
11414 
11415 /* TRANS_COLOR_MIN2 */
11416 
11417 #define CSL_DSS_OVR3_TRANS_COLOR_MIN2_TRANSCOLORKEY_MASK (0x0000000FU)
11418 #define CSL_DSS_OVR3_TRANS_COLOR_MIN2_TRANSCOLORKEY_SHIFT (0x00000000U)
11419 #define CSL_DSS_OVR3_TRANS_COLOR_MIN2_TRANSCOLORKEY_MAX (0x0000000FU)
11420 
11421 #define CSL_DSS_OVR3_TRANS_COLOR_MIN2_RESERVED_MASK (0xFFFFFFF0U)
11422 #define CSL_DSS_OVR3_TRANS_COLOR_MIN2_RESERVED_SHIFT (0x00000004U)
11423 #define CSL_DSS_OVR3_TRANS_COLOR_MIN2_RESERVED_MAX (0x0FFFFFFFU)
11424 
11425 /* ATTRIBUTES */
11426 
11427 #define CSL_DSS_OVR3_ATTRIBUTES_ENABLE_MASK (0x00000001U)
11428 #define CSL_DSS_OVR3_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
11429 #define CSL_DSS_OVR3_ATTRIBUTES_ENABLE_MAX (0x00000001U)
11430 
11431 #define CSL_DSS_OVR3_ATTRIBUTES_CHANNELIN_MASK (0x0000001EU)
11432 #define CSL_DSS_OVR3_ATTRIBUTES_CHANNELIN_SHIFT (0x00000001U)
11433 #define CSL_DSS_OVR3_ATTRIBUTES_CHANNELIN_MAX (0x0000000FU)
11434 
11435 #define CSL_DSS_OVR3_ATTRIBUTES_CHANNELIN_VAL_VID1 (0x0U)
11436 #define CSL_DSS_OVR3_ATTRIBUTES_CHANNELIN_VAL_VIDL1 (0x1U)
11437 #define CSL_DSS_OVR3_ATTRIBUTES_CHANNELIN_VAL_VID2 (0x2U)
11438 #define CSL_DSS_OVR3_ATTRIBUTES_CHANNELIN_VAL_VIDL2 (0x3U)
11439 #define CSL_DSS_OVR3_ATTRIBUTES_CHANNELIN_VAL_VIRTCH (0x4U)
11440 
11441 /* ATTRIBUTES2 */
11442 
11443 #define CSL_DSS_OVR3_ATTRIBUTES2_POSX_MASK (0x00003FFFU)
11444 #define CSL_DSS_OVR3_ATTRIBUTES2_POSX_SHIFT (0x00000000U)
11445 #define CSL_DSS_OVR3_ATTRIBUTES2_POSX_MAX (0x00003FFFU)
11446 
11447 #define CSL_DSS_OVR3_ATTRIBUTES2_POSY_MASK (0x3FFF0000U)
11448 #define CSL_DSS_OVR3_ATTRIBUTES2_POSY_SHIFT (0x00000010U)
11449 #define CSL_DSS_OVR3_ATTRIBUTES2_POSY_MAX (0x00003FFFU)
11450 
11451 /* SECURE */
11452 
11453 #define CSL_DSS_OVR3_SECURE_SECURE_MASK (0x00000001U)
11454 #define CSL_DSS_OVR3_SECURE_SECURE_SHIFT (0x00000000U)
11455 #define CSL_DSS_OVR3_SECURE_SECURE_MAX (0x00000001U)
11456 
11457 #define CSL_DSS_OVR3_SECURE_SECURE_VAL_SECUREDIS (0x0U)
11458 #define CSL_DSS_OVR3_SECURE_SECURE_VAL_SECUREEN (0x1U)
11459 
11460 #define CSL_DSS_OVR3_SECURE_RESERVED_MASK (0xFFFFFFFEU)
11461 #define CSL_DSS_OVR3_SECURE_RESERVED_SHIFT (0x00000001U)
11462 #define CSL_DSS_OVR3_SECURE_RESERVED_MAX (0x7FFFFFFFU)
11463 
11464 /**************************************************************************
11465 * Hardware Region : VP3 Registers
11466 **************************************************************************/
11467 
11468 
11469 /**************************************************************************
11470 * Register Overlay Structure
11471 **************************************************************************/
11472 
11473 typedef struct {
11474  volatile uint32_t CONFIG; /* CONFIG */
11475  volatile uint32_t CONTROL; /* CONTROL */
11476  volatile uint32_t CSC_COEF0; /* CSC_COEF0 */
11477  volatile uint32_t CSC_COEF1; /* CSC_COEF1 */
11478  volatile uint32_t CSC_COEF2; /* CSC_COEF2 */
11479  volatile uint32_t DATA_CYCLE_0; /* DATA_CYCLE_0 */
11480  volatile uint32_t DATA_CYCLE_1; /* DATA_CYCLE_1 */
11481  volatile uint32_t DATA_CYCLE_2; /* DATA_CYCLE_2 */
11482  volatile uint8_t Resv_68[36];
11483  volatile uint32_t LINE_NUMBER; /* LINE_NUMBER */
11484  volatile uint8_t Resv_76[4];
11485  volatile uint32_t POL_FREQ; /* POL_FREQ */
11486  volatile uint32_t SIZE_SCREEN; /* SIZE_SCREEN */
11487  volatile uint32_t TIMING_H; /* TIMING_H */
11488  volatile uint32_t TIMING_V; /* TIMING_V */
11489  volatile uint32_t CSC_COEF3; /* CSC_COEF3 */
11490  volatile uint32_t CSC_COEF4; /* CSC_COEF4 */
11491  volatile uint32_t CSC_COEF5; /* CSC_COEF5 */
11492  volatile uint32_t CSC_COEF6; /* CSC_COEF6 */
11493  volatile uint32_t CSC_COEF7; /* CSC_COEF7 */
11494  volatile uint32_t SAFETY_ATTRIBUTES[8U]; /* SAFETY_ATTRIBUTES 0..7 */
11495  volatile uint32_t SAFETY_CAPT_SIGNATURE[8U]; /* SAFETY_CAPT_SIGNATURE 0..7 */
11496  volatile uint32_t SAFETY_POSITION[8U]; /* SAFETY_POSITION 0..7 */
11497  volatile uint32_t SAFETY_REF_SIGNATURE[8U]; /* SAFETY_REF_SIGNATURE 0..7 */
11498  volatile uint32_t SAFETY_SIZE[8U]; /* SAFETY_SIZE 0..7 */
11499  volatile uint32_t SAFETY_LFSR_SEED; /* SAFETY_LFSR_SEED */
11500  volatile uint8_t Resv_288[12];
11501  volatile uint32_t GAMMA_TABLE_0; /* GAMMA_TABLE_0 */
11502  volatile uint32_t GAMMA_TABLE_1; /* GAMMA_TABLE_1 */
11503  volatile uint32_t GAMMA_TABLE_2; /* GAMMA_TABLE_2 */
11504  volatile uint32_t GAMMA_TABLE_3; /* GAMMA_TABLE_3 */
11505  volatile uint32_t GAMMA_TABLE_4; /* GAMMA_TABLE_4 */
11506  volatile uint32_t GAMMA_TABLE_5; /* GAMMA_TABLE_5 */
11507  volatile uint32_t GAMMA_TABLE_6; /* GAMMA_TABLE_6 */
11508  volatile uint32_t GAMMA_TABLE_7; /* GAMMA_TABLE_7 */
11509  volatile uint32_t GAMMA_TABLE_8; /* GAMMA_TABLE_8 */
11510  volatile uint32_t GAMMA_TABLE_9; /* GAMMA_TABLE_9 */
11511  volatile uint32_t GAMMA_TABLE_10; /* GAMMA_TABLE_10 */
11512  volatile uint32_t GAMMA_TABLE_11; /* GAMMA_TABLE_11 */
11513  volatile uint32_t GAMMA_TABLE_12; /* GAMMA_TABLE_12 */
11514  volatile uint32_t GAMMA_TABLE_13; /* GAMMA_TABLE_13 */
11515  volatile uint32_t GAMMA_TABLE_14; /* GAMMA_TABLE_14 */
11516  volatile uint32_t GAMMA_TABLE_15; /* GAMMA_TABLE_15 */
11517  volatile uint32_t DSS_OLDI_CFG; /* DSS_OLDI_CFG */
11518  volatile uint32_t DSS_OLDI_STATUS; /* DSS_OLDI_STATUS */
11519  volatile uint32_t DSS_OLDI_LB; /* DSS_OLDI_LB */
11520  volatile uint8_t Resv_376[12];
11521  volatile uint32_t SECURE; /* SECURE */
11522 } CSL_dss_vp3Regs;
11523 
11524 
11525 /**************************************************************************
11526 * Register Macros
11527 **************************************************************************/
11528 
11529 #define CSL_DSS_VP3_CONFIG (0x00000000U)
11530 #define CSL_DSS_VP3_CONTROL (0x00000004U)
11531 #define CSL_DSS_VP3_CSC_COEF0 (0x00000008U)
11532 #define CSL_DSS_VP3_CSC_COEF1 (0x0000000CU)
11533 #define CSL_DSS_VP3_CSC_COEF2 (0x00000010U)
11534 #define CSL_DSS_VP3_DATA_CYCLE_0 (0x00000014U)
11535 #define CSL_DSS_VP3_DATA_CYCLE_1 (0x00000018U)
11536 #define CSL_DSS_VP3_DATA_CYCLE_2 (0x0000001CU)
11537 #define CSL_DSS_VP3_LINE_NUMBER (0x00000044U)
11538 #define CSL_DSS_VP3_POL_FREQ (0x0000004CU)
11539 #define CSL_DSS_VP3_SIZE_SCREEN (0x00000050U)
11540 #define CSL_DSS_VP3_TIMING_H (0x00000054U)
11541 #define CSL_DSS_VP3_TIMING_V (0x00000058U)
11542 #define CSL_DSS_VP3_CSC_COEF3 (0x0000005CU)
11543 #define CSL_DSS_VP3_CSC_COEF4 (0x00000060U)
11544 #define CSL_DSS_VP3_CSC_COEF5 (0x00000064U)
11545 #define CSL_DSS_VP3_CSC_COEF6 (0x00000068U)
11546 #define CSL_DSS_VP3_CSC_COEF7 (0x0000006CU)
11547 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES(index) (0x00000070U+((uint32_t)(index)*0x4U))
11548 #define CSL_DSS_VP3_SAFETY_CAPT_SIGNATURE(index) (0x00000090U+((uint32_t)(index)*0x4U))
11549 #define CSL_DSS_VP3_SAFETY_POSITION(index) (0x000000B0U+((uint32_t)(index)*0x4U))
11550 #define CSL_DSS_VP3_SAFETY_REF_SIGNATURE(index) (0x000000D0U+((uint32_t)(index)*0x4U))
11551 #define CSL_DSS_VP3_SAFETY_SIZE(index) (0x000000F0U+((uint32_t)(index)*0x4U))
11552 #define CSL_DSS_VP3_SAFETY_LFSR_SEED (0x00000110U)
11553 #define CSL_DSS_VP3_GAMMA_TABLE_0 (0x00000120U)
11554 #define CSL_DSS_VP3_GAMMA_TABLE_1 (0x00000124U)
11555 #define CSL_DSS_VP3_GAMMA_TABLE_2 (0x00000128U)
11556 #define CSL_DSS_VP3_GAMMA_TABLE_3 (0x0000012CU)
11557 #define CSL_DSS_VP3_GAMMA_TABLE_4 (0x00000130U)
11558 #define CSL_DSS_VP3_GAMMA_TABLE_5 (0x00000134U)
11559 #define CSL_DSS_VP3_GAMMA_TABLE_6 (0x00000138U)
11560 #define CSL_DSS_VP3_GAMMA_TABLE_7 (0x0000013CU)
11561 #define CSL_DSS_VP3_GAMMA_TABLE_8 (0x00000140U)
11562 #define CSL_DSS_VP3_GAMMA_TABLE_9 (0x00000144U)
11563 #define CSL_DSS_VP3_GAMMA_TABLE_10 (0x00000148U)
11564 #define CSL_DSS_VP3_GAMMA_TABLE_11 (0x0000014CU)
11565 #define CSL_DSS_VP3_GAMMA_TABLE_12 (0x00000150U)
11566 #define CSL_DSS_VP3_GAMMA_TABLE_13 (0x00000154U)
11567 #define CSL_DSS_VP3_GAMMA_TABLE_14 (0x00000158U)
11568 #define CSL_DSS_VP3_GAMMA_TABLE_15 (0x0000015CU)
11569 #define CSL_DSS_VP3_DSS_OLDI_CFG (0x00000160U)
11570 #define CSL_DSS_VP3_DSS_OLDI_STATUS (0x00000164U)
11571 #define CSL_DSS_VP3_DSS_OLDI_LB (0x00000168U)
11572 #define CSL_DSS_VP3_SECURE (0x00000178U)
11573 
11574 /**************************************************************************
11575 * Field Definition Macros
11576 **************************************************************************/
11577 
11578 
11579 /* CONFIG */
11580 
11581 #define CSL_DSS_VP3_CONFIG_PIXELGATED_MASK (0x00000001U)
11582 #define CSL_DSS_VP3_CONFIG_PIXELGATED_SHIFT (0x00000000U)
11583 #define CSL_DSS_VP3_CONFIG_PIXELGATED_MAX (0x00000001U)
11584 
11585 #define CSL_DSS_VP3_CONFIG_PIXELGATED_VAL_PCLKTOGA (0x0U)
11586 #define CSL_DSS_VP3_CONFIG_PIXELGATED_VAL_PCLKTOGV (0x1U)
11587 
11588 #define CSL_DSS_VP3_CONFIG_DATAENABLEGATED_MASK (0x00000002U)
11589 #define CSL_DSS_VP3_CONFIG_DATAENABLEGATED_SHIFT (0x00000001U)
11590 #define CSL_DSS_VP3_CONFIG_DATAENABLEGATED_MAX (0x00000001U)
11591 
11592 #define CSL_DSS_VP3_CONFIG_DATAENABLEGATED_VAL_DEGDIS (0x0U)
11593 #define CSL_DSS_VP3_CONFIG_DATAENABLEGATED_VAL_DEGENB (0x1U)
11594 
11595 #define CSL_DSS_VP3_CONFIG_GAMMAENABLE_MASK (0x00000004U)
11596 #define CSL_DSS_VP3_CONFIG_GAMMAENABLE_SHIFT (0x00000002U)
11597 #define CSL_DSS_VP3_CONFIG_GAMMAENABLE_MAX (0x00000001U)
11598 
11599 #define CSL_DSS_VP3_CONFIG_GAMMAENABLE_VAL_GAMMADIS (0x0U)
11600 #define CSL_DSS_VP3_CONFIG_GAMMAENABLE_VAL_GAMMAENB (0x1U)
11601 
11602 #define CSL_DSS_VP3_CONFIG_HDMIMODE_MASK (0x00000008U)
11603 #define CSL_DSS_VP3_CONFIG_HDMIMODE_SHIFT (0x00000003U)
11604 #define CSL_DSS_VP3_CONFIG_HDMIMODE_MAX (0x00000001U)
11605 
11606 #define CSL_DSS_VP3_CONFIG_PIXELDATAGATED_MASK (0x00000010U)
11607 #define CSL_DSS_VP3_CONFIG_PIXELDATAGATED_SHIFT (0x00000004U)
11608 #define CSL_DSS_VP3_CONFIG_PIXELDATAGATED_MAX (0x00000001U)
11609 
11610 #define CSL_DSS_VP3_CONFIG_PIXELDATAGATED_VAL_PDGDIS (0x0U)
11611 #define CSL_DSS_VP3_CONFIG_PIXELDATAGATED_VAL_PDGENB (0x1U)
11612 
11613 #define CSL_DSS_VP3_CONFIG_PIXELCLOCKGATED_MASK (0x00000020U)
11614 #define CSL_DSS_VP3_CONFIG_PIXELCLOCKGATED_SHIFT (0x00000005U)
11615 #define CSL_DSS_VP3_CONFIG_PIXELCLOCKGATED_MAX (0x00000001U)
11616 
11617 #define CSL_DSS_VP3_CONFIG_PIXELCLOCKGATED_VAL_PCGDIS (0x0U)
11618 #define CSL_DSS_VP3_CONFIG_PIXELCLOCKGATED_VAL_PCGENB (0x1U)
11619 
11620 #define CSL_DSS_VP3_CONFIG_HSYNCGATED_MASK (0x00000040U)
11621 #define CSL_DSS_VP3_CONFIG_HSYNCGATED_SHIFT (0x00000006U)
11622 #define CSL_DSS_VP3_CONFIG_HSYNCGATED_MAX (0x00000001U)
11623 
11624 #define CSL_DSS_VP3_CONFIG_HSYNCGATED_VAL_HGDIS (0x0U)
11625 #define CSL_DSS_VP3_CONFIG_HSYNCGATED_VAL_HGENB (0x1U)
11626 
11627 #define CSL_DSS_VP3_CONFIG_VSYNCGATED_MASK (0x00000080U)
11628 #define CSL_DSS_VP3_CONFIG_VSYNCGATED_SHIFT (0x00000007U)
11629 #define CSL_DSS_VP3_CONFIG_VSYNCGATED_MAX (0x00000001U)
11630 
11631 #define CSL_DSS_VP3_CONFIG_VSYNCGATED_VAL_VGDIS (0x0U)
11632 #define CSL_DSS_VP3_CONFIG_VSYNCGATED_VAL_VGENB (0x1U)
11633 
11634 #define CSL_DSS_VP3_CONFIG_EXTERNALSYNCEN_MASK (0x00000100U)
11635 #define CSL_DSS_VP3_CONFIG_EXTERNALSYNCEN_SHIFT (0x00000008U)
11636 #define CSL_DSS_VP3_CONFIG_EXTERNALSYNCEN_MAX (0x00000001U)
11637 
11638 #define CSL_DSS_VP3_CONFIG_RESERVED1_MASK (0x00007E00U)
11639 #define CSL_DSS_VP3_CONFIG_RESERVED1_SHIFT (0x00000009U)
11640 #define CSL_DSS_VP3_CONFIG_RESERVED1_MAX (0x0000003FU)
11641 
11642 #define CSL_DSS_VP3_CONFIG_CPR_MASK (0x00008000U)
11643 #define CSL_DSS_VP3_CONFIG_CPR_SHIFT (0x0000000FU)
11644 #define CSL_DSS_VP3_CONFIG_CPR_MAX (0x00000001U)
11645 
11646 #define CSL_DSS_VP3_CONFIG_BUFFERHANDSHAKE_MASK (0x00010000U)
11647 #define CSL_DSS_VP3_CONFIG_BUFFERHANDSHAKE_SHIFT (0x00000010U)
11648 #define CSL_DSS_VP3_CONFIG_BUFFERHANDSHAKE_MAX (0x00000001U)
11649 
11650 #define CSL_DSS_VP3_CONFIG_RESERVED2_MASK (0x000E0000U)
11651 #define CSL_DSS_VP3_CONFIG_RESERVED2_SHIFT (0x00000011U)
11652 #define CSL_DSS_VP3_CONFIG_RESERVED2_MAX (0x00000007U)
11653 
11654 #define CSL_DSS_VP3_CONFIG_BT656ENABLE_MASK (0x00100000U)
11655 #define CSL_DSS_VP3_CONFIG_BT656ENABLE_SHIFT (0x00000014U)
11656 #define CSL_DSS_VP3_CONFIG_BT656ENABLE_MAX (0x00000001U)
11657 
11658 #define CSL_DSS_VP3_CONFIG_BT656ENABLE_VAL_DISABLE (0x0U)
11659 #define CSL_DSS_VP3_CONFIG_BT656ENABLE_VAL_ENABLE (0x1U)
11660 
11661 #define CSL_DSS_VP3_CONFIG_BT1120ENABLE_MASK (0x00200000U)
11662 #define CSL_DSS_VP3_CONFIG_BT1120ENABLE_SHIFT (0x00000015U)
11663 #define CSL_DSS_VP3_CONFIG_BT1120ENABLE_MAX (0x00000001U)
11664 
11665 #define CSL_DSS_VP3_CONFIG_BT1120ENABLE_VAL_DISABLE (0x0U)
11666 #define CSL_DSS_VP3_CONFIG_BT1120ENABLE_VAL_ENABLE (0x1U)
11667 
11668 #define CSL_DSS_VP3_CONFIG_OUTPUTMODEENABLE_MASK (0x00400000U)
11669 #define CSL_DSS_VP3_CONFIG_OUTPUTMODEENABLE_SHIFT (0x00000016U)
11670 #define CSL_DSS_VP3_CONFIG_OUTPUTMODEENABLE_MAX (0x00000001U)
11671 
11672 #define CSL_DSS_VP3_CONFIG_OUTPUTMODEENABLE_VAL_DISABLE (0x0U)
11673 #define CSL_DSS_VP3_CONFIG_OUTPUTMODEENABLE_VAL_ENABLE (0x1U)
11674 
11675 #define CSL_DSS_VP3_CONFIG_FIDFIRST_MASK (0x00800000U)
11676 #define CSL_DSS_VP3_CONFIG_FIDFIRST_SHIFT (0x00000017U)
11677 #define CSL_DSS_VP3_CONFIG_FIDFIRST_MAX (0x00000001U)
11678 
11679 #define CSL_DSS_VP3_CONFIG_FIDFIRST_VAL_EVEN (0x0U)
11680 #define CSL_DSS_VP3_CONFIG_FIDFIRST_VAL_ODD (0x1U)
11681 
11682 #define CSL_DSS_VP3_CONFIG_COLORCONVENABLE_MASK (0x01000000U)
11683 #define CSL_DSS_VP3_CONFIG_COLORCONVENABLE_SHIFT (0x00000018U)
11684 #define CSL_DSS_VP3_CONFIG_COLORCONVENABLE_MAX (0x00000001U)
11685 
11686 #define CSL_DSS_VP3_CONFIG_COLORCONVENABLE_VAL_COLSPCDIS (0x0U)
11687 #define CSL_DSS_VP3_CONFIG_COLORCONVENABLE_VAL_COLSPCENB (0x1U)
11688 
11689 #define CSL_DSS_VP3_CONFIG_FULLRANGE_MASK (0x02000000U)
11690 #define CSL_DSS_VP3_CONFIG_FULLRANGE_SHIFT (0x00000019U)
11691 #define CSL_DSS_VP3_CONFIG_FULLRANGE_MAX (0x00000001U)
11692 
11693 #define CSL_DSS_VP3_CONFIG_FULLRANGE_VAL_LIMRANGE (0x0U)
11694 #define CSL_DSS_VP3_CONFIG_FULLRANGE_VAL_FULLRANGE (0x1U)
11695 
11696 #define CSL_DSS_VP3_CONFIG_COLORCONVPOS_MASK (0x04000000U)
11697 #define CSL_DSS_VP3_CONFIG_COLORCONVPOS_SHIFT (0x0000001AU)
11698 #define CSL_DSS_VP3_CONFIG_COLORCONVPOS_MAX (0x00000001U)
11699 
11700 #define CSL_DSS_VP3_CONFIG_COLORCONVPOS_VAL_AFTERGAMMA (0x0U)
11701 #define CSL_DSS_VP3_CONFIG_COLORCONVPOS_VAL_BEFOREGAMMA (0x1U)
11702 
11703 #define CSL_DSS_VP3_CONFIG_RESERVED3_MASK (0xF8000000U)
11704 #define CSL_DSS_VP3_CONFIG_RESERVED3_SHIFT (0x0000001BU)
11705 #define CSL_DSS_VP3_CONFIG_RESERVED3_MAX (0x0000001FU)
11706 
11707 /* CONTROL */
11708 
11709 #define CSL_DSS_VP3_CONTROL_ENABLE_MASK (0x00000001U)
11710 #define CSL_DSS_VP3_CONTROL_ENABLE_SHIFT (0x00000000U)
11711 #define CSL_DSS_VP3_CONTROL_ENABLE_MAX (0x00000001U)
11712 
11713 #define CSL_DSS_VP3_CONTROL_ENABLE_VAL_LCDOPDIS (0x0U)
11714 #define CSL_DSS_VP3_CONTROL_ENABLE_VAL_LCDOPENB (0x1U)
11715 
11716 #define CSL_DSS_VP3_CONTROL_VPPROGLINENUMBERMODULO_MASK (0x00000002U)
11717 #define CSL_DSS_VP3_CONTROL_VPPROGLINENUMBERMODULO_SHIFT (0x00000001U)
11718 #define CSL_DSS_VP3_CONTROL_VPPROGLINENUMBERMODULO_MAX (0x00000001U)
11719 
11720 #define CSL_DSS_VP3_CONTROL_VPPROGLINENUMBERMODULO_VAL_MODDIS (0x0U)
11721 #define CSL_DSS_VP3_CONTROL_VPPROGLINENUMBERMODULO_VAL_MODEN (0x1U)
11722 
11723 #define CSL_DSS_VP3_CONTROL_MONOCOLOR_MASK (0x00000004U)
11724 #define CSL_DSS_VP3_CONTROL_MONOCOLOR_SHIFT (0x00000002U)
11725 #define CSL_DSS_VP3_CONTROL_MONOCOLOR_MAX (0x00000001U)
11726 
11727 #define CSL_DSS_VP3_CONTROL_STN_MASK (0x00000008U)
11728 #define CSL_DSS_VP3_CONTROL_STN_SHIFT (0x00000003U)
11729 #define CSL_DSS_VP3_CONTROL_STN_MAX (0x00000001U)
11730 
11731 #define CSL_DSS_VP3_CONTROL_M8B_MASK (0x00000010U)
11732 #define CSL_DSS_VP3_CONTROL_M8B_SHIFT (0x00000004U)
11733 #define CSL_DSS_VP3_CONTROL_M8B_MAX (0x00000001U)
11734 
11735 #define CSL_DSS_VP3_CONTROL_GOBIT_MASK (0x00000020U)
11736 #define CSL_DSS_VP3_CONTROL_GOBIT_SHIFT (0x00000005U)
11737 #define CSL_DSS_VP3_CONTROL_GOBIT_MAX (0x00000001U)
11738 
11739 #define CSL_DSS_VP3_CONTROL_GOBIT_VAL_HFUISR (0x0U)
11740 #define CSL_DSS_VP3_CONTROL_GOBIT_VAL_UFPSR (0x1U)
11741 
11742 #define CSL_DSS_VP3_CONTROL_DPIENABLE_MASK (0x00000040U)
11743 #define CSL_DSS_VP3_CONTROL_DPIENABLE_SHIFT (0x00000006U)
11744 #define CSL_DSS_VP3_CONTROL_DPIENABLE_MAX (0x00000001U)
11745 
11746 #define CSL_DSS_VP3_CONTROL_DPIENABLE_VAL_DPIOPDIS (0x0U)
11747 #define CSL_DSS_VP3_CONTROL_DPIENABLE_VAL_DPIOPENB (0x1U)
11748 
11749 #define CSL_DSS_VP3_CONTROL_STDITHERENABLE_MASK (0x00000080U)
11750 #define CSL_DSS_VP3_CONTROL_STDITHERENABLE_SHIFT (0x00000007U)
11751 #define CSL_DSS_VP3_CONTROL_STDITHERENABLE_MAX (0x00000001U)
11752 
11753 #define CSL_DSS_VP3_CONTROL_STDITHERENABLE_VAL_STDITHDIS (0x0U)
11754 #define CSL_DSS_VP3_CONTROL_STDITHERENABLE_VAL_STDITHENB (0x1U)
11755 
11756 #define CSL_DSS_VP3_CONTROL_DATALINES_MASK (0x00000700U)
11757 #define CSL_DSS_VP3_CONTROL_DATALINES_SHIFT (0x00000008U)
11758 #define CSL_DSS_VP3_CONTROL_DATALINES_MAX (0x00000007U)
11759 
11760 #define CSL_DSS_VP3_CONTROL_DATALINES_VAL_OALSB12B (0x0U)
11761 #define CSL_DSS_VP3_CONTROL_DATALINES_VAL_OALSB16B (0x1U)
11762 #define CSL_DSS_VP3_CONTROL_DATALINES_VAL_OALSB18B (0x2U)
11763 #define CSL_DSS_VP3_CONTROL_DATALINES_VAL_OALSB24B (0x3U)
11764 #define CSL_DSS_VP3_CONTROL_DATALINES_VAL_OALSB30B (0x4U)
11765 #define CSL_DSS_VP3_CONTROL_DATALINES_VAL_OALSB36B (0x5U)
11766 
11767 #define CSL_DSS_VP3_CONTROL_STALLMODE_MASK (0x00000800U)
11768 #define CSL_DSS_VP3_CONTROL_STALLMODE_SHIFT (0x0000000BU)
11769 #define CSL_DSS_VP3_CONTROL_STALLMODE_MAX (0x00000001U)
11770 
11771 #define CSL_DSS_VP3_CONTROL_STALLMODE_VAL_STALLDIS (0x0U)
11772 #define CSL_DSS_VP3_CONTROL_STALLMODE_VAL_STALLENB (0x1U)
11773 
11774 #define CSL_DSS_VP3_CONTROL_STALLMODETYPE_MASK (0x00001000U)
11775 #define CSL_DSS_VP3_CONTROL_STALLMODETYPE_SHIFT (0x0000000CU)
11776 #define CSL_DSS_VP3_CONTROL_STALLMODETYPE_MAX (0x00000001U)
11777 
11778 #define CSL_DSS_VP3_CONTROL_STALLMODETYPE_VAL_COMMANDMODE (0x0U)
11779 #define CSL_DSS_VP3_CONTROL_STALLMODETYPE_VAL_VIDEOMODE (0x1U)
11780 
11781 #define CSL_DSS_VP3_CONTROL_RESERVED3_MASK (0x00002000U)
11782 #define CSL_DSS_VP3_CONTROL_RESERVED3_SHIFT (0x0000000DU)
11783 #define CSL_DSS_VP3_CONTROL_RESERVED3_MAX (0x00000001U)
11784 
11785 #define CSL_DSS_VP3_CONTROL_HT_MASK (0x0001C000U)
11786 #define CSL_DSS_VP3_CONTROL_HT_SHIFT (0x0000000EU)
11787 #define CSL_DSS_VP3_CONTROL_HT_MAX (0x00000007U)
11788 
11789 #define CSL_DSS_VP3_CONTROL_RESERVED1_MASK (0x000E0000U)
11790 #define CSL_DSS_VP3_CONTROL_RESERVED1_SHIFT (0x00000011U)
11791 #define CSL_DSS_VP3_CONTROL_RESERVED1_MAX (0x00000007U)
11792 
11793 #define CSL_DSS_VP3_CONTROL_TDMENABLE_MASK (0x00100000U)
11794 #define CSL_DSS_VP3_CONTROL_TDMENABLE_SHIFT (0x00000014U)
11795 #define CSL_DSS_VP3_CONTROL_TDMENABLE_MAX (0x00000001U)
11796 
11797 #define CSL_DSS_VP3_CONTROL_TDMENABLE_VAL_TDMDIS (0x0U)
11798 #define CSL_DSS_VP3_CONTROL_TDMENABLE_VAL_TDMENB (0x1U)
11799 
11800 #define CSL_DSS_VP3_CONTROL_TDMPARALLELMODE_MASK (0x00600000U)
11801 #define CSL_DSS_VP3_CONTROL_TDMPARALLELMODE_SHIFT (0x00000015U)
11802 #define CSL_DSS_VP3_CONTROL_TDMPARALLELMODE_MAX (0x00000003U)
11803 
11804 #define CSL_DSS_VP3_CONTROL_TDMPARALLELMODE_VAL_8BPARAINT (0x0U)
11805 #define CSL_DSS_VP3_CONTROL_TDMPARALLELMODE_VAL_9BPARAINT (0x1U)
11806 #define CSL_DSS_VP3_CONTROL_TDMPARALLELMODE_VAL_12BPARAINT (0x2U)
11807 #define CSL_DSS_VP3_CONTROL_TDMPARALLELMODE_VAL_16BPARAINT (0x3U)
11808 
11809 #define CSL_DSS_VP3_CONTROL_TDMCYCLEFORMAT_MASK (0x01800000U)
11810 #define CSL_DSS_VP3_CONTROL_TDMCYCLEFORMAT_SHIFT (0x00000017U)
11811 #define CSL_DSS_VP3_CONTROL_TDMCYCLEFORMAT_MAX (0x00000003U)
11812 
11813 #define CSL_DSS_VP3_CONTROL_TDMCYCLEFORMAT_VAL_1CYCPERPIX (0x0U)
11814 #define CSL_DSS_VP3_CONTROL_TDMCYCLEFORMAT_VAL_2CYCPERPIX (0x1U)
11815 #define CSL_DSS_VP3_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPERPIX (0x2U)
11816 #define CSL_DSS_VP3_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPER2PIX (0x3U)
11817 
11818 #define CSL_DSS_VP3_CONTROL_TDMUNUSEDBITS_MASK (0x06000000U)
11819 #define CSL_DSS_VP3_CONTROL_TDMUNUSEDBITS_SHIFT (0x00000019U)
11820 #define CSL_DSS_VP3_CONTROL_TDMUNUSEDBITS_MAX (0x00000003U)
11821 
11822 #define CSL_DSS_VP3_CONTROL_TDMUNUSEDBITS_VAL_LOWLEVEL (0x0U)
11823 #define CSL_DSS_VP3_CONTROL_TDMUNUSEDBITS_VAL_HIGHLEVEL (0x1U)
11824 #define CSL_DSS_VP3_CONTROL_TDMUNUSEDBITS_VAL_UNCHANGED (0x2U)
11825 #define CSL_DSS_VP3_CONTROL_TDMUNUSEDBITS_VAL_RES (0x3U)
11826 
11827 #define CSL_DSS_VP3_CONTROL_RESERVED_MASK (0x38000000U)
11828 #define CSL_DSS_VP3_CONTROL_RESERVED_SHIFT (0x0000001BU)
11829 #define CSL_DSS_VP3_CONTROL_RESERVED_MAX (0x00000007U)
11830 
11831 #define CSL_DSS_VP3_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_MASK (0xC0000000U)
11832 #define CSL_DSS_VP3_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_SHIFT (0x0000001EU)
11833 #define CSL_DSS_VP3_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_MAX (0x00000003U)
11834 
11835 #define CSL_DSS_VP3_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_ONEFRAME (0x0U)
11836 #define CSL_DSS_VP3_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_TWOFRAMES (0x1U)
11837 #define CSL_DSS_VP3_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_FOURFRAMES (0x2U)
11838 #define CSL_DSS_VP3_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_RESERVED (0x3U)
11839 
11840 /* CSC_COEF0 */
11841 
11842 #define CSL_DSS_VP3_CSC_COEF0_C00_MASK (0x000007FFU)
11843 #define CSL_DSS_VP3_CSC_COEF0_C00_SHIFT (0x00000000U)
11844 #define CSL_DSS_VP3_CSC_COEF0_C00_MAX (0x000007FFU)
11845 
11846 #define CSL_DSS_VP3_CSC_COEF0_RESERVED_53_MASK (0x0000F800U)
11847 #define CSL_DSS_VP3_CSC_COEF0_RESERVED_53_SHIFT (0x0000000BU)
11848 #define CSL_DSS_VP3_CSC_COEF0_RESERVED_53_MAX (0x0000001FU)
11849 
11850 #define CSL_DSS_VP3_CSC_COEF0_C01_MASK (0x07FF0000U)
11851 #define CSL_DSS_VP3_CSC_COEF0_C01_SHIFT (0x00000010U)
11852 #define CSL_DSS_VP3_CSC_COEF0_C01_MAX (0x000007FFU)
11853 
11854 #define CSL_DSS_VP3_CSC_COEF0_RESERVED_52_MASK (0xF8000000U)
11855 #define CSL_DSS_VP3_CSC_COEF0_RESERVED_52_SHIFT (0x0000001BU)
11856 #define CSL_DSS_VP3_CSC_COEF0_RESERVED_52_MAX (0x0000001FU)
11857 
11858 /* CSC_COEF1 */
11859 
11860 #define CSL_DSS_VP3_CSC_COEF1_C02_MASK (0x000007FFU)
11861 #define CSL_DSS_VP3_CSC_COEF1_C02_SHIFT (0x00000000U)
11862 #define CSL_DSS_VP3_CSC_COEF1_C02_MAX (0x000007FFU)
11863 
11864 #define CSL_DSS_VP3_CSC_COEF1_RESERVED_55_MASK (0x0000F800U)
11865 #define CSL_DSS_VP3_CSC_COEF1_RESERVED_55_SHIFT (0x0000000BU)
11866 #define CSL_DSS_VP3_CSC_COEF1_RESERVED_55_MAX (0x0000001FU)
11867 
11868 #define CSL_DSS_VP3_CSC_COEF1_C10_MASK (0x07FF0000U)
11869 #define CSL_DSS_VP3_CSC_COEF1_C10_SHIFT (0x00000010U)
11870 #define CSL_DSS_VP3_CSC_COEF1_C10_MAX (0x000007FFU)
11871 
11872 #define CSL_DSS_VP3_CSC_COEF1_RESERVED_54_MASK (0xF8000000U)
11873 #define CSL_DSS_VP3_CSC_COEF1_RESERVED_54_SHIFT (0x0000001BU)
11874 #define CSL_DSS_VP3_CSC_COEF1_RESERVED_54_MAX (0x0000001FU)
11875 
11876 /* CSC_COEF2 */
11877 
11878 #define CSL_DSS_VP3_CSC_COEF2_C11_MASK (0x000007FFU)
11879 #define CSL_DSS_VP3_CSC_COEF2_C11_SHIFT (0x00000000U)
11880 #define CSL_DSS_VP3_CSC_COEF2_C11_MAX (0x000007FFU)
11881 
11882 #define CSL_DSS_VP3_CSC_COEF2_RESERVED_57_MASK (0x0000F800U)
11883 #define CSL_DSS_VP3_CSC_COEF2_RESERVED_57_SHIFT (0x0000000BU)
11884 #define CSL_DSS_VP3_CSC_COEF2_RESERVED_57_MAX (0x0000001FU)
11885 
11886 #define CSL_DSS_VP3_CSC_COEF2_C12_MASK (0x07FF0000U)
11887 #define CSL_DSS_VP3_CSC_COEF2_C12_SHIFT (0x00000010U)
11888 #define CSL_DSS_VP3_CSC_COEF2_C12_MAX (0x000007FFU)
11889 
11890 #define CSL_DSS_VP3_CSC_COEF2_RESERVED_56_MASK (0xF8000000U)
11891 #define CSL_DSS_VP3_CSC_COEF2_RESERVED_56_SHIFT (0x0000001BU)
11892 #define CSL_DSS_VP3_CSC_COEF2_RESERVED_56_MAX (0x0000001FU)
11893 
11894 /* DATA_CYCLE_0 */
11895 
11896 #define CSL_DSS_VP3_DATA_CYCLE_0_NBBITSPIXEL1_MASK (0x0000001FU)
11897 #define CSL_DSS_VP3_DATA_CYCLE_0_NBBITSPIXEL1_SHIFT (0x00000000U)
11898 #define CSL_DSS_VP3_DATA_CYCLE_0_NBBITSPIXEL1_MAX (0x0000001FU)
11899 
11900 #define CSL_DSS_VP3_DATA_CYCLE_0_RESERVED_4_MASK (0x000000E0U)
11901 #define CSL_DSS_VP3_DATA_CYCLE_0_RESERVED_4_SHIFT (0x00000005U)
11902 #define CSL_DSS_VP3_DATA_CYCLE_0_RESERVED_4_MAX (0x00000007U)
11903 
11904 #define CSL_DSS_VP3_DATA_CYCLE_0_BITALIGNMENTPIXEL1_MASK (0x00000F00U)
11905 #define CSL_DSS_VP3_DATA_CYCLE_0_BITALIGNMENTPIXEL1_SHIFT (0x00000008U)
11906 #define CSL_DSS_VP3_DATA_CYCLE_0_BITALIGNMENTPIXEL1_MAX (0x0000000FU)
11907 
11908 #define CSL_DSS_VP3_DATA_CYCLE_0_RESERVED_3_MASK (0x0000F000U)
11909 #define CSL_DSS_VP3_DATA_CYCLE_0_RESERVED_3_SHIFT (0x0000000CU)
11910 #define CSL_DSS_VP3_DATA_CYCLE_0_RESERVED_3_MAX (0x0000000FU)
11911 
11912 #define CSL_DSS_VP3_DATA_CYCLE_0_NBBITSPIXEL2_MASK (0x001F0000U)
11913 #define CSL_DSS_VP3_DATA_CYCLE_0_NBBITSPIXEL2_SHIFT (0x00000010U)
11914 #define CSL_DSS_VP3_DATA_CYCLE_0_NBBITSPIXEL2_MAX (0x0000001FU)
11915 
11916 #define CSL_DSS_VP3_DATA_CYCLE_0_RESERVED_6_MASK (0x00E00000U)
11917 #define CSL_DSS_VP3_DATA_CYCLE_0_RESERVED_6_SHIFT (0x00000015U)
11918 #define CSL_DSS_VP3_DATA_CYCLE_0_RESERVED_6_MAX (0x00000007U)
11919 
11920 #define CSL_DSS_VP3_DATA_CYCLE_0_BITALIGNMENTPIXEL2_MASK (0x0F000000U)
11921 #define CSL_DSS_VP3_DATA_CYCLE_0_BITALIGNMENTPIXEL2_SHIFT (0x00000018U)
11922 #define CSL_DSS_VP3_DATA_CYCLE_0_BITALIGNMENTPIXEL2_MAX (0x0000000FU)
11923 
11924 #define CSL_DSS_VP3_DATA_CYCLE_0_RESERVED_5_MASK (0xF0000000U)
11925 #define CSL_DSS_VP3_DATA_CYCLE_0_RESERVED_5_SHIFT (0x0000001CU)
11926 #define CSL_DSS_VP3_DATA_CYCLE_0_RESERVED_5_MAX (0x0000000FU)
11927 
11928 /* DATA_CYCLE_1 */
11929 
11930 #define CSL_DSS_VP3_DATA_CYCLE_1_NBBITSPIXEL1_MASK (0x0000001FU)
11931 #define CSL_DSS_VP3_DATA_CYCLE_1_NBBITSPIXEL1_SHIFT (0x00000000U)
11932 #define CSL_DSS_VP3_DATA_CYCLE_1_NBBITSPIXEL1_MAX (0x0000001FU)
11933 
11934 #define CSL_DSS_VP3_DATA_CYCLE_1_RESERVED_4_MASK (0x000000E0U)
11935 #define CSL_DSS_VP3_DATA_CYCLE_1_RESERVED_4_SHIFT (0x00000005U)
11936 #define CSL_DSS_VP3_DATA_CYCLE_1_RESERVED_4_MAX (0x00000007U)
11937 
11938 #define CSL_DSS_VP3_DATA_CYCLE_1_BITALIGNMENTPIXEL1_MASK (0x00000F00U)
11939 #define CSL_DSS_VP3_DATA_CYCLE_1_BITALIGNMENTPIXEL1_SHIFT (0x00000008U)
11940 #define CSL_DSS_VP3_DATA_CYCLE_1_BITALIGNMENTPIXEL1_MAX (0x0000000FU)
11941 
11942 #define CSL_DSS_VP3_DATA_CYCLE_1_RESERVED_3_MASK (0x0000F000U)
11943 #define CSL_DSS_VP3_DATA_CYCLE_1_RESERVED_3_SHIFT (0x0000000CU)
11944 #define CSL_DSS_VP3_DATA_CYCLE_1_RESERVED_3_MAX (0x0000000FU)
11945 
11946 #define CSL_DSS_VP3_DATA_CYCLE_1_NBBITSPIXEL2_MASK (0x001F0000U)
11947 #define CSL_DSS_VP3_DATA_CYCLE_1_NBBITSPIXEL2_SHIFT (0x00000010U)
11948 #define CSL_DSS_VP3_DATA_CYCLE_1_NBBITSPIXEL2_MAX (0x0000001FU)
11949 
11950 #define CSL_DSS_VP3_DATA_CYCLE_1_RESERVED_6_MASK (0x00E00000U)
11951 #define CSL_DSS_VP3_DATA_CYCLE_1_RESERVED_6_SHIFT (0x00000015U)
11952 #define CSL_DSS_VP3_DATA_CYCLE_1_RESERVED_6_MAX (0x00000007U)
11953 
11954 #define CSL_DSS_VP3_DATA_CYCLE_1_BITALIGNMENTPIXEL2_MASK (0x0F000000U)
11955 #define CSL_DSS_VP3_DATA_CYCLE_1_BITALIGNMENTPIXEL2_SHIFT (0x00000018U)
11956 #define CSL_DSS_VP3_DATA_CYCLE_1_BITALIGNMENTPIXEL2_MAX (0x0000000FU)
11957 
11958 #define CSL_DSS_VP3_DATA_CYCLE_1_RESERVED_5_MASK (0xF0000000U)
11959 #define CSL_DSS_VP3_DATA_CYCLE_1_RESERVED_5_SHIFT (0x0000001CU)
11960 #define CSL_DSS_VP3_DATA_CYCLE_1_RESERVED_5_MAX (0x0000000FU)
11961 
11962 /* DATA_CYCLE_2 */
11963 
11964 #define CSL_DSS_VP3_DATA_CYCLE_2_NBBITSPIXEL1_MASK (0x0000001FU)
11965 #define CSL_DSS_VP3_DATA_CYCLE_2_NBBITSPIXEL1_SHIFT (0x00000000U)
11966 #define CSL_DSS_VP3_DATA_CYCLE_2_NBBITSPIXEL1_MAX (0x0000001FU)
11967 
11968 #define CSL_DSS_VP3_DATA_CYCLE_2_RESERVED_4_MASK (0x000000E0U)
11969 #define CSL_DSS_VP3_DATA_CYCLE_2_RESERVED_4_SHIFT (0x00000005U)
11970 #define CSL_DSS_VP3_DATA_CYCLE_2_RESERVED_4_MAX (0x00000007U)
11971 
11972 #define CSL_DSS_VP3_DATA_CYCLE_2_BITALIGNMENTPIXEL1_MASK (0x00000F00U)
11973 #define CSL_DSS_VP3_DATA_CYCLE_2_BITALIGNMENTPIXEL1_SHIFT (0x00000008U)
11974 #define CSL_DSS_VP3_DATA_CYCLE_2_BITALIGNMENTPIXEL1_MAX (0x0000000FU)
11975 
11976 #define CSL_DSS_VP3_DATA_CYCLE_2_RESERVED_3_MASK (0x0000F000U)
11977 #define CSL_DSS_VP3_DATA_CYCLE_2_RESERVED_3_SHIFT (0x0000000CU)
11978 #define CSL_DSS_VP3_DATA_CYCLE_2_RESERVED_3_MAX (0x0000000FU)
11979 
11980 #define CSL_DSS_VP3_DATA_CYCLE_2_NBBITSPIXEL2_MASK (0x001F0000U)
11981 #define CSL_DSS_VP3_DATA_CYCLE_2_NBBITSPIXEL2_SHIFT (0x00000010U)
11982 #define CSL_DSS_VP3_DATA_CYCLE_2_NBBITSPIXEL2_MAX (0x0000001FU)
11983 
11984 #define CSL_DSS_VP3_DATA_CYCLE_2_RESERVED_6_MASK (0x00E00000U)
11985 #define CSL_DSS_VP3_DATA_CYCLE_2_RESERVED_6_SHIFT (0x00000015U)
11986 #define CSL_DSS_VP3_DATA_CYCLE_2_RESERVED_6_MAX (0x00000007U)
11987 
11988 #define CSL_DSS_VP3_DATA_CYCLE_2_BITALIGNMENTPIXEL2_MASK (0x0F000000U)
11989 #define CSL_DSS_VP3_DATA_CYCLE_2_BITALIGNMENTPIXEL2_SHIFT (0x00000018U)
11990 #define CSL_DSS_VP3_DATA_CYCLE_2_BITALIGNMENTPIXEL2_MAX (0x0000000FU)
11991 
11992 #define CSL_DSS_VP3_DATA_CYCLE_2_RESERVED_5_MASK (0xF0000000U)
11993 #define CSL_DSS_VP3_DATA_CYCLE_2_RESERVED_5_SHIFT (0x0000001CU)
11994 #define CSL_DSS_VP3_DATA_CYCLE_2_RESERVED_5_MAX (0x0000000FU)
11995 
11996 /* LINE_NUMBER */
11997 
11998 #define CSL_DSS_VP3_LINE_NUMBER_LINENUMBER_MASK (0x00003FFFU)
11999 #define CSL_DSS_VP3_LINE_NUMBER_LINENUMBER_SHIFT (0x00000000U)
12000 #define CSL_DSS_VP3_LINE_NUMBER_LINENUMBER_MAX (0x00003FFFU)
12001 
12002 #define CSL_DSS_VP3_LINE_NUMBER_RESERVED_MASK (0xFFFFC000U)
12003 #define CSL_DSS_VP3_LINE_NUMBER_RESERVED_SHIFT (0x0000000EU)
12004 #define CSL_DSS_VP3_LINE_NUMBER_RESERVED_MAX (0x0003FFFFU)
12005 
12006 /* POL_FREQ */
12007 
12008 #define CSL_DSS_VP3_POL_FREQ_ACB_MASK (0x000000FFU)
12009 #define CSL_DSS_VP3_POL_FREQ_ACB_SHIFT (0x00000000U)
12010 #define CSL_DSS_VP3_POL_FREQ_ACB_MAX (0x000000FFU)
12011 
12012 #define CSL_DSS_VP3_POL_FREQ_ACBI_MASK (0x00000F00U)
12013 #define CSL_DSS_VP3_POL_FREQ_ACBI_SHIFT (0x00000008U)
12014 #define CSL_DSS_VP3_POL_FREQ_ACBI_MAX (0x0000000FU)
12015 
12016 #define CSL_DSS_VP3_POL_FREQ_IVS_MASK (0x00001000U)
12017 #define CSL_DSS_VP3_POL_FREQ_IVS_SHIFT (0x0000000CU)
12018 #define CSL_DSS_VP3_POL_FREQ_IVS_MAX (0x00000001U)
12019 
12020 #define CSL_DSS_VP3_POL_FREQ_IVS_VAL_FCKPINAH (0x0U)
12021 #define CSL_DSS_VP3_POL_FREQ_IVS_VAL_FCKPINAL (0x1U)
12022 
12023 #define CSL_DSS_VP3_POL_FREQ_IHS_MASK (0x00002000U)
12024 #define CSL_DSS_VP3_POL_FREQ_IHS_SHIFT (0x0000000DU)
12025 #define CSL_DSS_VP3_POL_FREQ_IHS_MAX (0x00000001U)
12026 
12027 #define CSL_DSS_VP3_POL_FREQ_IHS_VAL_LCKPINAH (0x0U)
12028 #define CSL_DSS_VP3_POL_FREQ_IHS_VAL_LCKPINAL (0x1U)
12029 
12030 #define CSL_DSS_VP3_POL_FREQ_IPC_MASK (0x00004000U)
12031 #define CSL_DSS_VP3_POL_FREQ_IPC_SHIFT (0x0000000EU)
12032 #define CSL_DSS_VP3_POL_FREQ_IPC_MAX (0x00000001U)
12033 
12034 #define CSL_DSS_VP3_POL_FREQ_IPC_VAL_DRPCK (0x0U)
12035 #define CSL_DSS_VP3_POL_FREQ_IPC_VAL_DFPCK (0x1U)
12036 
12037 #define CSL_DSS_VP3_POL_FREQ_IEO_MASK (0x00008000U)
12038 #define CSL_DSS_VP3_POL_FREQ_IEO_SHIFT (0x0000000FU)
12039 #define CSL_DSS_VP3_POL_FREQ_IEO_MAX (0x00000001U)
12040 
12041 #define CSL_DSS_VP3_POL_FREQ_IEO_VAL_ACBAHIGH (0x0U)
12042 #define CSL_DSS_VP3_POL_FREQ_IEO_VAL_ACBALOW (0x1U)
12043 
12044 #define CSL_DSS_VP3_POL_FREQ_RF_MASK (0x00010000U)
12045 #define CSL_DSS_VP3_POL_FREQ_RF_SHIFT (0x00000010U)
12046 #define CSL_DSS_VP3_POL_FREQ_RF_MAX (0x00000001U)
12047 
12048 #define CSL_DSS_VP3_POL_FREQ_RF_VAL_DFEDPCK (0x0U)
12049 #define CSL_DSS_VP3_POL_FREQ_RF_VAL_DRIEDPCK (0x1U)
12050 
12051 #define CSL_DSS_VP3_POL_FREQ_ONOFF_MASK (0x00020000U)
12052 #define CSL_DSS_VP3_POL_FREQ_ONOFF_SHIFT (0x00000011U)
12053 #define CSL_DSS_VP3_POL_FREQ_ONOFF_MAX (0x00000001U)
12054 
12055 #define CSL_DSS_VP3_POL_FREQ_ONOFF_VAL_DOPEDPCK (0x0U)
12056 #define CSL_DSS_VP3_POL_FREQ_ONOFF_VAL_DBIT16 (0x1U)
12057 
12058 #define CSL_DSS_VP3_POL_FREQ_ALIGN_MASK (0x00040000U)
12059 #define CSL_DSS_VP3_POL_FREQ_ALIGN_SHIFT (0x00000012U)
12060 #define CSL_DSS_VP3_POL_FREQ_ALIGN_MAX (0x00000001U)
12061 
12062 #define CSL_DSS_VP3_POL_FREQ_ALIGN_VAL_NOTALIGNED (0x0U)
12063 #define CSL_DSS_VP3_POL_FREQ_ALIGN_VAL_ALIGNED (0x1U)
12064 
12065 #define CSL_DSS_VP3_POL_FREQ_RESERVED_MASK (0xFFF80000U)
12066 #define CSL_DSS_VP3_POL_FREQ_RESERVED_SHIFT (0x00000013U)
12067 #define CSL_DSS_VP3_POL_FREQ_RESERVED_MAX (0x00001FFFU)
12068 
12069 /* SIZE_SCREEN */
12070 
12071 #define CSL_DSS_VP3_SIZE_SCREEN_PPL_MASK (0x00003FFFU)
12072 #define CSL_DSS_VP3_SIZE_SCREEN_PPL_SHIFT (0x00000000U)
12073 #define CSL_DSS_VP3_SIZE_SCREEN_PPL_MAX (0x00003FFFU)
12074 
12075 #define CSL_DSS_VP3_SIZE_SCREEN_DELTA_LPP_MASK (0x0000C000U)
12076 #define CSL_DSS_VP3_SIZE_SCREEN_DELTA_LPP_SHIFT (0x0000000EU)
12077 #define CSL_DSS_VP3_SIZE_SCREEN_DELTA_LPP_MAX (0x00000003U)
12078 
12079 #define CSL_DSS_VP3_SIZE_SCREEN_DELTA_LPP_VAL_SAME (0x0U)
12080 #define CSL_DSS_VP3_SIZE_SCREEN_DELTA_LPP_VAL_PLUSONE (0x1U)
12081 #define CSL_DSS_VP3_SIZE_SCREEN_DELTA_LPP_VAL_MINUSONE (0x2U)
12082 
12083 #define CSL_DSS_VP3_SIZE_SCREEN_LPP_MASK (0x3FFF0000U)
12084 #define CSL_DSS_VP3_SIZE_SCREEN_LPP_SHIFT (0x00000010U)
12085 #define CSL_DSS_VP3_SIZE_SCREEN_LPP_MAX (0x00003FFFU)
12086 
12087 /* TIMING_H */
12088 
12089 #define CSL_DSS_VP3_TIMING_H_HSW_MASK (0x000000FFU)
12090 #define CSL_DSS_VP3_TIMING_H_HSW_SHIFT (0x00000000U)
12091 #define CSL_DSS_VP3_TIMING_H_HSW_MAX (0x000000FFU)
12092 
12093 #define CSL_DSS_VP3_TIMING_H_HFP_MASK (0x000FFF00U)
12094 #define CSL_DSS_VP3_TIMING_H_HFP_SHIFT (0x00000008U)
12095 #define CSL_DSS_VP3_TIMING_H_HFP_MAX (0x00000FFFU)
12096 
12097 #define CSL_DSS_VP3_TIMING_H_HBP_MASK (0xFFF00000U)
12098 #define CSL_DSS_VP3_TIMING_H_HBP_SHIFT (0x00000014U)
12099 #define CSL_DSS_VP3_TIMING_H_HBP_MAX (0x00000FFFU)
12100 
12101 /* TIMING_V */
12102 
12103 #define CSL_DSS_VP3_TIMING_V_VSW_MASK (0x000000FFU)
12104 #define CSL_DSS_VP3_TIMING_V_VSW_SHIFT (0x00000000U)
12105 #define CSL_DSS_VP3_TIMING_V_VSW_MAX (0x000000FFU)
12106 
12107 #define CSL_DSS_VP3_TIMING_V_VFP_MASK (0x000FFF00U)
12108 #define CSL_DSS_VP3_TIMING_V_VFP_SHIFT (0x00000008U)
12109 #define CSL_DSS_VP3_TIMING_V_VFP_MAX (0x00000FFFU)
12110 
12111 #define CSL_DSS_VP3_TIMING_V_VBP_MASK (0xFFF00000U)
12112 #define CSL_DSS_VP3_TIMING_V_VBP_SHIFT (0x00000014U)
12113 #define CSL_DSS_VP3_TIMING_V_VBP_MAX (0x00000FFFU)
12114 
12115 /* CSC_COEF3 */
12116 
12117 #define CSL_DSS_VP3_CSC_COEF3_C20_MASK (0x000007FFU)
12118 #define CSL_DSS_VP3_CSC_COEF3_C20_SHIFT (0x00000000U)
12119 #define CSL_DSS_VP3_CSC_COEF3_C20_MAX (0x000007FFU)
12120 
12121 #define CSL_DSS_VP3_CSC_COEF3_RESERVED_59_MASK (0x0000F800U)
12122 #define CSL_DSS_VP3_CSC_COEF3_RESERVED_59_SHIFT (0x0000000BU)
12123 #define CSL_DSS_VP3_CSC_COEF3_RESERVED_59_MAX (0x0000001FU)
12124 
12125 #define CSL_DSS_VP3_CSC_COEF3_C21_MASK (0x07FF0000U)
12126 #define CSL_DSS_VP3_CSC_COEF3_C21_SHIFT (0x00000010U)
12127 #define CSL_DSS_VP3_CSC_COEF3_C21_MAX (0x000007FFU)
12128 
12129 #define CSL_DSS_VP3_CSC_COEF3_RESERVED_58_MASK (0xF8000000U)
12130 #define CSL_DSS_VP3_CSC_COEF3_RESERVED_58_SHIFT (0x0000001BU)
12131 #define CSL_DSS_VP3_CSC_COEF3_RESERVED_58_MAX (0x0000001FU)
12132 
12133 /* CSC_COEF4 */
12134 
12135 #define CSL_DSS_VP3_CSC_COEF4_C22_MASK (0x000007FFU)
12136 #define CSL_DSS_VP3_CSC_COEF4_C22_SHIFT (0x00000000U)
12137 #define CSL_DSS_VP3_CSC_COEF4_C22_MAX (0x000007FFU)
12138 
12139 #define CSL_DSS_VP3_CSC_COEF4_RESERVED_60_MASK (0xFFFFF800U)
12140 #define CSL_DSS_VP3_CSC_COEF4_RESERVED_60_SHIFT (0x0000000BU)
12141 #define CSL_DSS_VP3_CSC_COEF4_RESERVED_60_MAX (0x001FFFFFU)
12142 
12143 /* CSC_COEF5 */
12144 
12145 #define CSL_DSS_VP3_CSC_COEF5_RESERVED_MASK (0x00000007U)
12146 #define CSL_DSS_VP3_CSC_COEF5_RESERVED_SHIFT (0x00000000U)
12147 #define CSL_DSS_VP3_CSC_COEF5_RESERVED_MAX (0x00000007U)
12148 
12149 #define CSL_DSS_VP3_CSC_COEF5_PREOFFSET1_MASK (0x0000FFF8U)
12150 #define CSL_DSS_VP3_CSC_COEF5_PREOFFSET1_SHIFT (0x00000003U)
12151 #define CSL_DSS_VP3_CSC_COEF5_PREOFFSET1_MAX (0x00001FFFU)
12152 
12153 #define CSL_DSS_VP3_CSC_COEF5_RESERVED1_MASK (0x00070000U)
12154 #define CSL_DSS_VP3_CSC_COEF5_RESERVED1_SHIFT (0x00000010U)
12155 #define CSL_DSS_VP3_CSC_COEF5_RESERVED1_MAX (0x00000007U)
12156 
12157 #define CSL_DSS_VP3_CSC_COEF5_PREOFFSET2_MASK (0xFFF80000U)
12158 #define CSL_DSS_VP3_CSC_COEF5_PREOFFSET2_SHIFT (0x00000013U)
12159 #define CSL_DSS_VP3_CSC_COEF5_PREOFFSET2_MAX (0x00001FFFU)
12160 
12161 /* CSC_COEF6 */
12162 
12163 #define CSL_DSS_VP3_CSC_COEF6_RESERVED_MASK (0x00000007U)
12164 #define CSL_DSS_VP3_CSC_COEF6_RESERVED_SHIFT (0x00000000U)
12165 #define CSL_DSS_VP3_CSC_COEF6_RESERVED_MAX (0x00000007U)
12166 
12167 #define CSL_DSS_VP3_CSC_COEF6_PREOFFSET3_MASK (0x0000FFF8U)
12168 #define CSL_DSS_VP3_CSC_COEF6_PREOFFSET3_SHIFT (0x00000003U)
12169 #define CSL_DSS_VP3_CSC_COEF6_PREOFFSET3_MAX (0x00001FFFU)
12170 
12171 #define CSL_DSS_VP3_CSC_COEF6_RESERVED1_MASK (0x00070000U)
12172 #define CSL_DSS_VP3_CSC_COEF6_RESERVED1_SHIFT (0x00000010U)
12173 #define CSL_DSS_VP3_CSC_COEF6_RESERVED1_MAX (0x00000007U)
12174 
12175 #define CSL_DSS_VP3_CSC_COEF6_POSTOFFSET1_MASK (0xFFF80000U)
12176 #define CSL_DSS_VP3_CSC_COEF6_POSTOFFSET1_SHIFT (0x00000013U)
12177 #define CSL_DSS_VP3_CSC_COEF6_POSTOFFSET1_MAX (0x00001FFFU)
12178 
12179 /* CSC_COEF7 */
12180 
12181 #define CSL_DSS_VP3_CSC_COEF7_RESERVED_MASK (0x00000007U)
12182 #define CSL_DSS_VP3_CSC_COEF7_RESERVED_SHIFT (0x00000000U)
12183 #define CSL_DSS_VP3_CSC_COEF7_RESERVED_MAX (0x00000007U)
12184 
12185 #define CSL_DSS_VP3_CSC_COEF7_POSTOFFSET2_MASK (0x0000FFF8U)
12186 #define CSL_DSS_VP3_CSC_COEF7_POSTOFFSET2_SHIFT (0x00000003U)
12187 #define CSL_DSS_VP3_CSC_COEF7_POSTOFFSET2_MAX (0x00001FFFU)
12188 
12189 #define CSL_DSS_VP3_CSC_COEF7_RESERVED1_MASK (0x00070000U)
12190 #define CSL_DSS_VP3_CSC_COEF7_RESERVED1_SHIFT (0x00000010U)
12191 #define CSL_DSS_VP3_CSC_COEF7_RESERVED1_MAX (0x00000007U)
12192 
12193 #define CSL_DSS_VP3_CSC_COEF7_POSTOFFSET3_MASK (0xFFF80000U)
12194 #define CSL_DSS_VP3_CSC_COEF7_POSTOFFSET3_SHIFT (0x00000013U)
12195 #define CSL_DSS_VP3_CSC_COEF7_POSTOFFSET3_MAX (0x00001FFFU)
12196 
12197 /* SAFETY_ATTRIBUTES */
12198 
12199 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_ENABLE_MASK (0x00000001U)
12200 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
12201 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_ENABLE_MAX (0x00000001U)
12202 
12203 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_CAPTUREMODE_MASK (0x00000002U)
12204 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_CAPTUREMODE_SHIFT (0x00000001U)
12205 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_CAPTUREMODE_MAX (0x00000001U)
12206 
12207 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_FRAMEFREEZE (0x0U)
12208 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_DATACHECK (0x1U)
12209 
12210 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_SEEDSELECT_MASK (0x00000004U)
12211 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_SEEDSELECT_SHIFT (0x00000002U)
12212 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_SEEDSELECT_MAX (0x00000001U)
12213 
12214 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_DISABLE (0x0U)
12215 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_ENABLE (0x1U)
12216 
12217 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_THRESHOLD_MASK (0x000007F8U)
12218 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_THRESHOLD_SHIFT (0x00000003U)
12219 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_THRESHOLD_MAX (0x000000FFU)
12220 
12221 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_FRAMESKIP_MASK (0x00001800U)
12222 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_FRAMESKIP_SHIFT (0x0000000BU)
12223 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_FRAMESKIP_MAX (0x00000003U)
12224 
12225 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_NOSKIP (0x0U)
12226 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_EVEN (0x1U)
12227 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_ODD (0x2U)
12228 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_RESERVED (0x3U)
12229 
12230 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_RESERVED_MASK (0xFFFFE000U)
12231 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_RESERVED_SHIFT (0x0000000DU)
12232 #define CSL_DSS_VP3_SAFETY_ATTRIBUTES_RESERVED_MAX (0x0007FFFFU)
12233 
12234 /* SAFETY_CAPT_SIGNATURE */
12235 
12236 #define CSL_DSS_VP3_SAFETY_CAPT_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
12237 #define CSL_DSS_VP3_SAFETY_CAPT_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
12238 #define CSL_DSS_VP3_SAFETY_CAPT_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
12239 
12240 /* SAFETY_POSITION */
12241 
12242 #define CSL_DSS_VP3_SAFETY_POSITION_POSX_MASK (0x00003FFFU)
12243 #define CSL_DSS_VP3_SAFETY_POSITION_POSX_SHIFT (0x00000000U)
12244 #define CSL_DSS_VP3_SAFETY_POSITION_POSX_MAX (0x00003FFFU)
12245 
12246 #define CSL_DSS_VP3_SAFETY_POSITION_POSY_MASK (0x3FFF0000U)
12247 #define CSL_DSS_VP3_SAFETY_POSITION_POSY_SHIFT (0x00000010U)
12248 #define CSL_DSS_VP3_SAFETY_POSITION_POSY_MAX (0x00003FFFU)
12249 
12250 /* SAFETY_REF_SIGNATURE */
12251 
12252 #define CSL_DSS_VP3_SAFETY_REF_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
12253 #define CSL_DSS_VP3_SAFETY_REF_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
12254 #define CSL_DSS_VP3_SAFETY_REF_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
12255 
12256 /* SAFETY_SIZE */
12257 
12258 #define CSL_DSS_VP3_SAFETY_SIZE_SIZEX_MASK (0x00003FFFU)
12259 #define CSL_DSS_VP3_SAFETY_SIZE_SIZEX_SHIFT (0x00000000U)
12260 #define CSL_DSS_VP3_SAFETY_SIZE_SIZEX_MAX (0x00003FFFU)
12261 
12262 #define CSL_DSS_VP3_SAFETY_SIZE_SIZEY_MASK (0x3FFF0000U)
12263 #define CSL_DSS_VP3_SAFETY_SIZE_SIZEY_SHIFT (0x00000010U)
12264 #define CSL_DSS_VP3_SAFETY_SIZE_SIZEY_MAX (0x00003FFFU)
12265 
12266 /* SAFETY_LFSR_SEED */
12267 
12268 #define CSL_DSS_VP3_SAFETY_LFSR_SEED_SEED_MASK (0xFFFFFFFFU)
12269 #define CSL_DSS_VP3_SAFETY_LFSR_SEED_SEED_SHIFT (0x00000000U)
12270 #define CSL_DSS_VP3_SAFETY_LFSR_SEED_SEED_MAX (0xFFFFFFFFU)
12271 
12272 /* GAMMA_TABLE_0 */
12273 
12274 #define CSL_DSS_VP3_GAMMA_TABLE_0_VALUE_B_MASK (0x000003FFU)
12275 #define CSL_DSS_VP3_GAMMA_TABLE_0_VALUE_B_SHIFT (0x00000000U)
12276 #define CSL_DSS_VP3_GAMMA_TABLE_0_VALUE_B_MAX (0x000003FFU)
12277 
12278 #define CSL_DSS_VP3_GAMMA_TABLE_0_VALUE_G_MASK (0x000FFC00U)
12279 #define CSL_DSS_VP3_GAMMA_TABLE_0_VALUE_G_SHIFT (0x0000000AU)
12280 #define CSL_DSS_VP3_GAMMA_TABLE_0_VALUE_G_MAX (0x000003FFU)
12281 
12282 #define CSL_DSS_VP3_GAMMA_TABLE_0_VALUE_R_MASK (0x3FF00000U)
12283 #define CSL_DSS_VP3_GAMMA_TABLE_0_VALUE_R_SHIFT (0x00000014U)
12284 #define CSL_DSS_VP3_GAMMA_TABLE_0_VALUE_R_MAX (0x000003FFU)
12285 
12286 #define CSL_DSS_VP3_GAMMA_TABLE_0_INDEX_MASK (0x80000000U)
12287 #define CSL_DSS_VP3_GAMMA_TABLE_0_INDEX_SHIFT (0x0000001FU)
12288 #define CSL_DSS_VP3_GAMMA_TABLE_0_INDEX_MAX (0x00000001U)
12289 
12290 /* GAMMA_TABLE_1 */
12291 
12292 #define CSL_DSS_VP3_GAMMA_TABLE_1_VALUE_B_MASK (0x000003FFU)
12293 #define CSL_DSS_VP3_GAMMA_TABLE_1_VALUE_B_SHIFT (0x00000000U)
12294 #define CSL_DSS_VP3_GAMMA_TABLE_1_VALUE_B_MAX (0x000003FFU)
12295 
12296 #define CSL_DSS_VP3_GAMMA_TABLE_1_VALUE_G_MASK (0x000FFC00U)
12297 #define CSL_DSS_VP3_GAMMA_TABLE_1_VALUE_G_SHIFT (0x0000000AU)
12298 #define CSL_DSS_VP3_GAMMA_TABLE_1_VALUE_G_MAX (0x000003FFU)
12299 
12300 #define CSL_DSS_VP3_GAMMA_TABLE_1_VALUE_R_MASK (0x3FF00000U)
12301 #define CSL_DSS_VP3_GAMMA_TABLE_1_VALUE_R_SHIFT (0x00000014U)
12302 #define CSL_DSS_VP3_GAMMA_TABLE_1_VALUE_R_MAX (0x000003FFU)
12303 
12304 #define CSL_DSS_VP3_GAMMA_TABLE_1_INDEX_MASK (0x80000000U)
12305 #define CSL_DSS_VP3_GAMMA_TABLE_1_INDEX_SHIFT (0x0000001FU)
12306 #define CSL_DSS_VP3_GAMMA_TABLE_1_INDEX_MAX (0x00000001U)
12307 
12308 /* GAMMA_TABLE_2 */
12309 
12310 #define CSL_DSS_VP3_GAMMA_TABLE_2_VALUE_B_MASK (0x000003FFU)
12311 #define CSL_DSS_VP3_GAMMA_TABLE_2_VALUE_B_SHIFT (0x00000000U)
12312 #define CSL_DSS_VP3_GAMMA_TABLE_2_VALUE_B_MAX (0x000003FFU)
12313 
12314 #define CSL_DSS_VP3_GAMMA_TABLE_2_VALUE_G_MASK (0x000FFC00U)
12315 #define CSL_DSS_VP3_GAMMA_TABLE_2_VALUE_G_SHIFT (0x0000000AU)
12316 #define CSL_DSS_VP3_GAMMA_TABLE_2_VALUE_G_MAX (0x000003FFU)
12317 
12318 #define CSL_DSS_VP3_GAMMA_TABLE_2_VALUE_R_MASK (0x3FF00000U)
12319 #define CSL_DSS_VP3_GAMMA_TABLE_2_VALUE_R_SHIFT (0x00000014U)
12320 #define CSL_DSS_VP3_GAMMA_TABLE_2_VALUE_R_MAX (0x000003FFU)
12321 
12322 #define CSL_DSS_VP3_GAMMA_TABLE_2_INDEX_MASK (0x80000000U)
12323 #define CSL_DSS_VP3_GAMMA_TABLE_2_INDEX_SHIFT (0x0000001FU)
12324 #define CSL_DSS_VP3_GAMMA_TABLE_2_INDEX_MAX (0x00000001U)
12325 
12326 /* GAMMA_TABLE_3 */
12327 
12328 #define CSL_DSS_VP3_GAMMA_TABLE_3_VALUE_B_MASK (0x000003FFU)
12329 #define CSL_DSS_VP3_GAMMA_TABLE_3_VALUE_B_SHIFT (0x00000000U)
12330 #define CSL_DSS_VP3_GAMMA_TABLE_3_VALUE_B_MAX (0x000003FFU)
12331 
12332 #define CSL_DSS_VP3_GAMMA_TABLE_3_VALUE_G_MASK (0x000FFC00U)
12333 #define CSL_DSS_VP3_GAMMA_TABLE_3_VALUE_G_SHIFT (0x0000000AU)
12334 #define CSL_DSS_VP3_GAMMA_TABLE_3_VALUE_G_MAX (0x000003FFU)
12335 
12336 #define CSL_DSS_VP3_GAMMA_TABLE_3_VALUE_R_MASK (0x3FF00000U)
12337 #define CSL_DSS_VP3_GAMMA_TABLE_3_VALUE_R_SHIFT (0x00000014U)
12338 #define CSL_DSS_VP3_GAMMA_TABLE_3_VALUE_R_MAX (0x000003FFU)
12339 
12340 #define CSL_DSS_VP3_GAMMA_TABLE_3_INDEX_MASK (0x80000000U)
12341 #define CSL_DSS_VP3_GAMMA_TABLE_3_INDEX_SHIFT (0x0000001FU)
12342 #define CSL_DSS_VP3_GAMMA_TABLE_3_INDEX_MAX (0x00000001U)
12343 
12344 /* GAMMA_TABLE_4 */
12345 
12346 #define CSL_DSS_VP3_GAMMA_TABLE_4_VALUE_B_MASK (0x000003FFU)
12347 #define CSL_DSS_VP3_GAMMA_TABLE_4_VALUE_B_SHIFT (0x00000000U)
12348 #define CSL_DSS_VP3_GAMMA_TABLE_4_VALUE_B_MAX (0x000003FFU)
12349 
12350 #define CSL_DSS_VP3_GAMMA_TABLE_4_VALUE_G_MASK (0x000FFC00U)
12351 #define CSL_DSS_VP3_GAMMA_TABLE_4_VALUE_G_SHIFT (0x0000000AU)
12352 #define CSL_DSS_VP3_GAMMA_TABLE_4_VALUE_G_MAX (0x000003FFU)
12353 
12354 #define CSL_DSS_VP3_GAMMA_TABLE_4_VALUE_R_MASK (0x3FF00000U)
12355 #define CSL_DSS_VP3_GAMMA_TABLE_4_VALUE_R_SHIFT (0x00000014U)
12356 #define CSL_DSS_VP3_GAMMA_TABLE_4_VALUE_R_MAX (0x000003FFU)
12357 
12358 #define CSL_DSS_VP3_GAMMA_TABLE_4_INDEX_MASK (0x80000000U)
12359 #define CSL_DSS_VP3_GAMMA_TABLE_4_INDEX_SHIFT (0x0000001FU)
12360 #define CSL_DSS_VP3_GAMMA_TABLE_4_INDEX_MAX (0x00000001U)
12361 
12362 /* GAMMA_TABLE_5 */
12363 
12364 #define CSL_DSS_VP3_GAMMA_TABLE_5_VALUE_B_MASK (0x000003FFU)
12365 #define CSL_DSS_VP3_GAMMA_TABLE_5_VALUE_B_SHIFT (0x00000000U)
12366 #define CSL_DSS_VP3_GAMMA_TABLE_5_VALUE_B_MAX (0x000003FFU)
12367 
12368 #define CSL_DSS_VP3_GAMMA_TABLE_5_VALUE_G_MASK (0x000FFC00U)
12369 #define CSL_DSS_VP3_GAMMA_TABLE_5_VALUE_G_SHIFT (0x0000000AU)
12370 #define CSL_DSS_VP3_GAMMA_TABLE_5_VALUE_G_MAX (0x000003FFU)
12371 
12372 #define CSL_DSS_VP3_GAMMA_TABLE_5_VALUE_R_MASK (0x3FF00000U)
12373 #define CSL_DSS_VP3_GAMMA_TABLE_5_VALUE_R_SHIFT (0x00000014U)
12374 #define CSL_DSS_VP3_GAMMA_TABLE_5_VALUE_R_MAX (0x000003FFU)
12375 
12376 #define CSL_DSS_VP3_GAMMA_TABLE_5_INDEX_MASK (0x80000000U)
12377 #define CSL_DSS_VP3_GAMMA_TABLE_5_INDEX_SHIFT (0x0000001FU)
12378 #define CSL_DSS_VP3_GAMMA_TABLE_5_INDEX_MAX (0x00000001U)
12379 
12380 /* GAMMA_TABLE_6 */
12381 
12382 #define CSL_DSS_VP3_GAMMA_TABLE_6_VALUE_B_MASK (0x000003FFU)
12383 #define CSL_DSS_VP3_GAMMA_TABLE_6_VALUE_B_SHIFT (0x00000000U)
12384 #define CSL_DSS_VP3_GAMMA_TABLE_6_VALUE_B_MAX (0x000003FFU)
12385 
12386 #define CSL_DSS_VP3_GAMMA_TABLE_6_VALUE_G_MASK (0x000FFC00U)
12387 #define CSL_DSS_VP3_GAMMA_TABLE_6_VALUE_G_SHIFT (0x0000000AU)
12388 #define CSL_DSS_VP3_GAMMA_TABLE_6_VALUE_G_MAX (0x000003FFU)
12389 
12390 #define CSL_DSS_VP3_GAMMA_TABLE_6_VALUE_R_MASK (0x3FF00000U)
12391 #define CSL_DSS_VP3_GAMMA_TABLE_6_VALUE_R_SHIFT (0x00000014U)
12392 #define CSL_DSS_VP3_GAMMA_TABLE_6_VALUE_R_MAX (0x000003FFU)
12393 
12394 #define CSL_DSS_VP3_GAMMA_TABLE_6_INDEX_MASK (0x80000000U)
12395 #define CSL_DSS_VP3_GAMMA_TABLE_6_INDEX_SHIFT (0x0000001FU)
12396 #define CSL_DSS_VP3_GAMMA_TABLE_6_INDEX_MAX (0x00000001U)
12397 
12398 /* GAMMA_TABLE_7 */
12399 
12400 #define CSL_DSS_VP3_GAMMA_TABLE_7_VALUE_B_MASK (0x000003FFU)
12401 #define CSL_DSS_VP3_GAMMA_TABLE_7_VALUE_B_SHIFT (0x00000000U)
12402 #define CSL_DSS_VP3_GAMMA_TABLE_7_VALUE_B_MAX (0x000003FFU)
12403 
12404 #define CSL_DSS_VP3_GAMMA_TABLE_7_VALUE_G_MASK (0x000FFC00U)
12405 #define CSL_DSS_VP3_GAMMA_TABLE_7_VALUE_G_SHIFT (0x0000000AU)
12406 #define CSL_DSS_VP3_GAMMA_TABLE_7_VALUE_G_MAX (0x000003FFU)
12407 
12408 #define CSL_DSS_VP3_GAMMA_TABLE_7_VALUE_R_MASK (0x3FF00000U)
12409 #define CSL_DSS_VP3_GAMMA_TABLE_7_VALUE_R_SHIFT (0x00000014U)
12410 #define CSL_DSS_VP3_GAMMA_TABLE_7_VALUE_R_MAX (0x000003FFU)
12411 
12412 #define CSL_DSS_VP3_GAMMA_TABLE_7_INDEX_MASK (0x80000000U)
12413 #define CSL_DSS_VP3_GAMMA_TABLE_7_INDEX_SHIFT (0x0000001FU)
12414 #define CSL_DSS_VP3_GAMMA_TABLE_7_INDEX_MAX (0x00000001U)
12415 
12416 /* GAMMA_TABLE_8 */
12417 
12418 #define CSL_DSS_VP3_GAMMA_TABLE_8_VALUE_B_MASK (0x000003FFU)
12419 #define CSL_DSS_VP3_GAMMA_TABLE_8_VALUE_B_SHIFT (0x00000000U)
12420 #define CSL_DSS_VP3_GAMMA_TABLE_8_VALUE_B_MAX (0x000003FFU)
12421 
12422 #define CSL_DSS_VP3_GAMMA_TABLE_8_VALUE_G_MASK (0x000FFC00U)
12423 #define CSL_DSS_VP3_GAMMA_TABLE_8_VALUE_G_SHIFT (0x0000000AU)
12424 #define CSL_DSS_VP3_GAMMA_TABLE_8_VALUE_G_MAX (0x000003FFU)
12425 
12426 #define CSL_DSS_VP3_GAMMA_TABLE_8_VALUE_R_MASK (0x3FF00000U)
12427 #define CSL_DSS_VP3_GAMMA_TABLE_8_VALUE_R_SHIFT (0x00000014U)
12428 #define CSL_DSS_VP3_GAMMA_TABLE_8_VALUE_R_MAX (0x000003FFU)
12429 
12430 #define CSL_DSS_VP3_GAMMA_TABLE_8_INDEX_MASK (0x80000000U)
12431 #define CSL_DSS_VP3_GAMMA_TABLE_8_INDEX_SHIFT (0x0000001FU)
12432 #define CSL_DSS_VP3_GAMMA_TABLE_8_INDEX_MAX (0x00000001U)
12433 
12434 /* GAMMA_TABLE_9 */
12435 
12436 #define CSL_DSS_VP3_GAMMA_TABLE_9_VALUE_B_MASK (0x000003FFU)
12437 #define CSL_DSS_VP3_GAMMA_TABLE_9_VALUE_B_SHIFT (0x00000000U)
12438 #define CSL_DSS_VP3_GAMMA_TABLE_9_VALUE_B_MAX (0x000003FFU)
12439 
12440 #define CSL_DSS_VP3_GAMMA_TABLE_9_VALUE_G_MASK (0x000FFC00U)
12441 #define CSL_DSS_VP3_GAMMA_TABLE_9_VALUE_G_SHIFT (0x0000000AU)
12442 #define CSL_DSS_VP3_GAMMA_TABLE_9_VALUE_G_MAX (0x000003FFU)
12443 
12444 #define CSL_DSS_VP3_GAMMA_TABLE_9_VALUE_R_MASK (0x3FF00000U)
12445 #define CSL_DSS_VP3_GAMMA_TABLE_9_VALUE_R_SHIFT (0x00000014U)
12446 #define CSL_DSS_VP3_GAMMA_TABLE_9_VALUE_R_MAX (0x000003FFU)
12447 
12448 #define CSL_DSS_VP3_GAMMA_TABLE_9_INDEX_MASK (0x80000000U)
12449 #define CSL_DSS_VP3_GAMMA_TABLE_9_INDEX_SHIFT (0x0000001FU)
12450 #define CSL_DSS_VP3_GAMMA_TABLE_9_INDEX_MAX (0x00000001U)
12451 
12452 /* GAMMA_TABLE_10 */
12453 
12454 #define CSL_DSS_VP3_GAMMA_TABLE_10_VALUE_B_MASK (0x000003FFU)
12455 #define CSL_DSS_VP3_GAMMA_TABLE_10_VALUE_B_SHIFT (0x00000000U)
12456 #define CSL_DSS_VP3_GAMMA_TABLE_10_VALUE_B_MAX (0x000003FFU)
12457 
12458 #define CSL_DSS_VP3_GAMMA_TABLE_10_VALUE_G_MASK (0x000FFC00U)
12459 #define CSL_DSS_VP3_GAMMA_TABLE_10_VALUE_G_SHIFT (0x0000000AU)
12460 #define CSL_DSS_VP3_GAMMA_TABLE_10_VALUE_G_MAX (0x000003FFU)
12461 
12462 #define CSL_DSS_VP3_GAMMA_TABLE_10_VALUE_R_MASK (0x3FF00000U)
12463 #define CSL_DSS_VP3_GAMMA_TABLE_10_VALUE_R_SHIFT (0x00000014U)
12464 #define CSL_DSS_VP3_GAMMA_TABLE_10_VALUE_R_MAX (0x000003FFU)
12465 
12466 #define CSL_DSS_VP3_GAMMA_TABLE_10_INDEX_MASK (0x80000000U)
12467 #define CSL_DSS_VP3_GAMMA_TABLE_10_INDEX_SHIFT (0x0000001FU)
12468 #define CSL_DSS_VP3_GAMMA_TABLE_10_INDEX_MAX (0x00000001U)
12469 
12470 /* GAMMA_TABLE_11 */
12471 
12472 #define CSL_DSS_VP3_GAMMA_TABLE_11_VALUE_B_MASK (0x000003FFU)
12473 #define CSL_DSS_VP3_GAMMA_TABLE_11_VALUE_B_SHIFT (0x00000000U)
12474 #define CSL_DSS_VP3_GAMMA_TABLE_11_VALUE_B_MAX (0x000003FFU)
12475 
12476 #define CSL_DSS_VP3_GAMMA_TABLE_11_VALUE_G_MASK (0x000FFC00U)
12477 #define CSL_DSS_VP3_GAMMA_TABLE_11_VALUE_G_SHIFT (0x0000000AU)
12478 #define CSL_DSS_VP3_GAMMA_TABLE_11_VALUE_G_MAX (0x000003FFU)
12479 
12480 #define CSL_DSS_VP3_GAMMA_TABLE_11_VALUE_R_MASK (0x3FF00000U)
12481 #define CSL_DSS_VP3_GAMMA_TABLE_11_VALUE_R_SHIFT (0x00000014U)
12482 #define CSL_DSS_VP3_GAMMA_TABLE_11_VALUE_R_MAX (0x000003FFU)
12483 
12484 #define CSL_DSS_VP3_GAMMA_TABLE_11_INDEX_MASK (0x80000000U)
12485 #define CSL_DSS_VP3_GAMMA_TABLE_11_INDEX_SHIFT (0x0000001FU)
12486 #define CSL_DSS_VP3_GAMMA_TABLE_11_INDEX_MAX (0x00000001U)
12487 
12488 /* GAMMA_TABLE_12 */
12489 
12490 #define CSL_DSS_VP3_GAMMA_TABLE_12_VALUE_B_MASK (0x000003FFU)
12491 #define CSL_DSS_VP3_GAMMA_TABLE_12_VALUE_B_SHIFT (0x00000000U)
12492 #define CSL_DSS_VP3_GAMMA_TABLE_12_VALUE_B_MAX (0x000003FFU)
12493 
12494 #define CSL_DSS_VP3_GAMMA_TABLE_12_VALUE_G_MASK (0x000FFC00U)
12495 #define CSL_DSS_VP3_GAMMA_TABLE_12_VALUE_G_SHIFT (0x0000000AU)
12496 #define CSL_DSS_VP3_GAMMA_TABLE_12_VALUE_G_MAX (0x000003FFU)
12497 
12498 #define CSL_DSS_VP3_GAMMA_TABLE_12_VALUE_R_MASK (0x3FF00000U)
12499 #define CSL_DSS_VP3_GAMMA_TABLE_12_VALUE_R_SHIFT (0x00000014U)
12500 #define CSL_DSS_VP3_GAMMA_TABLE_12_VALUE_R_MAX (0x000003FFU)
12501 
12502 #define CSL_DSS_VP3_GAMMA_TABLE_12_INDEX_MASK (0x80000000U)
12503 #define CSL_DSS_VP3_GAMMA_TABLE_12_INDEX_SHIFT (0x0000001FU)
12504 #define CSL_DSS_VP3_GAMMA_TABLE_12_INDEX_MAX (0x00000001U)
12505 
12506 /* GAMMA_TABLE_13 */
12507 
12508 #define CSL_DSS_VP3_GAMMA_TABLE_13_VALUE_B_MASK (0x000003FFU)
12509 #define CSL_DSS_VP3_GAMMA_TABLE_13_VALUE_B_SHIFT (0x00000000U)
12510 #define CSL_DSS_VP3_GAMMA_TABLE_13_VALUE_B_MAX (0x000003FFU)
12511 
12512 #define CSL_DSS_VP3_GAMMA_TABLE_13_VALUE_G_MASK (0x000FFC00U)
12513 #define CSL_DSS_VP3_GAMMA_TABLE_13_VALUE_G_SHIFT (0x0000000AU)
12514 #define CSL_DSS_VP3_GAMMA_TABLE_13_VALUE_G_MAX (0x000003FFU)
12515 
12516 #define CSL_DSS_VP3_GAMMA_TABLE_13_VALUE_R_MASK (0x3FF00000U)
12517 #define CSL_DSS_VP3_GAMMA_TABLE_13_VALUE_R_SHIFT (0x00000014U)
12518 #define CSL_DSS_VP3_GAMMA_TABLE_13_VALUE_R_MAX (0x000003FFU)
12519 
12520 #define CSL_DSS_VP3_GAMMA_TABLE_13_INDEX_MASK (0x80000000U)
12521 #define CSL_DSS_VP3_GAMMA_TABLE_13_INDEX_SHIFT (0x0000001FU)
12522 #define CSL_DSS_VP3_GAMMA_TABLE_13_INDEX_MAX (0x00000001U)
12523 
12524 /* GAMMA_TABLE_14 */
12525 
12526 #define CSL_DSS_VP3_GAMMA_TABLE_14_VALUE_B_MASK (0x000003FFU)
12527 #define CSL_DSS_VP3_GAMMA_TABLE_14_VALUE_B_SHIFT (0x00000000U)
12528 #define CSL_DSS_VP3_GAMMA_TABLE_14_VALUE_B_MAX (0x000003FFU)
12529 
12530 #define CSL_DSS_VP3_GAMMA_TABLE_14_VALUE_G_MASK (0x000FFC00U)
12531 #define CSL_DSS_VP3_GAMMA_TABLE_14_VALUE_G_SHIFT (0x0000000AU)
12532 #define CSL_DSS_VP3_GAMMA_TABLE_14_VALUE_G_MAX (0x000003FFU)
12533 
12534 #define CSL_DSS_VP3_GAMMA_TABLE_14_VALUE_R_MASK (0x3FF00000U)
12535 #define CSL_DSS_VP3_GAMMA_TABLE_14_VALUE_R_SHIFT (0x00000014U)
12536 #define CSL_DSS_VP3_GAMMA_TABLE_14_VALUE_R_MAX (0x000003FFU)
12537 
12538 #define CSL_DSS_VP3_GAMMA_TABLE_14_INDEX_MASK (0x80000000U)
12539 #define CSL_DSS_VP3_GAMMA_TABLE_14_INDEX_SHIFT (0x0000001FU)
12540 #define CSL_DSS_VP3_GAMMA_TABLE_14_INDEX_MAX (0x00000001U)
12541 
12542 /* GAMMA_TABLE_15 */
12543 
12544 #define CSL_DSS_VP3_GAMMA_TABLE_15_VALUE_B_MASK (0x000003FFU)
12545 #define CSL_DSS_VP3_GAMMA_TABLE_15_VALUE_B_SHIFT (0x00000000U)
12546 #define CSL_DSS_VP3_GAMMA_TABLE_15_VALUE_B_MAX (0x000003FFU)
12547 
12548 #define CSL_DSS_VP3_GAMMA_TABLE_15_VALUE_G_MASK (0x000FFC00U)
12549 #define CSL_DSS_VP3_GAMMA_TABLE_15_VALUE_G_SHIFT (0x0000000AU)
12550 #define CSL_DSS_VP3_GAMMA_TABLE_15_VALUE_G_MAX (0x000003FFU)
12551 
12552 #define CSL_DSS_VP3_GAMMA_TABLE_15_VALUE_R_MASK (0x3FF00000U)
12553 #define CSL_DSS_VP3_GAMMA_TABLE_15_VALUE_R_SHIFT (0x00000014U)
12554 #define CSL_DSS_VP3_GAMMA_TABLE_15_VALUE_R_MAX (0x000003FFU)
12555 
12556 #define CSL_DSS_VP3_GAMMA_TABLE_15_INDEX_MASK (0x80000000U)
12557 #define CSL_DSS_VP3_GAMMA_TABLE_15_INDEX_SHIFT (0x0000001FU)
12558 #define CSL_DSS_VP3_GAMMA_TABLE_15_INDEX_MAX (0x00000001U)
12559 
12560 /* DSS_OLDI_CFG */
12561 
12562 #define CSL_DSS_VP3_DSS_OLDI_CFG_RESERVED1_MASK (0x00003FFFU)
12563 #define CSL_DSS_VP3_DSS_OLDI_CFG_RESERVED1_SHIFT (0x00000000U)
12564 #define CSL_DSS_VP3_DSS_OLDI_CFG_RESERVED1_MAX (0x00003FFFU)
12565 
12566 #define CSL_DSS_VP3_DSS_OLDI_CFG_RESERVED_MASK (0xFFFFC000U)
12567 #define CSL_DSS_VP3_DSS_OLDI_CFG_RESERVED_SHIFT (0x0000000EU)
12568 #define CSL_DSS_VP3_DSS_OLDI_CFG_RESERVED_MAX (0x0003FFFFU)
12569 
12570 /* DSS_OLDI_STATUS */
12571 
12572 #define CSL_DSS_VP3_DSS_OLDI_STATUS_RESERVED_MASK (0xFFFFFFFFU)
12573 #define CSL_DSS_VP3_DSS_OLDI_STATUS_RESERVED_SHIFT (0x00000000U)
12574 #define CSL_DSS_VP3_DSS_OLDI_STATUS_RESERVED_MAX (0xFFFFFFFFU)
12575 
12576 /* DSS_OLDI_LB */
12577 
12578 #define CSL_DSS_VP3_DSS_OLDI_LB_RESERVED_MASK (0xFFFFFFFFU)
12579 #define CSL_DSS_VP3_DSS_OLDI_LB_RESERVED_SHIFT (0x00000000U)
12580 #define CSL_DSS_VP3_DSS_OLDI_LB_RESERVED_MAX (0xFFFFFFFFU)
12581 
12582 /* SECURE */
12583 
12584 #define CSL_DSS_VP3_SECURE_SECURE_MASK (0x00000001U)
12585 #define CSL_DSS_VP3_SECURE_SECURE_SHIFT (0x00000000U)
12586 #define CSL_DSS_VP3_SECURE_SECURE_MAX (0x00000001U)
12587 
12588 #define CSL_DSS_VP3_SECURE_SECURE_VAL_SECUREDIS (0x0U)
12589 #define CSL_DSS_VP3_SECURE_SECURE_VAL_SECUREEN (0x1U)
12590 
12591 #define CSL_DSS_VP3_SECURE_RESERVED_MASK (0xFFFFFFFEU)
12592 #define CSL_DSS_VP3_SECURE_RESERVED_SHIFT (0x00000001U)
12593 #define CSL_DSS_VP3_SECURE_RESERVED_MAX (0x7FFFFFFFU)
12594 
12595 /**************************************************************************
12596 * Hardware Region : OVR4 Registers
12597 **************************************************************************/
12598 
12599 
12600 /**************************************************************************
12601 * Register Overlay Structure
12602 **************************************************************************/
12603 
12604 typedef struct {
12605  volatile uint32_t CONFIG; /* CONFIG */
12606  volatile uint32_t VIRTUALVP; /* VIRTUALVP */
12607  volatile uint32_t DEFAULT_COLOR; /* DEFAULT_COLOR */
12608  volatile uint32_t DEFAULT_COLOR2; /* DEFAULT_COLOR2 */
12609  volatile uint32_t TRANS_COLOR_MAX; /* TRANS_COLOR_MAX */
12610  volatile uint32_t TRANS_COLOR_MAX2; /* TRANS_COLOR_MAX2 */
12611  volatile uint32_t TRANS_COLOR_MIN; /* TRANS_COLOR_MIN */
12612  volatile uint32_t TRANS_COLOR_MIN2; /* TRANS_COLOR_MIN2 */
12613  volatile uint32_t ATTRIBUTES[5U]; /* ATTRIBUTES 0..4 */
12614  volatile uint32_t ATTRIBUTES2[5U]; /* ATTRIBUTES2 0..4 */
12615  volatile uint32_t SECURE; /* SECURE */
12617 
12618 
12619 /**************************************************************************
12620 * Register Macros
12621 **************************************************************************/
12622 
12623 #define CSL_DSS_OVR4_CONFIG (0x00000000U)
12624 #define CSL_DSS_OVR4_VIRTUALVP (0x00000004U)
12625 #define CSL_DSS_OVR4_DEFAULT_COLOR (0x00000008U)
12626 #define CSL_DSS_OVR4_DEFAULT_COLOR2 (0x0000000CU)
12627 #define CSL_DSS_OVR4_TRANS_COLOR_MAX (0x00000010U)
12628 #define CSL_DSS_OVR4_TRANS_COLOR_MAX2 (0x00000014U)
12629 #define CSL_DSS_OVR4_TRANS_COLOR_MIN (0x00000018U)
12630 #define CSL_DSS_OVR4_TRANS_COLOR_MIN2 (0x0000001CU)
12631 #define CSL_DSS_OVR4_ATTRIBUTES(index) (0x00000020U+((uint32_t)(index)*0x4U))
12632 #define CSL_DSS_OVR4_ATTRIBUTES2(index) (0x00000034U+((uint32_t)(index)*0x4U))
12633 #define CSL_DSS_OVR4_SECURE (0x00000048U)
12634 
12635 /**************************************************************************
12636 * Field Definition Macros
12637 **************************************************************************/
12638 
12639 
12640 /* CONFIG */
12641 
12642 #define CSL_DSS_OVR4_CONFIG_RESERVED6_MASK (0x00000001U)
12643 #define CSL_DSS_OVR4_CONFIG_RESERVED6_SHIFT (0x00000000U)
12644 #define CSL_DSS_OVR4_CONFIG_RESERVED6_MAX (0x00000001U)
12645 
12646 #define CSL_DSS_OVR4_CONFIG_COLORBAREN_MASK (0x00000002U)
12647 #define CSL_DSS_OVR4_CONFIG_COLORBAREN_SHIFT (0x00000001U)
12648 #define CSL_DSS_OVR4_CONFIG_COLORBAREN_MAX (0x00000001U)
12649 
12650 #define CSL_DSS_OVR4_CONFIG_COLORBAREN_VAL_COLORBARDIS (0x0U)
12651 #define CSL_DSS_OVR4_CONFIG_COLORBAREN_VAL_COLORBAREN (0x1U)
12652 
12653 #define CSL_DSS_OVR4_CONFIG_RESERVED_MASK (0x000003FCU)
12654 #define CSL_DSS_OVR4_CONFIG_RESERVED_SHIFT (0x00000002U)
12655 #define CSL_DSS_OVR4_CONFIG_RESERVED_MAX (0x000000FFU)
12656 
12657 #define CSL_DSS_OVR4_CONFIG_TCKLCDENABLE_MASK (0x00000400U)
12658 #define CSL_DSS_OVR4_CONFIG_TCKLCDENABLE_SHIFT (0x0000000AU)
12659 #define CSL_DSS_OVR4_CONFIG_TCKLCDENABLE_MAX (0x00000001U)
12660 
12661 #define CSL_DSS_OVR4_CONFIG_TCKLCDENABLE_VAL_DISTCK (0x0U)
12662 #define CSL_DSS_OVR4_CONFIG_TCKLCDENABLE_VAL_ENBTCK (0x1U)
12663 
12664 #define CSL_DSS_OVR4_CONFIG_TCKLCDSELECTION_MASK (0x00000800U)
12665 #define CSL_DSS_OVR4_CONFIG_TCKLCDSELECTION_SHIFT (0x0000000BU)
12666 #define CSL_DSS_OVR4_CONFIG_TCKLCDSELECTION_MAX (0x00000001U)
12667 
12668 #define CSL_DSS_OVR4_CONFIG_TCKLCDSELECTION_VAL_GDTK (0x0U)
12669 #define CSL_DSS_OVR4_CONFIG_TCKLCDSELECTION_VAL_VSTK (0x1U)
12670 
12671 #define CSL_DSS_OVR4_CONFIG_RESERVED2_MASK (0x00001000U)
12672 #define CSL_DSS_OVR4_CONFIG_RESERVED2_SHIFT (0x0000000CU)
12673 #define CSL_DSS_OVR4_CONFIG_RESERVED2_MAX (0x00000001U)
12674 
12675 #define CSL_DSS_OVR4_CONFIG_RESERVED3_MASK (0x00002000U)
12676 #define CSL_DSS_OVR4_CONFIG_RESERVED3_SHIFT (0x0000000DU)
12677 #define CSL_DSS_OVR4_CONFIG_RESERVED3_MAX (0x00000001U)
12678 
12679 #define CSL_DSS_OVR4_CONFIG_RESERVED1_MASK (0xFFFFC000U)
12680 #define CSL_DSS_OVR4_CONFIG_RESERVED1_SHIFT (0x0000000EU)
12681 #define CSL_DSS_OVR4_CONFIG_RESERVED1_MAX (0x0003FFFFU)
12682 
12683 /* VIRTUALVP */
12684 
12685 #define CSL_DSS_OVR4_VIRTUALVP_PPL_MASK (0x00003FFFU)
12686 #define CSL_DSS_OVR4_VIRTUALVP_PPL_SHIFT (0x00000000U)
12687 #define CSL_DSS_OVR4_VIRTUALVP_PPL_MAX (0x00003FFFU)
12688 
12689 #define CSL_DSS_OVR4_VIRTUALVP_LPP_MASK (0x3FFF0000U)
12690 #define CSL_DSS_OVR4_VIRTUALVP_LPP_SHIFT (0x00000010U)
12691 #define CSL_DSS_OVR4_VIRTUALVP_LPP_MAX (0x00003FFFU)
12692 
12693 #define CSL_DSS_OVR4_VIRTUALVP_ENABLE_MASK (0x80000000U)
12694 #define CSL_DSS_OVR4_VIRTUALVP_ENABLE_SHIFT (0x0000001FU)
12695 #define CSL_DSS_OVR4_VIRTUALVP_ENABLE_MAX (0x00000001U)
12696 
12697 /* DEFAULT_COLOR */
12698 
12699 #define CSL_DSS_OVR4_DEFAULT_COLOR_DEFAULTCOLOR_MASK (0xFFFFFFFFU)
12700 #define CSL_DSS_OVR4_DEFAULT_COLOR_DEFAULTCOLOR_SHIFT (0x00000000U)
12701 #define CSL_DSS_OVR4_DEFAULT_COLOR_DEFAULTCOLOR_MAX (0xFFFFFFFFU)
12702 
12703 /* DEFAULT_COLOR2 */
12704 
12705 #define CSL_DSS_OVR4_DEFAULT_COLOR2_DEFAULTCOLOR_MASK (0x0000FFFFU)
12706 #define CSL_DSS_OVR4_DEFAULT_COLOR2_DEFAULTCOLOR_SHIFT (0x00000000U)
12707 #define CSL_DSS_OVR4_DEFAULT_COLOR2_DEFAULTCOLOR_MAX (0x0000FFFFU)
12708 
12709 #define CSL_DSS_OVR4_DEFAULT_COLOR2_RESERVED_MASK (0xFFFF0000U)
12710 #define CSL_DSS_OVR4_DEFAULT_COLOR2_RESERVED_SHIFT (0x00000010U)
12711 #define CSL_DSS_OVR4_DEFAULT_COLOR2_RESERVED_MAX (0x0000FFFFU)
12712 
12713 /* TRANS_COLOR_MAX */
12714 
12715 #define CSL_DSS_OVR4_TRANS_COLOR_MAX_TRANSCOLORKEY_MASK (0xFFFFFFFFU)
12716 #define CSL_DSS_OVR4_TRANS_COLOR_MAX_TRANSCOLORKEY_SHIFT (0x00000000U)
12717 #define CSL_DSS_OVR4_TRANS_COLOR_MAX_TRANSCOLORKEY_MAX (0xFFFFFFFFU)
12718 
12719 /* TRANS_COLOR_MAX2 */
12720 
12721 #define CSL_DSS_OVR4_TRANS_COLOR_MAX2_TRANSCOLORKEY_MASK (0x0000000FU)
12722 #define CSL_DSS_OVR4_TRANS_COLOR_MAX2_TRANSCOLORKEY_SHIFT (0x00000000U)
12723 #define CSL_DSS_OVR4_TRANS_COLOR_MAX2_TRANSCOLORKEY_MAX (0x0000000FU)
12724 
12725 #define CSL_DSS_OVR4_TRANS_COLOR_MAX2_RESERVED_MASK (0xFFFFFFF0U)
12726 #define CSL_DSS_OVR4_TRANS_COLOR_MAX2_RESERVED_SHIFT (0x00000004U)
12727 #define CSL_DSS_OVR4_TRANS_COLOR_MAX2_RESERVED_MAX (0x0FFFFFFFU)
12728 
12729 /* TRANS_COLOR_MIN */
12730 
12731 #define CSL_DSS_OVR4_TRANS_COLOR_MIN_TRANSCOLORKEY_MASK (0xFFFFFFFFU)
12732 #define CSL_DSS_OVR4_TRANS_COLOR_MIN_TRANSCOLORKEY_SHIFT (0x00000000U)
12733 #define CSL_DSS_OVR4_TRANS_COLOR_MIN_TRANSCOLORKEY_MAX (0xFFFFFFFFU)
12734 
12735 /* TRANS_COLOR_MIN2 */
12736 
12737 #define CSL_DSS_OVR4_TRANS_COLOR_MIN2_TRANSCOLORKEY_MASK (0x0000000FU)
12738 #define CSL_DSS_OVR4_TRANS_COLOR_MIN2_TRANSCOLORKEY_SHIFT (0x00000000U)
12739 #define CSL_DSS_OVR4_TRANS_COLOR_MIN2_TRANSCOLORKEY_MAX (0x0000000FU)
12740 
12741 #define CSL_DSS_OVR4_TRANS_COLOR_MIN2_RESERVED_MASK (0xFFFFFFF0U)
12742 #define CSL_DSS_OVR4_TRANS_COLOR_MIN2_RESERVED_SHIFT (0x00000004U)
12743 #define CSL_DSS_OVR4_TRANS_COLOR_MIN2_RESERVED_MAX (0x0FFFFFFFU)
12744 
12745 /* ATTRIBUTES */
12746 
12747 #define CSL_DSS_OVR4_ATTRIBUTES_ENABLE_MASK (0x00000001U)
12748 #define CSL_DSS_OVR4_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
12749 #define CSL_DSS_OVR4_ATTRIBUTES_ENABLE_MAX (0x00000001U)
12750 
12751 #define CSL_DSS_OVR4_ATTRIBUTES_CHANNELIN_MASK (0x0000001EU)
12752 #define CSL_DSS_OVR4_ATTRIBUTES_CHANNELIN_SHIFT (0x00000001U)
12753 #define CSL_DSS_OVR4_ATTRIBUTES_CHANNELIN_MAX (0x0000000FU)
12754 
12755 #define CSL_DSS_OVR4_ATTRIBUTES_CHANNELIN_VAL_VID1 (0x0U)
12756 #define CSL_DSS_OVR4_ATTRIBUTES_CHANNELIN_VAL_VIDL1 (0x1U)
12757 #define CSL_DSS_OVR4_ATTRIBUTES_CHANNELIN_VAL_VID2 (0x2U)
12758 #define CSL_DSS_OVR4_ATTRIBUTES_CHANNELIN_VAL_VIDL2 (0x3U)
12759 #define CSL_DSS_OVR4_ATTRIBUTES_CHANNELIN_VAL_VIRTCH (0x4U)
12760 
12761 /* ATTRIBUTES2 */
12762 
12763 #define CSL_DSS_OVR4_ATTRIBUTES2_POSX_MASK (0x00003FFFU)
12764 #define CSL_DSS_OVR4_ATTRIBUTES2_POSX_SHIFT (0x00000000U)
12765 #define CSL_DSS_OVR4_ATTRIBUTES2_POSX_MAX (0x00003FFFU)
12766 
12767 #define CSL_DSS_OVR4_ATTRIBUTES2_POSY_MASK (0x3FFF0000U)
12768 #define CSL_DSS_OVR4_ATTRIBUTES2_POSY_SHIFT (0x00000010U)
12769 #define CSL_DSS_OVR4_ATTRIBUTES2_POSY_MAX (0x00003FFFU)
12770 
12771 /* SECURE */
12772 
12773 #define CSL_DSS_OVR4_SECURE_SECURE_MASK (0x00000001U)
12774 #define CSL_DSS_OVR4_SECURE_SECURE_SHIFT (0x00000000U)
12775 #define CSL_DSS_OVR4_SECURE_SECURE_MAX (0x00000001U)
12776 
12777 #define CSL_DSS_OVR4_SECURE_SECURE_VAL_SECUREDIS (0x0U)
12778 #define CSL_DSS_OVR4_SECURE_SECURE_VAL_SECUREEN (0x1U)
12779 
12780 #define CSL_DSS_OVR4_SECURE_RESERVED_MASK (0xFFFFFFFEU)
12781 #define CSL_DSS_OVR4_SECURE_RESERVED_SHIFT (0x00000001U)
12782 #define CSL_DSS_OVR4_SECURE_RESERVED_MAX (0x7FFFFFFFU)
12783 
12784 /**************************************************************************
12785 * Hardware Region : VP4 Registers
12786 **************************************************************************/
12787 
12788 
12789 /**************************************************************************
12790 * Register Overlay Structure
12791 **************************************************************************/
12792 
12793 typedef struct {
12794  volatile uint32_t CONFIG; /* CONFIG */
12795  volatile uint32_t CONTROL; /* CONTROL */
12796  volatile uint32_t CSC_COEF0; /* CSC_COEF0 */
12797  volatile uint32_t CSC_COEF1; /* CSC_COEF1 */
12798  volatile uint32_t CSC_COEF2; /* CSC_COEF2 */
12799  volatile uint32_t DATA_CYCLE_0; /* DATA_CYCLE_0 */
12800  volatile uint32_t DATA_CYCLE_1; /* DATA_CYCLE_1 */
12801  volatile uint32_t DATA_CYCLE_2; /* DATA_CYCLE_2 */
12802  volatile uint8_t Resv_68[36];
12803  volatile uint32_t LINE_NUMBER; /* LINE_NUMBER */
12804  volatile uint8_t Resv_76[4];
12805  volatile uint32_t POL_FREQ; /* POL_FREQ */
12806  volatile uint32_t SIZE_SCREEN; /* SIZE_SCREEN */
12807  volatile uint32_t TIMING_H; /* TIMING_H */
12808  volatile uint32_t TIMING_V; /* TIMING_V */
12809  volatile uint32_t CSC_COEF3; /* CSC_COEF3 */
12810  volatile uint32_t CSC_COEF4; /* CSC_COEF4 */
12811  volatile uint32_t CSC_COEF5; /* CSC_COEF5 */
12812  volatile uint32_t CSC_COEF6; /* CSC_COEF6 */
12813  volatile uint32_t CSC_COEF7; /* CSC_COEF7 */
12814  volatile uint32_t SAFETY_ATTRIBUTES[8U]; /* SAFETY_ATTRIBUTES 0..7 */
12815  volatile uint32_t SAFETY_CAPT_SIGNATURE[8U]; /* SAFETY_CAPT_SIGNATURE 0..7 */
12816  volatile uint32_t SAFETY_POSITION[8U]; /* SAFETY_POSITION 0..7 */
12817  volatile uint32_t SAFETY_REF_SIGNATURE[8U]; /* SAFETY_REF_SIGNATURE 0..7 */
12818  volatile uint32_t SAFETY_SIZE[8U]; /* SAFETY_SIZE 0..7 */
12819  volatile uint32_t SAFETY_LFSR_SEED; /* SAFETY_LFSR_SEED */
12820  volatile uint8_t Resv_288[12];
12821  volatile uint32_t GAMMA_TABLE_0; /* GAMMA_TABLE_0 */
12822  volatile uint32_t GAMMA_TABLE_1; /* GAMMA_TABLE_1 */
12823  volatile uint32_t GAMMA_TABLE_2; /* GAMMA_TABLE_2 */
12824  volatile uint32_t GAMMA_TABLE_3; /* GAMMA_TABLE_3 */
12825  volatile uint32_t GAMMA_TABLE_4; /* GAMMA_TABLE_4 */
12826  volatile uint32_t GAMMA_TABLE_5; /* GAMMA_TABLE_5 */
12827  volatile uint32_t GAMMA_TABLE_6; /* GAMMA_TABLE_6 */
12828  volatile uint32_t GAMMA_TABLE_7; /* GAMMA_TABLE_7 */
12829  volatile uint32_t GAMMA_TABLE_8; /* GAMMA_TABLE_8 */
12830  volatile uint32_t GAMMA_TABLE_9; /* GAMMA_TABLE_9 */
12831  volatile uint32_t GAMMA_TABLE_10; /* GAMMA_TABLE_10 */
12832  volatile uint32_t GAMMA_TABLE_11; /* GAMMA_TABLE_11 */
12833  volatile uint32_t GAMMA_TABLE_12; /* GAMMA_TABLE_12 */
12834  volatile uint32_t GAMMA_TABLE_13; /* GAMMA_TABLE_13 */
12835  volatile uint32_t GAMMA_TABLE_14; /* GAMMA_TABLE_14 */
12836  volatile uint32_t GAMMA_TABLE_15; /* GAMMA_TABLE_15 */
12837  volatile uint32_t DSS_OLDI_CFG; /* DSS_OLDI_CFG */
12838  volatile uint32_t DSS_OLDI_STATUS; /* DSS_OLDI_STATUS */
12839  volatile uint32_t DSS_OLDI_LB; /* DSS_OLDI_LB */
12840  volatile uint8_t Resv_376[12];
12841  volatile uint32_t SECURE; /* SECURE */
12842 } CSL_dss_vp4Regs;
12843 
12844 
12845 /**************************************************************************
12846 * Register Macros
12847 **************************************************************************/
12848 
12849 #define CSL_DSS_VP4_CONFIG (0x00000000U)
12850 #define CSL_DSS_VP4_CONTROL (0x00000004U)
12851 #define CSL_DSS_VP4_CSC_COEF0 (0x00000008U)
12852 #define CSL_DSS_VP4_CSC_COEF1 (0x0000000CU)
12853 #define CSL_DSS_VP4_CSC_COEF2 (0x00000010U)
12854 #define CSL_DSS_VP4_DATA_CYCLE_0 (0x00000014U)
12855 #define CSL_DSS_VP4_DATA_CYCLE_1 (0x00000018U)
12856 #define CSL_DSS_VP4_DATA_CYCLE_2 (0x0000001CU)
12857 #define CSL_DSS_VP4_LINE_NUMBER (0x00000044U)
12858 #define CSL_DSS_VP4_POL_FREQ (0x0000004CU)
12859 #define CSL_DSS_VP4_SIZE_SCREEN (0x00000050U)
12860 #define CSL_DSS_VP4_TIMING_H (0x00000054U)
12861 #define CSL_DSS_VP4_TIMING_V (0x00000058U)
12862 #define CSL_DSS_VP4_CSC_COEF3 (0x0000005CU)
12863 #define CSL_DSS_VP4_CSC_COEF4 (0x00000060U)
12864 #define CSL_DSS_VP4_CSC_COEF5 (0x00000064U)
12865 #define CSL_DSS_VP4_CSC_COEF6 (0x00000068U)
12866 #define CSL_DSS_VP4_CSC_COEF7 (0x0000006CU)
12867 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES(index) (0x00000070U+((uint32_t)(index)*0x4U))
12868 #define CSL_DSS_VP4_SAFETY_CAPT_SIGNATURE(index) (0x00000090U+((uint32_t)(index)*0x4U))
12869 #define CSL_DSS_VP4_SAFETY_POSITION(index) (0x000000B0U+((uint32_t)(index)*0x4U))
12870 #define CSL_DSS_VP4_SAFETY_REF_SIGNATURE(index) (0x000000D0U+((uint32_t)(index)*0x4U))
12871 #define CSL_DSS_VP4_SAFETY_SIZE(index) (0x000000F0U+((uint32_t)(index)*0x4U))
12872 #define CSL_DSS_VP4_SAFETY_LFSR_SEED (0x00000110U)
12873 #define CSL_DSS_VP4_GAMMA_TABLE_0 (0x00000120U)
12874 #define CSL_DSS_VP4_GAMMA_TABLE_1 (0x00000124U)
12875 #define CSL_DSS_VP4_GAMMA_TABLE_2 (0x00000128U)
12876 #define CSL_DSS_VP4_GAMMA_TABLE_3 (0x0000012CU)
12877 #define CSL_DSS_VP4_GAMMA_TABLE_4 (0x00000130U)
12878 #define CSL_DSS_VP4_GAMMA_TABLE_5 (0x00000134U)
12879 #define CSL_DSS_VP4_GAMMA_TABLE_6 (0x00000138U)
12880 #define CSL_DSS_VP4_GAMMA_TABLE_7 (0x0000013CU)
12881 #define CSL_DSS_VP4_GAMMA_TABLE_8 (0x00000140U)
12882 #define CSL_DSS_VP4_GAMMA_TABLE_9 (0x00000144U)
12883 #define CSL_DSS_VP4_GAMMA_TABLE_10 (0x00000148U)
12884 #define CSL_DSS_VP4_GAMMA_TABLE_11 (0x0000014CU)
12885 #define CSL_DSS_VP4_GAMMA_TABLE_12 (0x00000150U)
12886 #define CSL_DSS_VP4_GAMMA_TABLE_13 (0x00000154U)
12887 #define CSL_DSS_VP4_GAMMA_TABLE_14 (0x00000158U)
12888 #define CSL_DSS_VP4_GAMMA_TABLE_15 (0x0000015CU)
12889 #define CSL_DSS_VP4_DSS_OLDI_CFG (0x00000160U)
12890 #define CSL_DSS_VP4_DSS_OLDI_STATUS (0x00000164U)
12891 #define CSL_DSS_VP4_DSS_OLDI_LB (0x00000168U)
12892 #define CSL_DSS_VP4_SECURE (0x00000178U)
12893 
12894 /**************************************************************************
12895 * Field Definition Macros
12896 **************************************************************************/
12897 
12898 
12899 /* CONFIG */
12900 
12901 #define CSL_DSS_VP4_CONFIG_PIXELGATED_MASK (0x00000001U)
12902 #define CSL_DSS_VP4_CONFIG_PIXELGATED_SHIFT (0x00000000U)
12903 #define CSL_DSS_VP4_CONFIG_PIXELGATED_MAX (0x00000001U)
12904 
12905 #define CSL_DSS_VP4_CONFIG_PIXELGATED_VAL_PCLKTOGA (0x0U)
12906 #define CSL_DSS_VP4_CONFIG_PIXELGATED_VAL_PCLKTOGV (0x1U)
12907 
12908 #define CSL_DSS_VP4_CONFIG_DATAENABLEGATED_MASK (0x00000002U)
12909 #define CSL_DSS_VP4_CONFIG_DATAENABLEGATED_SHIFT (0x00000001U)
12910 #define CSL_DSS_VP4_CONFIG_DATAENABLEGATED_MAX (0x00000001U)
12911 
12912 #define CSL_DSS_VP4_CONFIG_DATAENABLEGATED_VAL_DEGDIS (0x0U)
12913 #define CSL_DSS_VP4_CONFIG_DATAENABLEGATED_VAL_DEGENB (0x1U)
12914 
12915 #define CSL_DSS_VP4_CONFIG_GAMMAENABLE_MASK (0x00000004U)
12916 #define CSL_DSS_VP4_CONFIG_GAMMAENABLE_SHIFT (0x00000002U)
12917 #define CSL_DSS_VP4_CONFIG_GAMMAENABLE_MAX (0x00000001U)
12918 
12919 #define CSL_DSS_VP4_CONFIG_GAMMAENABLE_VAL_GAMMADIS (0x0U)
12920 #define CSL_DSS_VP4_CONFIG_GAMMAENABLE_VAL_GAMMAENB (0x1U)
12921 
12922 #define CSL_DSS_VP4_CONFIG_HDMIMODE_MASK (0x00000008U)
12923 #define CSL_DSS_VP4_CONFIG_HDMIMODE_SHIFT (0x00000003U)
12924 #define CSL_DSS_VP4_CONFIG_HDMIMODE_MAX (0x00000001U)
12925 
12926 #define CSL_DSS_VP4_CONFIG_PIXELDATAGATED_MASK (0x00000010U)
12927 #define CSL_DSS_VP4_CONFIG_PIXELDATAGATED_SHIFT (0x00000004U)
12928 #define CSL_DSS_VP4_CONFIG_PIXELDATAGATED_MAX (0x00000001U)
12929 
12930 #define CSL_DSS_VP4_CONFIG_PIXELDATAGATED_VAL_PDGDIS (0x0U)
12931 #define CSL_DSS_VP4_CONFIG_PIXELDATAGATED_VAL_PDGENB (0x1U)
12932 
12933 #define CSL_DSS_VP4_CONFIG_PIXELCLOCKGATED_MASK (0x00000020U)
12934 #define CSL_DSS_VP4_CONFIG_PIXELCLOCKGATED_SHIFT (0x00000005U)
12935 #define CSL_DSS_VP4_CONFIG_PIXELCLOCKGATED_MAX (0x00000001U)
12936 
12937 #define CSL_DSS_VP4_CONFIG_PIXELCLOCKGATED_VAL_PCGDIS (0x0U)
12938 #define CSL_DSS_VP4_CONFIG_PIXELCLOCKGATED_VAL_PCGENB (0x1U)
12939 
12940 #define CSL_DSS_VP4_CONFIG_HSYNCGATED_MASK (0x00000040U)
12941 #define CSL_DSS_VP4_CONFIG_HSYNCGATED_SHIFT (0x00000006U)
12942 #define CSL_DSS_VP4_CONFIG_HSYNCGATED_MAX (0x00000001U)
12943 
12944 #define CSL_DSS_VP4_CONFIG_HSYNCGATED_VAL_HGDIS (0x0U)
12945 #define CSL_DSS_VP4_CONFIG_HSYNCGATED_VAL_HGENB (0x1U)
12946 
12947 #define CSL_DSS_VP4_CONFIG_VSYNCGATED_MASK (0x00000080U)
12948 #define CSL_DSS_VP4_CONFIG_VSYNCGATED_SHIFT (0x00000007U)
12949 #define CSL_DSS_VP4_CONFIG_VSYNCGATED_MAX (0x00000001U)
12950 
12951 #define CSL_DSS_VP4_CONFIG_VSYNCGATED_VAL_VGDIS (0x0U)
12952 #define CSL_DSS_VP4_CONFIG_VSYNCGATED_VAL_VGENB (0x1U)
12953 
12954 #define CSL_DSS_VP4_CONFIG_EXTERNALSYNCEN_MASK (0x00000100U)
12955 #define CSL_DSS_VP4_CONFIG_EXTERNALSYNCEN_SHIFT (0x00000008U)
12956 #define CSL_DSS_VP4_CONFIG_EXTERNALSYNCEN_MAX (0x00000001U)
12957 
12958 #define CSL_DSS_VP4_CONFIG_RESERVED1_MASK (0x00007E00U)
12959 #define CSL_DSS_VP4_CONFIG_RESERVED1_SHIFT (0x00000009U)
12960 #define CSL_DSS_VP4_CONFIG_RESERVED1_MAX (0x0000003FU)
12961 
12962 #define CSL_DSS_VP4_CONFIG_CPR_MASK (0x00008000U)
12963 #define CSL_DSS_VP4_CONFIG_CPR_SHIFT (0x0000000FU)
12964 #define CSL_DSS_VP4_CONFIG_CPR_MAX (0x00000001U)
12965 
12966 #define CSL_DSS_VP4_CONFIG_BUFFERHANDSHAKE_MASK (0x00010000U)
12967 #define CSL_DSS_VP4_CONFIG_BUFFERHANDSHAKE_SHIFT (0x00000010U)
12968 #define CSL_DSS_VP4_CONFIG_BUFFERHANDSHAKE_MAX (0x00000001U)
12969 
12970 #define CSL_DSS_VP4_CONFIG_RESERVED2_MASK (0x000E0000U)
12971 #define CSL_DSS_VP4_CONFIG_RESERVED2_SHIFT (0x00000011U)
12972 #define CSL_DSS_VP4_CONFIG_RESERVED2_MAX (0x00000007U)
12973 
12974 #define CSL_DSS_VP4_CONFIG_BT656ENABLE_MASK (0x00100000U)
12975 #define CSL_DSS_VP4_CONFIG_BT656ENABLE_SHIFT (0x00000014U)
12976 #define CSL_DSS_VP4_CONFIG_BT656ENABLE_MAX (0x00000001U)
12977 
12978 #define CSL_DSS_VP4_CONFIG_BT656ENABLE_VAL_DISABLE (0x0U)
12979 #define CSL_DSS_VP4_CONFIG_BT656ENABLE_VAL_ENABLE (0x1U)
12980 
12981 #define CSL_DSS_VP4_CONFIG_BT1120ENABLE_MASK (0x00200000U)
12982 #define CSL_DSS_VP4_CONFIG_BT1120ENABLE_SHIFT (0x00000015U)
12983 #define CSL_DSS_VP4_CONFIG_BT1120ENABLE_MAX (0x00000001U)
12984 
12985 #define CSL_DSS_VP4_CONFIG_BT1120ENABLE_VAL_DISABLE (0x0U)
12986 #define CSL_DSS_VP4_CONFIG_BT1120ENABLE_VAL_ENABLE (0x1U)
12987 
12988 #define CSL_DSS_VP4_CONFIG_OUTPUTMODEENABLE_MASK (0x00400000U)
12989 #define CSL_DSS_VP4_CONFIG_OUTPUTMODEENABLE_SHIFT (0x00000016U)
12990 #define CSL_DSS_VP4_CONFIG_OUTPUTMODEENABLE_MAX (0x00000001U)
12991 
12992 #define CSL_DSS_VP4_CONFIG_OUTPUTMODEENABLE_VAL_DISABLE (0x0U)
12993 #define CSL_DSS_VP4_CONFIG_OUTPUTMODEENABLE_VAL_ENABLE (0x1U)
12994 
12995 #define CSL_DSS_VP4_CONFIG_FIDFIRST_MASK (0x00800000U)
12996 #define CSL_DSS_VP4_CONFIG_FIDFIRST_SHIFT (0x00000017U)
12997 #define CSL_DSS_VP4_CONFIG_FIDFIRST_MAX (0x00000001U)
12998 
12999 #define CSL_DSS_VP4_CONFIG_FIDFIRST_VAL_EVEN (0x0U)
13000 #define CSL_DSS_VP4_CONFIG_FIDFIRST_VAL_ODD (0x1U)
13001 
13002 #define CSL_DSS_VP4_CONFIG_COLORCONVENABLE_MASK (0x01000000U)
13003 #define CSL_DSS_VP4_CONFIG_COLORCONVENABLE_SHIFT (0x00000018U)
13004 #define CSL_DSS_VP4_CONFIG_COLORCONVENABLE_MAX (0x00000001U)
13005 
13006 #define CSL_DSS_VP4_CONFIG_COLORCONVENABLE_VAL_COLSPCDIS (0x0U)
13007 #define CSL_DSS_VP4_CONFIG_COLORCONVENABLE_VAL_COLSPCENB (0x1U)
13008 
13009 #define CSL_DSS_VP4_CONFIG_FULLRANGE_MASK (0x02000000U)
13010 #define CSL_DSS_VP4_CONFIG_FULLRANGE_SHIFT (0x00000019U)
13011 #define CSL_DSS_VP4_CONFIG_FULLRANGE_MAX (0x00000001U)
13012 
13013 #define CSL_DSS_VP4_CONFIG_FULLRANGE_VAL_LIMRANGE (0x0U)
13014 #define CSL_DSS_VP4_CONFIG_FULLRANGE_VAL_FULLRANGE (0x1U)
13015 
13016 #define CSL_DSS_VP4_CONFIG_COLORCONVPOS_MASK (0x04000000U)
13017 #define CSL_DSS_VP4_CONFIG_COLORCONVPOS_SHIFT (0x0000001AU)
13018 #define CSL_DSS_VP4_CONFIG_COLORCONVPOS_MAX (0x00000001U)
13019 
13020 #define CSL_DSS_VP4_CONFIG_COLORCONVPOS_VAL_AFTERGAMMA (0x0U)
13021 #define CSL_DSS_VP4_CONFIG_COLORCONVPOS_VAL_BEFOREGAMMA (0x1U)
13022 
13023 #define CSL_DSS_VP4_CONFIG_RESERVED3_MASK (0xF8000000U)
13024 #define CSL_DSS_VP4_CONFIG_RESERVED3_SHIFT (0x0000001BU)
13025 #define CSL_DSS_VP4_CONFIG_RESERVED3_MAX (0x0000001FU)
13026 
13027 /* CONTROL */
13028 
13029 #define CSL_DSS_VP4_CONTROL_ENABLE_MASK (0x00000001U)
13030 #define CSL_DSS_VP4_CONTROL_ENABLE_SHIFT (0x00000000U)
13031 #define CSL_DSS_VP4_CONTROL_ENABLE_MAX (0x00000001U)
13032 
13033 #define CSL_DSS_VP4_CONTROL_ENABLE_VAL_LCDOPDIS (0x0U)
13034 #define CSL_DSS_VP4_CONTROL_ENABLE_VAL_LCDOPENB (0x1U)
13035 
13036 #define CSL_DSS_VP4_CONTROL_VPPROGLINENUMBERMODULO_MASK (0x00000002U)
13037 #define CSL_DSS_VP4_CONTROL_VPPROGLINENUMBERMODULO_SHIFT (0x00000001U)
13038 #define CSL_DSS_VP4_CONTROL_VPPROGLINENUMBERMODULO_MAX (0x00000001U)
13039 
13040 #define CSL_DSS_VP4_CONTROL_VPPROGLINENUMBERMODULO_VAL_MODDIS (0x0U)
13041 #define CSL_DSS_VP4_CONTROL_VPPROGLINENUMBERMODULO_VAL_MODEN (0x1U)
13042 
13043 #define CSL_DSS_VP4_CONTROL_MONOCOLOR_MASK (0x00000004U)
13044 #define CSL_DSS_VP4_CONTROL_MONOCOLOR_SHIFT (0x00000002U)
13045 #define CSL_DSS_VP4_CONTROL_MONOCOLOR_MAX (0x00000001U)
13046 
13047 #define CSL_DSS_VP4_CONTROL_STN_MASK (0x00000008U)
13048 #define CSL_DSS_VP4_CONTROL_STN_SHIFT (0x00000003U)
13049 #define CSL_DSS_VP4_CONTROL_STN_MAX (0x00000001U)
13050 
13051 #define CSL_DSS_VP4_CONTROL_M8B_MASK (0x00000010U)
13052 #define CSL_DSS_VP4_CONTROL_M8B_SHIFT (0x00000004U)
13053 #define CSL_DSS_VP4_CONTROL_M8B_MAX (0x00000001U)
13054 
13055 #define CSL_DSS_VP4_CONTROL_GOBIT_MASK (0x00000020U)
13056 #define CSL_DSS_VP4_CONTROL_GOBIT_SHIFT (0x00000005U)
13057 #define CSL_DSS_VP4_CONTROL_GOBIT_MAX (0x00000001U)
13058 
13059 #define CSL_DSS_VP4_CONTROL_GOBIT_VAL_HFUISR (0x0U)
13060 #define CSL_DSS_VP4_CONTROL_GOBIT_VAL_UFPSR (0x1U)
13061 
13062 #define CSL_DSS_VP4_CONTROL_DPIENABLE_MASK (0x00000040U)
13063 #define CSL_DSS_VP4_CONTROL_DPIENABLE_SHIFT (0x00000006U)
13064 #define CSL_DSS_VP4_CONTROL_DPIENABLE_MAX (0x00000001U)
13065 
13066 #define CSL_DSS_VP4_CONTROL_DPIENABLE_VAL_DPIOPDIS (0x0U)
13067 #define CSL_DSS_VP4_CONTROL_DPIENABLE_VAL_DPIOPENB (0x1U)
13068 
13069 #define CSL_DSS_VP4_CONTROL_STDITHERENABLE_MASK (0x00000080U)
13070 #define CSL_DSS_VP4_CONTROL_STDITHERENABLE_SHIFT (0x00000007U)
13071 #define CSL_DSS_VP4_CONTROL_STDITHERENABLE_MAX (0x00000001U)
13072 
13073 #define CSL_DSS_VP4_CONTROL_STDITHERENABLE_VAL_STDITHDIS (0x0U)
13074 #define CSL_DSS_VP4_CONTROL_STDITHERENABLE_VAL_STDITHENB (0x1U)
13075 
13076 #define CSL_DSS_VP4_CONTROL_DATALINES_MASK (0x00000700U)
13077 #define CSL_DSS_VP4_CONTROL_DATALINES_SHIFT (0x00000008U)
13078 #define CSL_DSS_VP4_CONTROL_DATALINES_MAX (0x00000007U)
13079 
13080 #define CSL_DSS_VP4_CONTROL_DATALINES_VAL_OALSB12B (0x0U)
13081 #define CSL_DSS_VP4_CONTROL_DATALINES_VAL_OALSB16B (0x1U)
13082 #define CSL_DSS_VP4_CONTROL_DATALINES_VAL_OALSB18B (0x2U)
13083 #define CSL_DSS_VP4_CONTROL_DATALINES_VAL_OALSB24B (0x3U)
13084 #define CSL_DSS_VP4_CONTROL_DATALINES_VAL_OALSB30B (0x4U)
13085 #define CSL_DSS_VP4_CONTROL_DATALINES_VAL_OALSB36B (0x5U)
13086 
13087 #define CSL_DSS_VP4_CONTROL_STALLMODE_MASK (0x00000800U)
13088 #define CSL_DSS_VP4_CONTROL_STALLMODE_SHIFT (0x0000000BU)
13089 #define CSL_DSS_VP4_CONTROL_STALLMODE_MAX (0x00000001U)
13090 
13091 #define CSL_DSS_VP4_CONTROL_STALLMODE_VAL_STALLDIS (0x0U)
13092 #define CSL_DSS_VP4_CONTROL_STALLMODE_VAL_STALLENB (0x1U)
13093 
13094 #define CSL_DSS_VP4_CONTROL_STALLMODETYPE_MASK (0x00001000U)
13095 #define CSL_DSS_VP4_CONTROL_STALLMODETYPE_SHIFT (0x0000000CU)
13096 #define CSL_DSS_VP4_CONTROL_STALLMODETYPE_MAX (0x00000001U)
13097 
13098 #define CSL_DSS_VP4_CONTROL_STALLMODETYPE_VAL_COMMANDMODE (0x0U)
13099 #define CSL_DSS_VP4_CONTROL_STALLMODETYPE_VAL_VIDEOMODE (0x1U)
13100 
13101 #define CSL_DSS_VP4_CONTROL_RESERVED3_MASK (0x00002000U)
13102 #define CSL_DSS_VP4_CONTROL_RESERVED3_SHIFT (0x0000000DU)
13103 #define CSL_DSS_VP4_CONTROL_RESERVED3_MAX (0x00000001U)
13104 
13105 #define CSL_DSS_VP4_CONTROL_HT_MASK (0x0001C000U)
13106 #define CSL_DSS_VP4_CONTROL_HT_SHIFT (0x0000000EU)
13107 #define CSL_DSS_VP4_CONTROL_HT_MAX (0x00000007U)
13108 
13109 #define CSL_DSS_VP4_CONTROL_RESERVED1_MASK (0x000E0000U)
13110 #define CSL_DSS_VP4_CONTROL_RESERVED1_SHIFT (0x00000011U)
13111 #define CSL_DSS_VP4_CONTROL_RESERVED1_MAX (0x00000007U)
13112 
13113 #define CSL_DSS_VP4_CONTROL_TDMENABLE_MASK (0x00100000U)
13114 #define CSL_DSS_VP4_CONTROL_TDMENABLE_SHIFT (0x00000014U)
13115 #define CSL_DSS_VP4_CONTROL_TDMENABLE_MAX (0x00000001U)
13116 
13117 #define CSL_DSS_VP4_CONTROL_TDMENABLE_VAL_TDMDIS (0x0U)
13118 #define CSL_DSS_VP4_CONTROL_TDMENABLE_VAL_TDMENB (0x1U)
13119 
13120 #define CSL_DSS_VP4_CONTROL_TDMPARALLELMODE_MASK (0x00600000U)
13121 #define CSL_DSS_VP4_CONTROL_TDMPARALLELMODE_SHIFT (0x00000015U)
13122 #define CSL_DSS_VP4_CONTROL_TDMPARALLELMODE_MAX (0x00000003U)
13123 
13124 #define CSL_DSS_VP4_CONTROL_TDMPARALLELMODE_VAL_8BPARAINT (0x0U)
13125 #define CSL_DSS_VP4_CONTROL_TDMPARALLELMODE_VAL_9BPARAINT (0x1U)
13126 #define CSL_DSS_VP4_CONTROL_TDMPARALLELMODE_VAL_12BPARAINT (0x2U)
13127 #define CSL_DSS_VP4_CONTROL_TDMPARALLELMODE_VAL_16BPARAINT (0x3U)
13128 
13129 #define CSL_DSS_VP4_CONTROL_TDMCYCLEFORMAT_MASK (0x01800000U)
13130 #define CSL_DSS_VP4_CONTROL_TDMCYCLEFORMAT_SHIFT (0x00000017U)
13131 #define CSL_DSS_VP4_CONTROL_TDMCYCLEFORMAT_MAX (0x00000003U)
13132 
13133 #define CSL_DSS_VP4_CONTROL_TDMCYCLEFORMAT_VAL_1CYCPERPIX (0x0U)
13134 #define CSL_DSS_VP4_CONTROL_TDMCYCLEFORMAT_VAL_2CYCPERPIX (0x1U)
13135 #define CSL_DSS_VP4_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPERPIX (0x2U)
13136 #define CSL_DSS_VP4_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPER2PIX (0x3U)
13137 
13138 #define CSL_DSS_VP4_CONTROL_TDMUNUSEDBITS_MASK (0x06000000U)
13139 #define CSL_DSS_VP4_CONTROL_TDMUNUSEDBITS_SHIFT (0x00000019U)
13140 #define CSL_DSS_VP4_CONTROL_TDMUNUSEDBITS_MAX (0x00000003U)
13141 
13142 #define CSL_DSS_VP4_CONTROL_TDMUNUSEDBITS_VAL_LOWLEVEL (0x0U)
13143 #define CSL_DSS_VP4_CONTROL_TDMUNUSEDBITS_VAL_HIGHLEVEL (0x1U)
13144 #define CSL_DSS_VP4_CONTROL_TDMUNUSEDBITS_VAL_UNCHANGED (0x2U)
13145 #define CSL_DSS_VP4_CONTROL_TDMUNUSEDBITS_VAL_RES (0x3U)
13146 
13147 #define CSL_DSS_VP4_CONTROL_RESERVED_MASK (0x38000000U)
13148 #define CSL_DSS_VP4_CONTROL_RESERVED_SHIFT (0x0000001BU)
13149 #define CSL_DSS_VP4_CONTROL_RESERVED_MAX (0x00000007U)
13150 
13151 #define CSL_DSS_VP4_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_MASK (0xC0000000U)
13152 #define CSL_DSS_VP4_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_SHIFT (0x0000001EU)
13153 #define CSL_DSS_VP4_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_MAX (0x00000003U)
13154 
13155 #define CSL_DSS_VP4_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_ONEFRAME (0x0U)
13156 #define CSL_DSS_VP4_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_TWOFRAMES (0x1U)
13157 #define CSL_DSS_VP4_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_FOURFRAMES (0x2U)
13158 #define CSL_DSS_VP4_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_RESERVED (0x3U)
13159 
13160 /* CSC_COEF0 */
13161 
13162 #define CSL_DSS_VP4_CSC_COEF0_C00_MASK (0x000007FFU)
13163 #define CSL_DSS_VP4_CSC_COEF0_C00_SHIFT (0x00000000U)
13164 #define CSL_DSS_VP4_CSC_COEF0_C00_MAX (0x000007FFU)
13165 
13166 #define CSL_DSS_VP4_CSC_COEF0_RESERVED_53_MASK (0x0000F800U)
13167 #define CSL_DSS_VP4_CSC_COEF0_RESERVED_53_SHIFT (0x0000000BU)
13168 #define CSL_DSS_VP4_CSC_COEF0_RESERVED_53_MAX (0x0000001FU)
13169 
13170 #define CSL_DSS_VP4_CSC_COEF0_C01_MASK (0x07FF0000U)
13171 #define CSL_DSS_VP4_CSC_COEF0_C01_SHIFT (0x00000010U)
13172 #define CSL_DSS_VP4_CSC_COEF0_C01_MAX (0x000007FFU)
13173 
13174 #define CSL_DSS_VP4_CSC_COEF0_RESERVED_52_MASK (0xF8000000U)
13175 #define CSL_DSS_VP4_CSC_COEF0_RESERVED_52_SHIFT (0x0000001BU)
13176 #define CSL_DSS_VP4_CSC_COEF0_RESERVED_52_MAX (0x0000001FU)
13177 
13178 /* CSC_COEF1 */
13179 
13180 #define CSL_DSS_VP4_CSC_COEF1_C02_MASK (0x000007FFU)
13181 #define CSL_DSS_VP4_CSC_COEF1_C02_SHIFT (0x00000000U)
13182 #define CSL_DSS_VP4_CSC_COEF1_C02_MAX (0x000007FFU)
13183 
13184 #define CSL_DSS_VP4_CSC_COEF1_RESERVED_55_MASK (0x0000F800U)
13185 #define CSL_DSS_VP4_CSC_COEF1_RESERVED_55_SHIFT (0x0000000BU)
13186 #define CSL_DSS_VP4_CSC_COEF1_RESERVED_55_MAX (0x0000001FU)
13187 
13188 #define CSL_DSS_VP4_CSC_COEF1_C10_MASK (0x07FF0000U)
13189 #define CSL_DSS_VP4_CSC_COEF1_C10_SHIFT (0x00000010U)
13190 #define CSL_DSS_VP4_CSC_COEF1_C10_MAX (0x000007FFU)
13191 
13192 #define CSL_DSS_VP4_CSC_COEF1_RESERVED_54_MASK (0xF8000000U)
13193 #define CSL_DSS_VP4_CSC_COEF1_RESERVED_54_SHIFT (0x0000001BU)
13194 #define CSL_DSS_VP4_CSC_COEF1_RESERVED_54_MAX (0x0000001FU)
13195 
13196 /* CSC_COEF2 */
13197 
13198 #define CSL_DSS_VP4_CSC_COEF2_C11_MASK (0x000007FFU)
13199 #define CSL_DSS_VP4_CSC_COEF2_C11_SHIFT (0x00000000U)
13200 #define CSL_DSS_VP4_CSC_COEF2_C11_MAX (0x000007FFU)
13201 
13202 #define CSL_DSS_VP4_CSC_COEF2_RESERVED_57_MASK (0x0000F800U)
13203 #define CSL_DSS_VP4_CSC_COEF2_RESERVED_57_SHIFT (0x0000000BU)
13204 #define CSL_DSS_VP4_CSC_COEF2_RESERVED_57_MAX (0x0000001FU)
13205 
13206 #define CSL_DSS_VP4_CSC_COEF2_C12_MASK (0x07FF0000U)
13207 #define CSL_DSS_VP4_CSC_COEF2_C12_SHIFT (0x00000010U)
13208 #define CSL_DSS_VP4_CSC_COEF2_C12_MAX (0x000007FFU)
13209 
13210 #define CSL_DSS_VP4_CSC_COEF2_RESERVED_56_MASK (0xF8000000U)
13211 #define CSL_DSS_VP4_CSC_COEF2_RESERVED_56_SHIFT (0x0000001BU)
13212 #define CSL_DSS_VP4_CSC_COEF2_RESERVED_56_MAX (0x0000001FU)
13213 
13214 /* DATA_CYCLE_0 */
13215 
13216 #define CSL_DSS_VP4_DATA_CYCLE_0_NBBITSPIXEL1_MASK (0x0000001FU)
13217 #define CSL_DSS_VP4_DATA_CYCLE_0_NBBITSPIXEL1_SHIFT (0x00000000U)
13218 #define CSL_DSS_VP4_DATA_CYCLE_0_NBBITSPIXEL1_MAX (0x0000001FU)
13219 
13220 #define CSL_DSS_VP4_DATA_CYCLE_0_RESERVED_4_MASK (0x000000E0U)
13221 #define CSL_DSS_VP4_DATA_CYCLE_0_RESERVED_4_SHIFT (0x00000005U)
13222 #define CSL_DSS_VP4_DATA_CYCLE_0_RESERVED_4_MAX (0x00000007U)
13223 
13224 #define CSL_DSS_VP4_DATA_CYCLE_0_BITALIGNMENTPIXEL1_MASK (0x00000F00U)
13225 #define CSL_DSS_VP4_DATA_CYCLE_0_BITALIGNMENTPIXEL1_SHIFT (0x00000008U)
13226 #define CSL_DSS_VP4_DATA_CYCLE_0_BITALIGNMENTPIXEL1_MAX (0x0000000FU)
13227 
13228 #define CSL_DSS_VP4_DATA_CYCLE_0_RESERVED_3_MASK (0x0000F000U)
13229 #define CSL_DSS_VP4_DATA_CYCLE_0_RESERVED_3_SHIFT (0x0000000CU)
13230 #define CSL_DSS_VP4_DATA_CYCLE_0_RESERVED_3_MAX (0x0000000FU)
13231 
13232 #define CSL_DSS_VP4_DATA_CYCLE_0_NBBITSPIXEL2_MASK (0x001F0000U)
13233 #define CSL_DSS_VP4_DATA_CYCLE_0_NBBITSPIXEL2_SHIFT (0x00000010U)
13234 #define CSL_DSS_VP4_DATA_CYCLE_0_NBBITSPIXEL2_MAX (0x0000001FU)
13235 
13236 #define CSL_DSS_VP4_DATA_CYCLE_0_RESERVED_6_MASK (0x00E00000U)
13237 #define CSL_DSS_VP4_DATA_CYCLE_0_RESERVED_6_SHIFT (0x00000015U)
13238 #define CSL_DSS_VP4_DATA_CYCLE_0_RESERVED_6_MAX (0x00000007U)
13239 
13240 #define CSL_DSS_VP4_DATA_CYCLE_0_BITALIGNMENTPIXEL2_MASK (0x0F000000U)
13241 #define CSL_DSS_VP4_DATA_CYCLE_0_BITALIGNMENTPIXEL2_SHIFT (0x00000018U)
13242 #define CSL_DSS_VP4_DATA_CYCLE_0_BITALIGNMENTPIXEL2_MAX (0x0000000FU)
13243 
13244 #define CSL_DSS_VP4_DATA_CYCLE_0_RESERVED_5_MASK (0xF0000000U)
13245 #define CSL_DSS_VP4_DATA_CYCLE_0_RESERVED_5_SHIFT (0x0000001CU)
13246 #define CSL_DSS_VP4_DATA_CYCLE_0_RESERVED_5_MAX (0x0000000FU)
13247 
13248 /* DATA_CYCLE_1 */
13249 
13250 #define CSL_DSS_VP4_DATA_CYCLE_1_NBBITSPIXEL1_MASK (0x0000001FU)
13251 #define CSL_DSS_VP4_DATA_CYCLE_1_NBBITSPIXEL1_SHIFT (0x00000000U)
13252 #define CSL_DSS_VP4_DATA_CYCLE_1_NBBITSPIXEL1_MAX (0x0000001FU)
13253 
13254 #define CSL_DSS_VP4_DATA_CYCLE_1_RESERVED_4_MASK (0x000000E0U)
13255 #define CSL_DSS_VP4_DATA_CYCLE_1_RESERVED_4_SHIFT (0x00000005U)
13256 #define CSL_DSS_VP4_DATA_CYCLE_1_RESERVED_4_MAX (0x00000007U)
13257 
13258 #define CSL_DSS_VP4_DATA_CYCLE_1_BITALIGNMENTPIXEL1_MASK (0x00000F00U)
13259 #define CSL_DSS_VP4_DATA_CYCLE_1_BITALIGNMENTPIXEL1_SHIFT (0x00000008U)
13260 #define CSL_DSS_VP4_DATA_CYCLE_1_BITALIGNMENTPIXEL1_MAX (0x0000000FU)
13261 
13262 #define CSL_DSS_VP4_DATA_CYCLE_1_RESERVED_3_MASK (0x0000F000U)
13263 #define CSL_DSS_VP4_DATA_CYCLE_1_RESERVED_3_SHIFT (0x0000000CU)
13264 #define CSL_DSS_VP4_DATA_CYCLE_1_RESERVED_3_MAX (0x0000000FU)
13265 
13266 #define CSL_DSS_VP4_DATA_CYCLE_1_NBBITSPIXEL2_MASK (0x001F0000U)
13267 #define CSL_DSS_VP4_DATA_CYCLE_1_NBBITSPIXEL2_SHIFT (0x00000010U)
13268 #define CSL_DSS_VP4_DATA_CYCLE_1_NBBITSPIXEL2_MAX (0x0000001FU)
13269 
13270 #define CSL_DSS_VP4_DATA_CYCLE_1_RESERVED_6_MASK (0x00E00000U)
13271 #define CSL_DSS_VP4_DATA_CYCLE_1_RESERVED_6_SHIFT (0x00000015U)
13272 #define CSL_DSS_VP4_DATA_CYCLE_1_RESERVED_6_MAX (0x00000007U)
13273 
13274 #define CSL_DSS_VP4_DATA_CYCLE_1_BITALIGNMENTPIXEL2_MASK (0x0F000000U)
13275 #define CSL_DSS_VP4_DATA_CYCLE_1_BITALIGNMENTPIXEL2_SHIFT (0x00000018U)
13276 #define CSL_DSS_VP4_DATA_CYCLE_1_BITALIGNMENTPIXEL2_MAX (0x0000000FU)
13277 
13278 #define CSL_DSS_VP4_DATA_CYCLE_1_RESERVED_5_MASK (0xF0000000U)
13279 #define CSL_DSS_VP4_DATA_CYCLE_1_RESERVED_5_SHIFT (0x0000001CU)
13280 #define CSL_DSS_VP4_DATA_CYCLE_1_RESERVED_5_MAX (0x0000000FU)
13281 
13282 /* DATA_CYCLE_2 */
13283 
13284 #define CSL_DSS_VP4_DATA_CYCLE_2_NBBITSPIXEL1_MASK (0x0000001FU)
13285 #define CSL_DSS_VP4_DATA_CYCLE_2_NBBITSPIXEL1_SHIFT (0x00000000U)
13286 #define CSL_DSS_VP4_DATA_CYCLE_2_NBBITSPIXEL1_MAX (0x0000001FU)
13287 
13288 #define CSL_DSS_VP4_DATA_CYCLE_2_RESERVED_4_MASK (0x000000E0U)
13289 #define CSL_DSS_VP4_DATA_CYCLE_2_RESERVED_4_SHIFT (0x00000005U)
13290 #define CSL_DSS_VP4_DATA_CYCLE_2_RESERVED_4_MAX (0x00000007U)
13291 
13292 #define CSL_DSS_VP4_DATA_CYCLE_2_BITALIGNMENTPIXEL1_MASK (0x00000F00U)
13293 #define CSL_DSS_VP4_DATA_CYCLE_2_BITALIGNMENTPIXEL1_SHIFT (0x00000008U)
13294 #define CSL_DSS_VP4_DATA_CYCLE_2_BITALIGNMENTPIXEL1_MAX (0x0000000FU)
13295 
13296 #define CSL_DSS_VP4_DATA_CYCLE_2_RESERVED_3_MASK (0x0000F000U)
13297 #define CSL_DSS_VP4_DATA_CYCLE_2_RESERVED_3_SHIFT (0x0000000CU)
13298 #define CSL_DSS_VP4_DATA_CYCLE_2_RESERVED_3_MAX (0x0000000FU)
13299 
13300 #define CSL_DSS_VP4_DATA_CYCLE_2_NBBITSPIXEL2_MASK (0x001F0000U)
13301 #define CSL_DSS_VP4_DATA_CYCLE_2_NBBITSPIXEL2_SHIFT (0x00000010U)
13302 #define CSL_DSS_VP4_DATA_CYCLE_2_NBBITSPIXEL2_MAX (0x0000001FU)
13303 
13304 #define CSL_DSS_VP4_DATA_CYCLE_2_RESERVED_6_MASK (0x00E00000U)
13305 #define CSL_DSS_VP4_DATA_CYCLE_2_RESERVED_6_SHIFT (0x00000015U)
13306 #define CSL_DSS_VP4_DATA_CYCLE_2_RESERVED_6_MAX (0x00000007U)
13307 
13308 #define CSL_DSS_VP4_DATA_CYCLE_2_BITALIGNMENTPIXEL2_MASK (0x0F000000U)
13309 #define CSL_DSS_VP4_DATA_CYCLE_2_BITALIGNMENTPIXEL2_SHIFT (0x00000018U)
13310 #define CSL_DSS_VP4_DATA_CYCLE_2_BITALIGNMENTPIXEL2_MAX (0x0000000FU)
13311 
13312 #define CSL_DSS_VP4_DATA_CYCLE_2_RESERVED_5_MASK (0xF0000000U)
13313 #define CSL_DSS_VP4_DATA_CYCLE_2_RESERVED_5_SHIFT (0x0000001CU)
13314 #define CSL_DSS_VP4_DATA_CYCLE_2_RESERVED_5_MAX (0x0000000FU)
13315 
13316 /* LINE_NUMBER */
13317 
13318 #define CSL_DSS_VP4_LINE_NUMBER_LINENUMBER_MASK (0x00003FFFU)
13319 #define CSL_DSS_VP4_LINE_NUMBER_LINENUMBER_SHIFT (0x00000000U)
13320 #define CSL_DSS_VP4_LINE_NUMBER_LINENUMBER_MAX (0x00003FFFU)
13321 
13322 #define CSL_DSS_VP4_LINE_NUMBER_RESERVED_MASK (0xFFFFC000U)
13323 #define CSL_DSS_VP4_LINE_NUMBER_RESERVED_SHIFT (0x0000000EU)
13324 #define CSL_DSS_VP4_LINE_NUMBER_RESERVED_MAX (0x0003FFFFU)
13325 
13326 /* POL_FREQ */
13327 
13328 #define CSL_DSS_VP4_POL_FREQ_ACB_MASK (0x000000FFU)
13329 #define CSL_DSS_VP4_POL_FREQ_ACB_SHIFT (0x00000000U)
13330 #define CSL_DSS_VP4_POL_FREQ_ACB_MAX (0x000000FFU)
13331 
13332 #define CSL_DSS_VP4_POL_FREQ_ACBI_MASK (0x00000F00U)
13333 #define CSL_DSS_VP4_POL_FREQ_ACBI_SHIFT (0x00000008U)
13334 #define CSL_DSS_VP4_POL_FREQ_ACBI_MAX (0x0000000FU)
13335 
13336 #define CSL_DSS_VP4_POL_FREQ_IVS_MASK (0x00001000U)
13337 #define CSL_DSS_VP4_POL_FREQ_IVS_SHIFT (0x0000000CU)
13338 #define CSL_DSS_VP4_POL_FREQ_IVS_MAX (0x00000001U)
13339 
13340 #define CSL_DSS_VP4_POL_FREQ_IVS_VAL_FCKPINAH (0x0U)
13341 #define CSL_DSS_VP4_POL_FREQ_IVS_VAL_FCKPINAL (0x1U)
13342 
13343 #define CSL_DSS_VP4_POL_FREQ_IHS_MASK (0x00002000U)
13344 #define CSL_DSS_VP4_POL_FREQ_IHS_SHIFT (0x0000000DU)
13345 #define CSL_DSS_VP4_POL_FREQ_IHS_MAX (0x00000001U)
13346 
13347 #define CSL_DSS_VP4_POL_FREQ_IHS_VAL_LCKPINAH (0x0U)
13348 #define CSL_DSS_VP4_POL_FREQ_IHS_VAL_LCKPINAL (0x1U)
13349 
13350 #define CSL_DSS_VP4_POL_FREQ_IPC_MASK (0x00004000U)
13351 #define CSL_DSS_VP4_POL_FREQ_IPC_SHIFT (0x0000000EU)
13352 #define CSL_DSS_VP4_POL_FREQ_IPC_MAX (0x00000001U)
13353 
13354 #define CSL_DSS_VP4_POL_FREQ_IPC_VAL_DRPCK (0x0U)
13355 #define CSL_DSS_VP4_POL_FREQ_IPC_VAL_DFPCK (0x1U)
13356 
13357 #define CSL_DSS_VP4_POL_FREQ_IEO_MASK (0x00008000U)
13358 #define CSL_DSS_VP4_POL_FREQ_IEO_SHIFT (0x0000000FU)
13359 #define CSL_DSS_VP4_POL_FREQ_IEO_MAX (0x00000001U)
13360 
13361 #define CSL_DSS_VP4_POL_FREQ_IEO_VAL_ACBAHIGH (0x0U)
13362 #define CSL_DSS_VP4_POL_FREQ_IEO_VAL_ACBALOW (0x1U)
13363 
13364 #define CSL_DSS_VP4_POL_FREQ_RF_MASK (0x00010000U)
13365 #define CSL_DSS_VP4_POL_FREQ_RF_SHIFT (0x00000010U)
13366 #define CSL_DSS_VP4_POL_FREQ_RF_MAX (0x00000001U)
13367 
13368 #define CSL_DSS_VP4_POL_FREQ_RF_VAL_DFEDPCK (0x0U)
13369 #define CSL_DSS_VP4_POL_FREQ_RF_VAL_DRIEDPCK (0x1U)
13370 
13371 #define CSL_DSS_VP4_POL_FREQ_ONOFF_MASK (0x00020000U)
13372 #define CSL_DSS_VP4_POL_FREQ_ONOFF_SHIFT (0x00000011U)
13373 #define CSL_DSS_VP4_POL_FREQ_ONOFF_MAX (0x00000001U)
13374 
13375 #define CSL_DSS_VP4_POL_FREQ_ONOFF_VAL_DOPEDPCK (0x0U)
13376 #define CSL_DSS_VP4_POL_FREQ_ONOFF_VAL_DBIT16 (0x1U)
13377 
13378 #define CSL_DSS_VP4_POL_FREQ_ALIGN_MASK (0x00040000U)
13379 #define CSL_DSS_VP4_POL_FREQ_ALIGN_SHIFT (0x00000012U)
13380 #define CSL_DSS_VP4_POL_FREQ_ALIGN_MAX (0x00000001U)
13381 
13382 #define CSL_DSS_VP4_POL_FREQ_ALIGN_VAL_NOTALIGNED (0x0U)
13383 #define CSL_DSS_VP4_POL_FREQ_ALIGN_VAL_ALIGNED (0x1U)
13384 
13385 #define CSL_DSS_VP4_POL_FREQ_RESERVED_MASK (0xFFF80000U)
13386 #define CSL_DSS_VP4_POL_FREQ_RESERVED_SHIFT (0x00000013U)
13387 #define CSL_DSS_VP4_POL_FREQ_RESERVED_MAX (0x00001FFFU)
13388 
13389 /* SIZE_SCREEN */
13390 
13391 #define CSL_DSS_VP4_SIZE_SCREEN_PPL_MASK (0x00003FFFU)
13392 #define CSL_DSS_VP4_SIZE_SCREEN_PPL_SHIFT (0x00000000U)
13393 #define CSL_DSS_VP4_SIZE_SCREEN_PPL_MAX (0x00003FFFU)
13394 
13395 #define CSL_DSS_VP4_SIZE_SCREEN_DELTA_LPP_MASK (0x0000C000U)
13396 #define CSL_DSS_VP4_SIZE_SCREEN_DELTA_LPP_SHIFT (0x0000000EU)
13397 #define CSL_DSS_VP4_SIZE_SCREEN_DELTA_LPP_MAX (0x00000003U)
13398 
13399 #define CSL_DSS_VP4_SIZE_SCREEN_DELTA_LPP_VAL_SAME (0x0U)
13400 #define CSL_DSS_VP4_SIZE_SCREEN_DELTA_LPP_VAL_PLUSONE (0x1U)
13401 #define CSL_DSS_VP4_SIZE_SCREEN_DELTA_LPP_VAL_MINUSONE (0x2U)
13402 
13403 #define CSL_DSS_VP4_SIZE_SCREEN_LPP_MASK (0x3FFF0000U)
13404 #define CSL_DSS_VP4_SIZE_SCREEN_LPP_SHIFT (0x00000010U)
13405 #define CSL_DSS_VP4_SIZE_SCREEN_LPP_MAX (0x00003FFFU)
13406 
13407 /* TIMING_H */
13408 
13409 #define CSL_DSS_VP4_TIMING_H_HSW_MASK (0x000000FFU)
13410 #define CSL_DSS_VP4_TIMING_H_HSW_SHIFT (0x00000000U)
13411 #define CSL_DSS_VP4_TIMING_H_HSW_MAX (0x000000FFU)
13412 
13413 #define CSL_DSS_VP4_TIMING_H_HFP_MASK (0x000FFF00U)
13414 #define CSL_DSS_VP4_TIMING_H_HFP_SHIFT (0x00000008U)
13415 #define CSL_DSS_VP4_TIMING_H_HFP_MAX (0x00000FFFU)
13416 
13417 #define CSL_DSS_VP4_TIMING_H_HBP_MASK (0xFFF00000U)
13418 #define CSL_DSS_VP4_TIMING_H_HBP_SHIFT (0x00000014U)
13419 #define CSL_DSS_VP4_TIMING_H_HBP_MAX (0x00000FFFU)
13420 
13421 /* TIMING_V */
13422 
13423 #define CSL_DSS_VP4_TIMING_V_VSW_MASK (0x000000FFU)
13424 #define CSL_DSS_VP4_TIMING_V_VSW_SHIFT (0x00000000U)
13425 #define CSL_DSS_VP4_TIMING_V_VSW_MAX (0x000000FFU)
13426 
13427 #define CSL_DSS_VP4_TIMING_V_VFP_MASK (0x000FFF00U)
13428 #define CSL_DSS_VP4_TIMING_V_VFP_SHIFT (0x00000008U)
13429 #define CSL_DSS_VP4_TIMING_V_VFP_MAX (0x00000FFFU)
13430 
13431 #define CSL_DSS_VP4_TIMING_V_VBP_MASK (0xFFF00000U)
13432 #define CSL_DSS_VP4_TIMING_V_VBP_SHIFT (0x00000014U)
13433 #define CSL_DSS_VP4_TIMING_V_VBP_MAX (0x00000FFFU)
13434 
13435 /* CSC_COEF3 */
13436 
13437 #define CSL_DSS_VP4_CSC_COEF3_C20_MASK (0x000007FFU)
13438 #define CSL_DSS_VP4_CSC_COEF3_C20_SHIFT (0x00000000U)
13439 #define CSL_DSS_VP4_CSC_COEF3_C20_MAX (0x000007FFU)
13440 
13441 #define CSL_DSS_VP4_CSC_COEF3_RESERVED_59_MASK (0x0000F800U)
13442 #define CSL_DSS_VP4_CSC_COEF3_RESERVED_59_SHIFT (0x0000000BU)
13443 #define CSL_DSS_VP4_CSC_COEF3_RESERVED_59_MAX (0x0000001FU)
13444 
13445 #define CSL_DSS_VP4_CSC_COEF3_C21_MASK (0x07FF0000U)
13446 #define CSL_DSS_VP4_CSC_COEF3_C21_SHIFT (0x00000010U)
13447 #define CSL_DSS_VP4_CSC_COEF3_C21_MAX (0x000007FFU)
13448 
13449 #define CSL_DSS_VP4_CSC_COEF3_RESERVED_58_MASK (0xF8000000U)
13450 #define CSL_DSS_VP4_CSC_COEF3_RESERVED_58_SHIFT (0x0000001BU)
13451 #define CSL_DSS_VP4_CSC_COEF3_RESERVED_58_MAX (0x0000001FU)
13452 
13453 /* CSC_COEF4 */
13454 
13455 #define CSL_DSS_VP4_CSC_COEF4_C22_MASK (0x000007FFU)
13456 #define CSL_DSS_VP4_CSC_COEF4_C22_SHIFT (0x00000000U)
13457 #define CSL_DSS_VP4_CSC_COEF4_C22_MAX (0x000007FFU)
13458 
13459 #define CSL_DSS_VP4_CSC_COEF4_RESERVED_60_MASK (0xFFFFF800U)
13460 #define CSL_DSS_VP4_CSC_COEF4_RESERVED_60_SHIFT (0x0000000BU)
13461 #define CSL_DSS_VP4_CSC_COEF4_RESERVED_60_MAX (0x001FFFFFU)
13462 
13463 /* CSC_COEF5 */
13464 
13465 #define CSL_DSS_VP4_CSC_COEF5_RESERVED_MASK (0x00000007U)
13466 #define CSL_DSS_VP4_CSC_COEF5_RESERVED_SHIFT (0x00000000U)
13467 #define CSL_DSS_VP4_CSC_COEF5_RESERVED_MAX (0x00000007U)
13468 
13469 #define CSL_DSS_VP4_CSC_COEF5_PREOFFSET1_MASK (0x0000FFF8U)
13470 #define CSL_DSS_VP4_CSC_COEF5_PREOFFSET1_SHIFT (0x00000003U)
13471 #define CSL_DSS_VP4_CSC_COEF5_PREOFFSET1_MAX (0x00001FFFU)
13472 
13473 #define CSL_DSS_VP4_CSC_COEF5_RESERVED1_MASK (0x00070000U)
13474 #define CSL_DSS_VP4_CSC_COEF5_RESERVED1_SHIFT (0x00000010U)
13475 #define CSL_DSS_VP4_CSC_COEF5_RESERVED1_MAX (0x00000007U)
13476 
13477 #define CSL_DSS_VP4_CSC_COEF5_PREOFFSET2_MASK (0xFFF80000U)
13478 #define CSL_DSS_VP4_CSC_COEF5_PREOFFSET2_SHIFT (0x00000013U)
13479 #define CSL_DSS_VP4_CSC_COEF5_PREOFFSET2_MAX (0x00001FFFU)
13480 
13481 /* CSC_COEF6 */
13482 
13483 #define CSL_DSS_VP4_CSC_COEF6_RESERVED_MASK (0x00000007U)
13484 #define CSL_DSS_VP4_CSC_COEF6_RESERVED_SHIFT (0x00000000U)
13485 #define CSL_DSS_VP4_CSC_COEF6_RESERVED_MAX (0x00000007U)
13486 
13487 #define CSL_DSS_VP4_CSC_COEF6_PREOFFSET3_MASK (0x0000FFF8U)
13488 #define CSL_DSS_VP4_CSC_COEF6_PREOFFSET3_SHIFT (0x00000003U)
13489 #define CSL_DSS_VP4_CSC_COEF6_PREOFFSET3_MAX (0x00001FFFU)
13490 
13491 #define CSL_DSS_VP4_CSC_COEF6_RESERVED1_MASK (0x00070000U)
13492 #define CSL_DSS_VP4_CSC_COEF6_RESERVED1_SHIFT (0x00000010U)
13493 #define CSL_DSS_VP4_CSC_COEF6_RESERVED1_MAX (0x00000007U)
13494 
13495 #define CSL_DSS_VP4_CSC_COEF6_POSTOFFSET1_MASK (0xFFF80000U)
13496 #define CSL_DSS_VP4_CSC_COEF6_POSTOFFSET1_SHIFT (0x00000013U)
13497 #define CSL_DSS_VP4_CSC_COEF6_POSTOFFSET1_MAX (0x00001FFFU)
13498 
13499 /* CSC_COEF7 */
13500 
13501 #define CSL_DSS_VP4_CSC_COEF7_RESERVED_MASK (0x00000007U)
13502 #define CSL_DSS_VP4_CSC_COEF7_RESERVED_SHIFT (0x00000000U)
13503 #define CSL_DSS_VP4_CSC_COEF7_RESERVED_MAX (0x00000007U)
13504 
13505 #define CSL_DSS_VP4_CSC_COEF7_POSTOFFSET2_MASK (0x0000FFF8U)
13506 #define CSL_DSS_VP4_CSC_COEF7_POSTOFFSET2_SHIFT (0x00000003U)
13507 #define CSL_DSS_VP4_CSC_COEF7_POSTOFFSET2_MAX (0x00001FFFU)
13508 
13509 #define CSL_DSS_VP4_CSC_COEF7_RESERVED1_MASK (0x00070000U)
13510 #define CSL_DSS_VP4_CSC_COEF7_RESERVED1_SHIFT (0x00000010U)
13511 #define CSL_DSS_VP4_CSC_COEF7_RESERVED1_MAX (0x00000007U)
13512 
13513 #define CSL_DSS_VP4_CSC_COEF7_POSTOFFSET3_MASK (0xFFF80000U)
13514 #define CSL_DSS_VP4_CSC_COEF7_POSTOFFSET3_SHIFT (0x00000013U)
13515 #define CSL_DSS_VP4_CSC_COEF7_POSTOFFSET3_MAX (0x00001FFFU)
13516 
13517 /* SAFETY_ATTRIBUTES */
13518 
13519 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_ENABLE_MASK (0x00000001U)
13520 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
13521 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_ENABLE_MAX (0x00000001U)
13522 
13523 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_CAPTUREMODE_MASK (0x00000002U)
13524 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_CAPTUREMODE_SHIFT (0x00000001U)
13525 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_CAPTUREMODE_MAX (0x00000001U)
13526 
13527 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_FRAMEFREEZE (0x0U)
13528 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_DATACHECK (0x1U)
13529 
13530 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_SEEDSELECT_MASK (0x00000004U)
13531 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_SEEDSELECT_SHIFT (0x00000002U)
13532 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_SEEDSELECT_MAX (0x00000001U)
13533 
13534 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_DISABLE (0x0U)
13535 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_ENABLE (0x1U)
13536 
13537 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_THRESHOLD_MASK (0x000007F8U)
13538 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_THRESHOLD_SHIFT (0x00000003U)
13539 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_THRESHOLD_MAX (0x000000FFU)
13540 
13541 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_FRAMESKIP_MASK (0x00001800U)
13542 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_FRAMESKIP_SHIFT (0x0000000BU)
13543 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_FRAMESKIP_MAX (0x00000003U)
13544 
13545 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_NOSKIP (0x0U)
13546 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_EVEN (0x1U)
13547 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_ODD (0x2U)
13548 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_RESERVED (0x3U)
13549 
13550 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_RESERVED_MASK (0xFFFFE000U)
13551 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_RESERVED_SHIFT (0x0000000DU)
13552 #define CSL_DSS_VP4_SAFETY_ATTRIBUTES_RESERVED_MAX (0x0007FFFFU)
13553 
13554 /* SAFETY_CAPT_SIGNATURE */
13555 
13556 #define CSL_DSS_VP4_SAFETY_CAPT_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
13557 #define CSL_DSS_VP4_SAFETY_CAPT_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
13558 #define CSL_DSS_VP4_SAFETY_CAPT_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
13559 
13560 /* SAFETY_POSITION */
13561 
13562 #define CSL_DSS_VP4_SAFETY_POSITION_POSX_MASK (0x00003FFFU)
13563 #define CSL_DSS_VP4_SAFETY_POSITION_POSX_SHIFT (0x00000000U)
13564 #define CSL_DSS_VP4_SAFETY_POSITION_POSX_MAX (0x00003FFFU)
13565 
13566 #define CSL_DSS_VP4_SAFETY_POSITION_POSY_MASK (0x3FFF0000U)
13567 #define CSL_DSS_VP4_SAFETY_POSITION_POSY_SHIFT (0x00000010U)
13568 #define CSL_DSS_VP4_SAFETY_POSITION_POSY_MAX (0x00003FFFU)
13569 
13570 /* SAFETY_REF_SIGNATURE */
13571 
13572 #define CSL_DSS_VP4_SAFETY_REF_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
13573 #define CSL_DSS_VP4_SAFETY_REF_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
13574 #define CSL_DSS_VP4_SAFETY_REF_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
13575 
13576 /* SAFETY_SIZE */
13577 
13578 #define CSL_DSS_VP4_SAFETY_SIZE_SIZEX_MASK (0x00003FFFU)
13579 #define CSL_DSS_VP4_SAFETY_SIZE_SIZEX_SHIFT (0x00000000U)
13580 #define CSL_DSS_VP4_SAFETY_SIZE_SIZEX_MAX (0x00003FFFU)
13581 
13582 #define CSL_DSS_VP4_SAFETY_SIZE_SIZEY_MASK (0x3FFF0000U)
13583 #define CSL_DSS_VP4_SAFETY_SIZE_SIZEY_SHIFT (0x00000010U)
13584 #define CSL_DSS_VP4_SAFETY_SIZE_SIZEY_MAX (0x00003FFFU)
13585 
13586 /* SAFETY_LFSR_SEED */
13587 
13588 #define CSL_DSS_VP4_SAFETY_LFSR_SEED_SEED_MASK (0xFFFFFFFFU)
13589 #define CSL_DSS_VP4_SAFETY_LFSR_SEED_SEED_SHIFT (0x00000000U)
13590 #define CSL_DSS_VP4_SAFETY_LFSR_SEED_SEED_MAX (0xFFFFFFFFU)
13591 
13592 /* GAMMA_TABLE_0 */
13593 
13594 #define CSL_DSS_VP4_GAMMA_TABLE_0_VALUE_B_MASK (0x000003FFU)
13595 #define CSL_DSS_VP4_GAMMA_TABLE_0_VALUE_B_SHIFT (0x00000000U)
13596 #define CSL_DSS_VP4_GAMMA_TABLE_0_VALUE_B_MAX (0x000003FFU)
13597 
13598 #define CSL_DSS_VP4_GAMMA_TABLE_0_VALUE_G_MASK (0x000FFC00U)
13599 #define CSL_DSS_VP4_GAMMA_TABLE_0_VALUE_G_SHIFT (0x0000000AU)
13600 #define CSL_DSS_VP4_GAMMA_TABLE_0_VALUE_G_MAX (0x000003FFU)
13601 
13602 #define CSL_DSS_VP4_GAMMA_TABLE_0_VALUE_R_MASK (0x3FF00000U)
13603 #define CSL_DSS_VP4_GAMMA_TABLE_0_VALUE_R_SHIFT (0x00000014U)
13604 #define CSL_DSS_VP4_GAMMA_TABLE_0_VALUE_R_MAX (0x000003FFU)
13605 
13606 #define CSL_DSS_VP4_GAMMA_TABLE_0_INDEX_MASK (0x80000000U)
13607 #define CSL_DSS_VP4_GAMMA_TABLE_0_INDEX_SHIFT (0x0000001FU)
13608 #define CSL_DSS_VP4_GAMMA_TABLE_0_INDEX_MAX (0x00000001U)
13609 
13610 /* GAMMA_TABLE_1 */
13611 
13612 #define CSL_DSS_VP4_GAMMA_TABLE_1_VALUE_B_MASK (0x000003FFU)
13613 #define CSL_DSS_VP4_GAMMA_TABLE_1_VALUE_B_SHIFT (0x00000000U)
13614 #define CSL_DSS_VP4_GAMMA_TABLE_1_VALUE_B_MAX (0x000003FFU)
13615 
13616 #define CSL_DSS_VP4_GAMMA_TABLE_1_VALUE_G_MASK (0x000FFC00U)
13617 #define CSL_DSS_VP4_GAMMA_TABLE_1_VALUE_G_SHIFT (0x0000000AU)
13618 #define CSL_DSS_VP4_GAMMA_TABLE_1_VALUE_G_MAX (0x000003FFU)
13619 
13620 #define CSL_DSS_VP4_GAMMA_TABLE_1_VALUE_R_MASK (0x3FF00000U)
13621 #define CSL_DSS_VP4_GAMMA_TABLE_1_VALUE_R_SHIFT (0x00000014U)
13622 #define CSL_DSS_VP4_GAMMA_TABLE_1_VALUE_R_MAX (0x000003FFU)
13623 
13624 #define CSL_DSS_VP4_GAMMA_TABLE_1_INDEX_MASK (0x80000000U)
13625 #define CSL_DSS_VP4_GAMMA_TABLE_1_INDEX_SHIFT (0x0000001FU)
13626 #define CSL_DSS_VP4_GAMMA_TABLE_1_INDEX_MAX (0x00000001U)
13627 
13628 /* GAMMA_TABLE_2 */
13629 
13630 #define CSL_DSS_VP4_GAMMA_TABLE_2_VALUE_B_MASK (0x000003FFU)
13631 #define CSL_DSS_VP4_GAMMA_TABLE_2_VALUE_B_SHIFT (0x00000000U)
13632 #define CSL_DSS_VP4_GAMMA_TABLE_2_VALUE_B_MAX (0x000003FFU)
13633 
13634 #define CSL_DSS_VP4_GAMMA_TABLE_2_VALUE_G_MASK (0x000FFC00U)
13635 #define CSL_DSS_VP4_GAMMA_TABLE_2_VALUE_G_SHIFT (0x0000000AU)
13636 #define CSL_DSS_VP4_GAMMA_TABLE_2_VALUE_G_MAX (0x000003FFU)
13637 
13638 #define CSL_DSS_VP4_GAMMA_TABLE_2_VALUE_R_MASK (0x3FF00000U)
13639 #define CSL_DSS_VP4_GAMMA_TABLE_2_VALUE_R_SHIFT (0x00000014U)
13640 #define CSL_DSS_VP4_GAMMA_TABLE_2_VALUE_R_MAX (0x000003FFU)
13641 
13642 #define CSL_DSS_VP4_GAMMA_TABLE_2_INDEX_MASK (0x80000000U)
13643 #define CSL_DSS_VP4_GAMMA_TABLE_2_INDEX_SHIFT (0x0000001FU)
13644 #define CSL_DSS_VP4_GAMMA_TABLE_2_INDEX_MAX (0x00000001U)
13645 
13646 /* GAMMA_TABLE_3 */
13647 
13648 #define CSL_DSS_VP4_GAMMA_TABLE_3_VALUE_B_MASK (0x000003FFU)
13649 #define CSL_DSS_VP4_GAMMA_TABLE_3_VALUE_B_SHIFT (0x00000000U)
13650 #define CSL_DSS_VP4_GAMMA_TABLE_3_VALUE_B_MAX (0x000003FFU)
13651 
13652 #define CSL_DSS_VP4_GAMMA_TABLE_3_VALUE_G_MASK (0x000FFC00U)
13653 #define CSL_DSS_VP4_GAMMA_TABLE_3_VALUE_G_SHIFT (0x0000000AU)
13654 #define CSL_DSS_VP4_GAMMA_TABLE_3_VALUE_G_MAX (0x000003FFU)
13655 
13656 #define CSL_DSS_VP4_GAMMA_TABLE_3_VALUE_R_MASK (0x3FF00000U)
13657 #define CSL_DSS_VP4_GAMMA_TABLE_3_VALUE_R_SHIFT (0x00000014U)
13658 #define CSL_DSS_VP4_GAMMA_TABLE_3_VALUE_R_MAX (0x000003FFU)
13659 
13660 #define CSL_DSS_VP4_GAMMA_TABLE_3_INDEX_MASK (0x80000000U)
13661 #define CSL_DSS_VP4_GAMMA_TABLE_3_INDEX_SHIFT (0x0000001FU)
13662 #define CSL_DSS_VP4_GAMMA_TABLE_3_INDEX_MAX (0x00000001U)
13663 
13664 /* GAMMA_TABLE_4 */
13665 
13666 #define CSL_DSS_VP4_GAMMA_TABLE_4_VALUE_B_MASK (0x000003FFU)
13667 #define CSL_DSS_VP4_GAMMA_TABLE_4_VALUE_B_SHIFT (0x00000000U)
13668 #define CSL_DSS_VP4_GAMMA_TABLE_4_VALUE_B_MAX (0x000003FFU)
13669 
13670 #define CSL_DSS_VP4_GAMMA_TABLE_4_VALUE_G_MASK (0x000FFC00U)
13671 #define CSL_DSS_VP4_GAMMA_TABLE_4_VALUE_G_SHIFT (0x0000000AU)
13672 #define CSL_DSS_VP4_GAMMA_TABLE_4_VALUE_G_MAX (0x000003FFU)
13673 
13674 #define CSL_DSS_VP4_GAMMA_TABLE_4_VALUE_R_MASK (0x3FF00000U)
13675 #define CSL_DSS_VP4_GAMMA_TABLE_4_VALUE_R_SHIFT (0x00000014U)
13676 #define CSL_DSS_VP4_GAMMA_TABLE_4_VALUE_R_MAX (0x000003FFU)
13677 
13678 #define CSL_DSS_VP4_GAMMA_TABLE_4_INDEX_MASK (0x80000000U)
13679 #define CSL_DSS_VP4_GAMMA_TABLE_4_INDEX_SHIFT (0x0000001FU)
13680 #define CSL_DSS_VP4_GAMMA_TABLE_4_INDEX_MAX (0x00000001U)
13681 
13682 /* GAMMA_TABLE_5 */
13683 
13684 #define CSL_DSS_VP4_GAMMA_TABLE_5_VALUE_B_MASK (0x000003FFU)
13685 #define CSL_DSS_VP4_GAMMA_TABLE_5_VALUE_B_SHIFT (0x00000000U)
13686 #define CSL_DSS_VP4_GAMMA_TABLE_5_VALUE_B_MAX (0x000003FFU)
13687 
13688 #define CSL_DSS_VP4_GAMMA_TABLE_5_VALUE_G_MASK (0x000FFC00U)
13689 #define CSL_DSS_VP4_GAMMA_TABLE_5_VALUE_G_SHIFT (0x0000000AU)
13690 #define CSL_DSS_VP4_GAMMA_TABLE_5_VALUE_G_MAX (0x000003FFU)
13691 
13692 #define CSL_DSS_VP4_GAMMA_TABLE_5_VALUE_R_MASK (0x3FF00000U)
13693 #define CSL_DSS_VP4_GAMMA_TABLE_5_VALUE_R_SHIFT (0x00000014U)
13694 #define CSL_DSS_VP4_GAMMA_TABLE_5_VALUE_R_MAX (0x000003FFU)
13695 
13696 #define CSL_DSS_VP4_GAMMA_TABLE_5_INDEX_MASK (0x80000000U)
13697 #define CSL_DSS_VP4_GAMMA_TABLE_5_INDEX_SHIFT (0x0000001FU)
13698 #define CSL_DSS_VP4_GAMMA_TABLE_5_INDEX_MAX (0x00000001U)
13699 
13700 /* GAMMA_TABLE_6 */
13701 
13702 #define CSL_DSS_VP4_GAMMA_TABLE_6_VALUE_B_MASK (0x000003FFU)
13703 #define CSL_DSS_VP4_GAMMA_TABLE_6_VALUE_B_SHIFT (0x00000000U)
13704 #define CSL_DSS_VP4_GAMMA_TABLE_6_VALUE_B_MAX (0x000003FFU)
13705 
13706 #define CSL_DSS_VP4_GAMMA_TABLE_6_VALUE_G_MASK (0x000FFC00U)
13707 #define CSL_DSS_VP4_GAMMA_TABLE_6_VALUE_G_SHIFT (0x0000000AU)
13708 #define CSL_DSS_VP4_GAMMA_TABLE_6_VALUE_G_MAX (0x000003FFU)
13709 
13710 #define CSL_DSS_VP4_GAMMA_TABLE_6_VALUE_R_MASK (0x3FF00000U)
13711 #define CSL_DSS_VP4_GAMMA_TABLE_6_VALUE_R_SHIFT (0x00000014U)
13712 #define CSL_DSS_VP4_GAMMA_TABLE_6_VALUE_R_MAX (0x000003FFU)
13713 
13714 #define CSL_DSS_VP4_GAMMA_TABLE_6_INDEX_MASK (0x80000000U)
13715 #define CSL_DSS_VP4_GAMMA_TABLE_6_INDEX_SHIFT (0x0000001FU)
13716 #define CSL_DSS_VP4_GAMMA_TABLE_6_INDEX_MAX (0x00000001U)
13717 
13718 /* GAMMA_TABLE_7 */
13719 
13720 #define CSL_DSS_VP4_GAMMA_TABLE_7_VALUE_B_MASK (0x000003FFU)
13721 #define CSL_DSS_VP4_GAMMA_TABLE_7_VALUE_B_SHIFT (0x00000000U)
13722 #define CSL_DSS_VP4_GAMMA_TABLE_7_VALUE_B_MAX (0x000003FFU)
13723 
13724 #define CSL_DSS_VP4_GAMMA_TABLE_7_VALUE_G_MASK (0x000FFC00U)
13725 #define CSL_DSS_VP4_GAMMA_TABLE_7_VALUE_G_SHIFT (0x0000000AU)
13726 #define CSL_DSS_VP4_GAMMA_TABLE_7_VALUE_G_MAX (0x000003FFU)
13727 
13728 #define CSL_DSS_VP4_GAMMA_TABLE_7_VALUE_R_MASK (0x3FF00000U)
13729 #define CSL_DSS_VP4_GAMMA_TABLE_7_VALUE_R_SHIFT (0x00000014U)
13730 #define CSL_DSS_VP4_GAMMA_TABLE_7_VALUE_R_MAX (0x000003FFU)
13731 
13732 #define CSL_DSS_VP4_GAMMA_TABLE_7_INDEX_MASK (0x80000000U)
13733 #define CSL_DSS_VP4_GAMMA_TABLE_7_INDEX_SHIFT (0x0000001FU)
13734 #define CSL_DSS_VP4_GAMMA_TABLE_7_INDEX_MAX (0x00000001U)
13735 
13736 /* GAMMA_TABLE_8 */
13737 
13738 #define CSL_DSS_VP4_GAMMA_TABLE_8_VALUE_B_MASK (0x000003FFU)
13739 #define CSL_DSS_VP4_GAMMA_TABLE_8_VALUE_B_SHIFT (0x00000000U)
13740 #define CSL_DSS_VP4_GAMMA_TABLE_8_VALUE_B_MAX (0x000003FFU)
13741 
13742 #define CSL_DSS_VP4_GAMMA_TABLE_8_VALUE_G_MASK (0x000FFC00U)
13743 #define CSL_DSS_VP4_GAMMA_TABLE_8_VALUE_G_SHIFT (0x0000000AU)
13744 #define CSL_DSS_VP4_GAMMA_TABLE_8_VALUE_G_MAX (0x000003FFU)
13745 
13746 #define CSL_DSS_VP4_GAMMA_TABLE_8_VALUE_R_MASK (0x3FF00000U)
13747 #define CSL_DSS_VP4_GAMMA_TABLE_8_VALUE_R_SHIFT (0x00000014U)
13748 #define CSL_DSS_VP4_GAMMA_TABLE_8_VALUE_R_MAX (0x000003FFU)
13749 
13750 #define CSL_DSS_VP4_GAMMA_TABLE_8_INDEX_MASK (0x80000000U)
13751 #define CSL_DSS_VP4_GAMMA_TABLE_8_INDEX_SHIFT (0x0000001FU)
13752 #define CSL_DSS_VP4_GAMMA_TABLE_8_INDEX_MAX (0x00000001U)
13753 
13754 /* GAMMA_TABLE_9 */
13755 
13756 #define CSL_DSS_VP4_GAMMA_TABLE_9_VALUE_B_MASK (0x000003FFU)
13757 #define CSL_DSS_VP4_GAMMA_TABLE_9_VALUE_B_SHIFT (0x00000000U)
13758 #define CSL_DSS_VP4_GAMMA_TABLE_9_VALUE_B_MAX (0x000003FFU)
13759 
13760 #define CSL_DSS_VP4_GAMMA_TABLE_9_VALUE_G_MASK (0x000FFC00U)
13761 #define CSL_DSS_VP4_GAMMA_TABLE_9_VALUE_G_SHIFT (0x0000000AU)
13762 #define CSL_DSS_VP4_GAMMA_TABLE_9_VALUE_G_MAX (0x000003FFU)
13763 
13764 #define CSL_DSS_VP4_GAMMA_TABLE_9_VALUE_R_MASK (0x3FF00000U)
13765 #define CSL_DSS_VP4_GAMMA_TABLE_9_VALUE_R_SHIFT (0x00000014U)
13766 #define CSL_DSS_VP4_GAMMA_TABLE_9_VALUE_R_MAX (0x000003FFU)
13767 
13768 #define CSL_DSS_VP4_GAMMA_TABLE_9_INDEX_MASK (0x80000000U)
13769 #define CSL_DSS_VP4_GAMMA_TABLE_9_INDEX_SHIFT (0x0000001FU)
13770 #define CSL_DSS_VP4_GAMMA_TABLE_9_INDEX_MAX (0x00000001U)
13771 
13772 /* GAMMA_TABLE_10 */
13773 
13774 #define CSL_DSS_VP4_GAMMA_TABLE_10_VALUE_B_MASK (0x000003FFU)
13775 #define CSL_DSS_VP4_GAMMA_TABLE_10_VALUE_B_SHIFT (0x00000000U)
13776 #define CSL_DSS_VP4_GAMMA_TABLE_10_VALUE_B_MAX (0x000003FFU)
13777 
13778 #define CSL_DSS_VP4_GAMMA_TABLE_10_VALUE_G_MASK (0x000FFC00U)
13779 #define CSL_DSS_VP4_GAMMA_TABLE_10_VALUE_G_SHIFT (0x0000000AU)
13780 #define CSL_DSS_VP4_GAMMA_TABLE_10_VALUE_G_MAX (0x000003FFU)
13781 
13782 #define CSL_DSS_VP4_GAMMA_TABLE_10_VALUE_R_MASK (0x3FF00000U)
13783 #define CSL_DSS_VP4_GAMMA_TABLE_10_VALUE_R_SHIFT (0x00000014U)
13784 #define CSL_DSS_VP4_GAMMA_TABLE_10_VALUE_R_MAX (0x000003FFU)
13785 
13786 #define CSL_DSS_VP4_GAMMA_TABLE_10_INDEX_MASK (0x80000000U)
13787 #define CSL_DSS_VP4_GAMMA_TABLE_10_INDEX_SHIFT (0x0000001FU)
13788 #define CSL_DSS_VP4_GAMMA_TABLE_10_INDEX_MAX (0x00000001U)
13789 
13790 /* GAMMA_TABLE_11 */
13791 
13792 #define CSL_DSS_VP4_GAMMA_TABLE_11_VALUE_B_MASK (0x000003FFU)
13793 #define CSL_DSS_VP4_GAMMA_TABLE_11_VALUE_B_SHIFT (0x00000000U)
13794 #define CSL_DSS_VP4_GAMMA_TABLE_11_VALUE_B_MAX (0x000003FFU)
13795 
13796 #define CSL_DSS_VP4_GAMMA_TABLE_11_VALUE_G_MASK (0x000FFC00U)
13797 #define CSL_DSS_VP4_GAMMA_TABLE_11_VALUE_G_SHIFT (0x0000000AU)
13798 #define CSL_DSS_VP4_GAMMA_TABLE_11_VALUE_G_MAX (0x000003FFU)
13799 
13800 #define CSL_DSS_VP4_GAMMA_TABLE_11_VALUE_R_MASK (0x3FF00000U)
13801 #define CSL_DSS_VP4_GAMMA_TABLE_11_VALUE_R_SHIFT (0x00000014U)
13802 #define CSL_DSS_VP4_GAMMA_TABLE_11_VALUE_R_MAX (0x000003FFU)
13803 
13804 #define CSL_DSS_VP4_GAMMA_TABLE_11_INDEX_MASK (0x80000000U)
13805 #define CSL_DSS_VP4_GAMMA_TABLE_11_INDEX_SHIFT (0x0000001FU)
13806 #define CSL_DSS_VP4_GAMMA_TABLE_11_INDEX_MAX (0x00000001U)
13807 
13808 /* GAMMA_TABLE_12 */
13809 
13810 #define CSL_DSS_VP4_GAMMA_TABLE_12_VALUE_B_MASK (0x000003FFU)
13811 #define CSL_DSS_VP4_GAMMA_TABLE_12_VALUE_B_SHIFT (0x00000000U)
13812 #define CSL_DSS_VP4_GAMMA_TABLE_12_VALUE_B_MAX (0x000003FFU)
13813 
13814 #define CSL_DSS_VP4_GAMMA_TABLE_12_VALUE_G_MASK (0x000FFC00U)
13815 #define CSL_DSS_VP4_GAMMA_TABLE_12_VALUE_G_SHIFT (0x0000000AU)
13816 #define CSL_DSS_VP4_GAMMA_TABLE_12_VALUE_G_MAX (0x000003FFU)
13817 
13818 #define CSL_DSS_VP4_GAMMA_TABLE_12_VALUE_R_MASK (0x3FF00000U)
13819 #define CSL_DSS_VP4_GAMMA_TABLE_12_VALUE_R_SHIFT (0x00000014U)
13820 #define CSL_DSS_VP4_GAMMA_TABLE_12_VALUE_R_MAX (0x000003FFU)
13821 
13822 #define CSL_DSS_VP4_GAMMA_TABLE_12_INDEX_MASK (0x80000000U)
13823 #define CSL_DSS_VP4_GAMMA_TABLE_12_INDEX_SHIFT (0x0000001FU)
13824 #define CSL_DSS_VP4_GAMMA_TABLE_12_INDEX_MAX (0x00000001U)
13825 
13826 /* GAMMA_TABLE_13 */
13827 
13828 #define CSL_DSS_VP4_GAMMA_TABLE_13_VALUE_B_MASK (0x000003FFU)
13829 #define CSL_DSS_VP4_GAMMA_TABLE_13_VALUE_B_SHIFT (0x00000000U)
13830 #define CSL_DSS_VP4_GAMMA_TABLE_13_VALUE_B_MAX (0x000003FFU)
13831 
13832 #define CSL_DSS_VP4_GAMMA_TABLE_13_VALUE_G_MASK (0x000FFC00U)
13833 #define CSL_DSS_VP4_GAMMA_TABLE_13_VALUE_G_SHIFT (0x0000000AU)
13834 #define CSL_DSS_VP4_GAMMA_TABLE_13_VALUE_G_MAX (0x000003FFU)
13835 
13836 #define CSL_DSS_VP4_GAMMA_TABLE_13_VALUE_R_MASK (0x3FF00000U)
13837 #define CSL_DSS_VP4_GAMMA_TABLE_13_VALUE_R_SHIFT (0x00000014U)
13838 #define CSL_DSS_VP4_GAMMA_TABLE_13_VALUE_R_MAX (0x000003FFU)
13839 
13840 #define CSL_DSS_VP4_GAMMA_TABLE_13_INDEX_MASK (0x80000000U)
13841 #define CSL_DSS_VP4_GAMMA_TABLE_13_INDEX_SHIFT (0x0000001FU)
13842 #define CSL_DSS_VP4_GAMMA_TABLE_13_INDEX_MAX (0x00000001U)
13843 
13844 /* GAMMA_TABLE_14 */
13845 
13846 #define CSL_DSS_VP4_GAMMA_TABLE_14_VALUE_B_MASK (0x000003FFU)
13847 #define CSL_DSS_VP4_GAMMA_TABLE_14_VALUE_B_SHIFT (0x00000000U)
13848 #define CSL_DSS_VP4_GAMMA_TABLE_14_VALUE_B_MAX (0x000003FFU)
13849 
13850 #define CSL_DSS_VP4_GAMMA_TABLE_14_VALUE_G_MASK (0x000FFC00U)
13851 #define CSL_DSS_VP4_GAMMA_TABLE_14_VALUE_G_SHIFT (0x0000000AU)
13852 #define CSL_DSS_VP4_GAMMA_TABLE_14_VALUE_G_MAX (0x000003FFU)
13853 
13854 #define CSL_DSS_VP4_GAMMA_TABLE_14_VALUE_R_MASK (0x3FF00000U)
13855 #define CSL_DSS_VP4_GAMMA_TABLE_14_VALUE_R_SHIFT (0x00000014U)
13856 #define CSL_DSS_VP4_GAMMA_TABLE_14_VALUE_R_MAX (0x000003FFU)
13857 
13858 #define CSL_DSS_VP4_GAMMA_TABLE_14_INDEX_MASK (0x80000000U)
13859 #define CSL_DSS_VP4_GAMMA_TABLE_14_INDEX_SHIFT (0x0000001FU)
13860 #define CSL_DSS_VP4_GAMMA_TABLE_14_INDEX_MAX (0x00000001U)
13861 
13862 /* GAMMA_TABLE_15 */
13863 
13864 #define CSL_DSS_VP4_GAMMA_TABLE_15_VALUE_B_MASK (0x000003FFU)
13865 #define CSL_DSS_VP4_GAMMA_TABLE_15_VALUE_B_SHIFT (0x00000000U)
13866 #define CSL_DSS_VP4_GAMMA_TABLE_15_VALUE_B_MAX (0x000003FFU)
13867 
13868 #define CSL_DSS_VP4_GAMMA_TABLE_15_VALUE_G_MASK (0x000FFC00U)
13869 #define CSL_DSS_VP4_GAMMA_TABLE_15_VALUE_G_SHIFT (0x0000000AU)
13870 #define CSL_DSS_VP4_GAMMA_TABLE_15_VALUE_G_MAX (0x000003FFU)
13871 
13872 #define CSL_DSS_VP4_GAMMA_TABLE_15_VALUE_R_MASK (0x3FF00000U)
13873 #define CSL_DSS_VP4_GAMMA_TABLE_15_VALUE_R_SHIFT (0x00000014U)
13874 #define CSL_DSS_VP4_GAMMA_TABLE_15_VALUE_R_MAX (0x000003FFU)
13875 
13876 #define CSL_DSS_VP4_GAMMA_TABLE_15_INDEX_MASK (0x80000000U)
13877 #define CSL_DSS_VP4_GAMMA_TABLE_15_INDEX_SHIFT (0x0000001FU)
13878 #define CSL_DSS_VP4_GAMMA_TABLE_15_INDEX_MAX (0x00000001U)
13879 
13880 /* DSS_OLDI_CFG */
13881 
13882 #define CSL_DSS_VP4_DSS_OLDI_CFG_RESERVED1_MASK (0x00003FFFU)
13883 #define CSL_DSS_VP4_DSS_OLDI_CFG_RESERVED1_SHIFT (0x00000000U)
13884 #define CSL_DSS_VP4_DSS_OLDI_CFG_RESERVED1_MAX (0x00003FFFU)
13885 
13886 #define CSL_DSS_VP4_DSS_OLDI_CFG_RESERVED_MASK (0xFFFFC000U)
13887 #define CSL_DSS_VP4_DSS_OLDI_CFG_RESERVED_SHIFT (0x0000000EU)
13888 #define CSL_DSS_VP4_DSS_OLDI_CFG_RESERVED_MAX (0x0003FFFFU)
13889 
13890 /* DSS_OLDI_STATUS */
13891 
13892 #define CSL_DSS_VP4_DSS_OLDI_STATUS_RESERVED_MASK (0xFFFFFFFFU)
13893 #define CSL_DSS_VP4_DSS_OLDI_STATUS_RESERVED_SHIFT (0x00000000U)
13894 #define CSL_DSS_VP4_DSS_OLDI_STATUS_RESERVED_MAX (0xFFFFFFFFU)
13895 
13896 /* DSS_OLDI_LB */
13897 
13898 #define CSL_DSS_VP4_DSS_OLDI_LB_RESERVED_MASK (0xFFFFFFFFU)
13899 #define CSL_DSS_VP4_DSS_OLDI_LB_RESERVED_SHIFT (0x00000000U)
13900 #define CSL_DSS_VP4_DSS_OLDI_LB_RESERVED_MAX (0xFFFFFFFFU)
13901 
13902 /* SECURE */
13903 
13904 #define CSL_DSS_VP4_SECURE_SECURE_MASK (0x00000001U)
13905 #define CSL_DSS_VP4_SECURE_SECURE_SHIFT (0x00000000U)
13906 #define CSL_DSS_VP4_SECURE_SECURE_MAX (0x00000001U)
13907 
13908 #define CSL_DSS_VP4_SECURE_SECURE_VAL_SECUREDIS (0x0U)
13909 #define CSL_DSS_VP4_SECURE_SECURE_VAL_SECUREEN (0x1U)
13910 
13911 #define CSL_DSS_VP4_SECURE_RESERVED_MASK (0xFFFFFFFEU)
13912 #define CSL_DSS_VP4_SECURE_RESERVED_SHIFT (0x00000001U)
13913 #define CSL_DSS_VP4_SECURE_RESERVED_MAX (0x7FFFFFFFU)
13914 
13915 /**************************************************************************
13916 * Hardware Region : WB Registers
13917 **************************************************************************/
13918 
13919 
13920 /**************************************************************************
13921 * Register Overlay Structure
13922 **************************************************************************/
13923 
13924 typedef struct {
13925  volatile uint32_t ACCUH_0; /* ACCUH_0 */
13926  volatile uint32_t ACCUH_1; /* ACCUH_1 */
13927  volatile uint32_t ACCUH2_0; /* ACCUH2_0 */
13928  volatile uint32_t ACCUH2_1; /* ACCUH2_1 */
13929  volatile uint32_t ACCUV_0; /* ACCUV_0 */
13930  volatile uint32_t ACCUV_1; /* ACCUV_1 */
13931  volatile uint32_t ACCUV2_0; /* ACCUV2_0 */
13932  volatile uint32_t ACCUV2_1; /* ACCUV2_1 */
13933  volatile uint32_t ATTRIBUTES; /* ATTRIBUTES */
13934  volatile uint32_t ATTRIBUTES2; /* ATTRIBUTES2 */
13935  volatile uint32_t BA_0; /* BA_0 */
13936  volatile uint32_t BA_1; /* BA_1 */
13937  volatile uint32_t BA_UV_0; /* BA_UV_0 */
13938  volatile uint32_t BA_UV_1; /* BA_UV_1 */
13939  volatile uint32_t BUF_SIZE_STATUS; /* BUF_SIZE_STATUS */
13940  volatile uint32_t BUF_THRESHOLD; /* BUF_THRESHOLD */
13941  volatile uint32_t CSC_COEF0; /* CSC_COEF0 */
13942  volatile uint32_t CSC_COEF1; /* CSC_COEF1 */
13943  volatile uint32_t CSC_COEF2; /* CSC_COEF2 */
13944  volatile uint32_t CSC_COEF3; /* CSC_COEF3 */
13945  volatile uint32_t CSC_COEF4; /* CSC_COEF4 */
13946  volatile uint32_t CSC_COEF5; /* CSC_COEF5 */
13947  volatile uint32_t CSC_COEF6; /* CSC_COEF6 */
13948  volatile uint32_t FIRH; /* FIRH */
13949  volatile uint32_t FIRH2; /* FIRH2 */
13950  volatile uint32_t FIRV; /* FIRV */
13951  volatile uint32_t FIRV2; /* FIRV2 */
13952  volatile uint32_t FIR_COEF_H0[9U]; /* FIR_COEF_H0 0..8 */
13953  volatile uint32_t FIR_COEF_H0_C[9U]; /* FIR_COEF_H0_C 0..8 */
13954  volatile uint32_t FIR_COEF_H12[16U]; /* FIR_COEF_H12 0..15 */
13955  volatile uint32_t FIR_COEF_H12_C[16U]; /* FIR_COEF_H12_C 0..15 */
13956  volatile uint32_t FIR_COEF_V0[9U]; /* FIR_COEF_V0 0..8 */
13957  volatile uint32_t FIR_COEF_V0_C[9U]; /* FIR_COEF_V0_C 0..8 */
13958  volatile uint32_t FIR_COEF_V12[16U]; /* FIR_COEF_V12 0..15 */
13959  volatile uint32_t FIR_COEF_V12_C[16U]; /* FIR_COEF_V12_C 0..15 */
13960  volatile uint8_t Resv_516[8];
13961  volatile uint32_t MFLAG_THRESHOLD; /* MFLAG_THRESHOLD */
13962  volatile uint32_t PICTURE_SIZE; /* PICTURE_SIZE */
13963  volatile uint8_t Resv_528[4];
13964  volatile uint32_t SIZE; /* SIZE */
13965  volatile uint32_t POSITION; /* POSITION */
13966  volatile uint8_t Resv_540[4];
13967  volatile uint32_t CSC_COEF7; /* CSC_COEF7 */
13968  volatile uint8_t Resv_548[4];
13969  volatile uint32_t ROW_INC; /* ROW_INC */
13970  volatile uint32_t ROW_INC_UV; /* ROW_INC_UV */
13971  volatile uint32_t BA_EXT_0; /* BA_EXT_0 */
13972  volatile uint32_t BA_EXT_1; /* BA_EXT_1 */
13973  volatile uint32_t BA_UV_EXT_0; /* BA_UV_EXT_0 */
13974  volatile uint32_t BA_UV_EXT_1; /* BA_UV_EXT_1 */
13975  volatile uint8_t Resv_584[12];
13976  volatile uint32_t SECURE; /* SECURE */
13977 } CSL_dss_wbRegs;
13978 
13979 
13980 /**************************************************************************
13981 * Register Macros
13982 **************************************************************************/
13983 
13984 #define CSL_DSS_WB_ACCUH_0 (0x00000000U)
13985 #define CSL_DSS_WB_ACCUH_1 (0x00000004U)
13986 #define CSL_DSS_WB_ACCUH2_0 (0x00000008U)
13987 #define CSL_DSS_WB_ACCUH2_1 (0x0000000CU)
13988 #define CSL_DSS_WB_ACCUV_0 (0x00000010U)
13989 #define CSL_DSS_WB_ACCUV_1 (0x00000014U)
13990 #define CSL_DSS_WB_ACCUV2_0 (0x00000018U)
13991 #define CSL_DSS_WB_ACCUV2_1 (0x0000001CU)
13992 #define CSL_DSS_WB_ATTRIBUTES (0x00000020U)
13993 #define CSL_DSS_WB_ATTRIBUTES2 (0x00000024U)
13994 #define CSL_DSS_WB_BA_0 (0x00000028U)
13995 #define CSL_DSS_WB_BA_1 (0x0000002CU)
13996 #define CSL_DSS_WB_BA_UV_0 (0x00000030U)
13997 #define CSL_DSS_WB_BA_UV_1 (0x00000034U)
13998 #define CSL_DSS_WB_BUF_SIZE_STATUS (0x00000038U)
13999 #define CSL_DSS_WB_BUF_THRESHOLD (0x0000003CU)
14000 #define CSL_DSS_WB_CSC_COEF0 (0x00000040U)
14001 #define CSL_DSS_WB_CSC_COEF1 (0x00000044U)
14002 #define CSL_DSS_WB_CSC_COEF2 (0x00000048U)
14003 #define CSL_DSS_WB_CSC_COEF3 (0x0000004CU)
14004 #define CSL_DSS_WB_CSC_COEF4 (0x00000050U)
14005 #define CSL_DSS_WB_CSC_COEF5 (0x00000054U)
14006 #define CSL_DSS_WB_CSC_COEF6 (0x00000058U)
14007 #define CSL_DSS_WB_FIRH (0x0000005CU)
14008 #define CSL_DSS_WB_FIRH2 (0x00000060U)
14009 #define CSL_DSS_WB_FIRV (0x00000064U)
14010 #define CSL_DSS_WB_FIRV2 (0x00000068U)
14011 #define CSL_DSS_WB_FIR_COEF_H0(index) (0x0000006CU+((uint32_t)(index)*0x4U))
14012 #define CSL_DSS_WB_FIR_COEF_H0_C(index) (0x00000090U+((uint32_t)(index)*0x4U))
14013 #define CSL_DSS_WB_FIR_COEF_H12(index) (0x000000B4U+((uint32_t)(index)*0x4U))
14014 #define CSL_DSS_WB_FIR_COEF_H12_C(index) (0x000000F4U+((uint32_t)(index)*0x4U))
14015 #define CSL_DSS_WB_FIR_COEF_V0(index) (0x00000134U+((uint32_t)(index)*0x4U))
14016 #define CSL_DSS_WB_FIR_COEF_V0_C(index) (0x00000158U+((uint32_t)(index)*0x4U))
14017 #define CSL_DSS_WB_FIR_COEF_V12(index) (0x0000017CU+((uint32_t)(index)*0x4U))
14018 #define CSL_DSS_WB_FIR_COEF_V12_C(index) (0x000001BCU+((uint32_t)(index)*0x4U))
14019 #define CSL_DSS_WB_MFLAG_THRESHOLD (0x00000204U)
14020 #define CSL_DSS_WB_PICTURE_SIZE (0x00000208U)
14021 #define CSL_DSS_WB_SIZE (0x00000210U)
14022 #define CSL_DSS_WB_POSITION (0x00000214U)
14023 #define CSL_DSS_WB_CSC_COEF7 (0x0000021CU)
14024 #define CSL_DSS_WB_ROW_INC (0x00000224U)
14025 #define CSL_DSS_WB_ROW_INC_UV (0x00000228U)
14026 #define CSL_DSS_WB_BA_EXT_0 (0x0000022CU)
14027 #define CSL_DSS_WB_BA_EXT_1 (0x00000230U)
14028 #define CSL_DSS_WB_BA_UV_EXT_0 (0x00000234U)
14029 #define CSL_DSS_WB_BA_UV_EXT_1 (0x00000238U)
14030 #define CSL_DSS_WB_SECURE (0x00000248U)
14031 
14032 /**************************************************************************
14033 * Field Definition Macros
14034 **************************************************************************/
14035 
14036 
14037 /* ACCUH_0 */
14038 
14039 #define CSL_DSS_WB_ACCUH_0_HORIZONTALACCU_MASK (0x00FFFFFFU)
14040 #define CSL_DSS_WB_ACCUH_0_HORIZONTALACCU_SHIFT (0x00000000U)
14041 #define CSL_DSS_WB_ACCUH_0_HORIZONTALACCU_MAX (0x00FFFFFFU)
14042 
14043 #define CSL_DSS_WB_ACCUH_0_RESERVED_MASK (0xFF000000U)
14044 #define CSL_DSS_WB_ACCUH_0_RESERVED_SHIFT (0x00000018U)
14045 #define CSL_DSS_WB_ACCUH_0_RESERVED_MAX (0x000000FFU)
14046 
14047 /* ACCUH_1 */
14048 
14049 #define CSL_DSS_WB_ACCUH_1_HORIZONTALACCU_MASK (0x00FFFFFFU)
14050 #define CSL_DSS_WB_ACCUH_1_HORIZONTALACCU_SHIFT (0x00000000U)
14051 #define CSL_DSS_WB_ACCUH_1_HORIZONTALACCU_MAX (0x00FFFFFFU)
14052 
14053 #define CSL_DSS_WB_ACCUH_1_RESERVED_MASK (0xFF000000U)
14054 #define CSL_DSS_WB_ACCUH_1_RESERVED_SHIFT (0x00000018U)
14055 #define CSL_DSS_WB_ACCUH_1_RESERVED_MAX (0x000000FFU)
14056 
14057 /* ACCUH2_0 */
14058 
14059 #define CSL_DSS_WB_ACCUH2_0_HORIZONTALACCU_MASK (0x00FFFFFFU)
14060 #define CSL_DSS_WB_ACCUH2_0_HORIZONTALACCU_SHIFT (0x00000000U)
14061 #define CSL_DSS_WB_ACCUH2_0_HORIZONTALACCU_MAX (0x00FFFFFFU)
14062 
14063 #define CSL_DSS_WB_ACCUH2_0_RESERVED_MASK (0xFF000000U)
14064 #define CSL_DSS_WB_ACCUH2_0_RESERVED_SHIFT (0x00000018U)
14065 #define CSL_DSS_WB_ACCUH2_0_RESERVED_MAX (0x000000FFU)
14066 
14067 /* ACCUH2_1 */
14068 
14069 #define CSL_DSS_WB_ACCUH2_1_HORIZONTALACCU_MASK (0x00FFFFFFU)
14070 #define CSL_DSS_WB_ACCUH2_1_HORIZONTALACCU_SHIFT (0x00000000U)
14071 #define CSL_DSS_WB_ACCUH2_1_HORIZONTALACCU_MAX (0x00FFFFFFU)
14072 
14073 #define CSL_DSS_WB_ACCUH2_1_RESERVED_MASK (0xFF000000U)
14074 #define CSL_DSS_WB_ACCUH2_1_RESERVED_SHIFT (0x00000018U)
14075 #define CSL_DSS_WB_ACCUH2_1_RESERVED_MAX (0x000000FFU)
14076 
14077 /* ACCUV_0 */
14078 
14079 #define CSL_DSS_WB_ACCUV_0_VERTICALACCU_MASK (0x00FFFFFFU)
14080 #define CSL_DSS_WB_ACCUV_0_VERTICALACCU_SHIFT (0x00000000U)
14081 #define CSL_DSS_WB_ACCUV_0_VERTICALACCU_MAX (0x00FFFFFFU)
14082 
14083 #define CSL_DSS_WB_ACCUV_0_RESERVED_MASK (0xFF000000U)
14084 #define CSL_DSS_WB_ACCUV_0_RESERVED_SHIFT (0x00000018U)
14085 #define CSL_DSS_WB_ACCUV_0_RESERVED_MAX (0x000000FFU)
14086 
14087 /* ACCUV_1 */
14088 
14089 #define CSL_DSS_WB_ACCUV_1_VERTICALACCU_MASK (0x00FFFFFFU)
14090 #define CSL_DSS_WB_ACCUV_1_VERTICALACCU_SHIFT (0x00000000U)
14091 #define CSL_DSS_WB_ACCUV_1_VERTICALACCU_MAX (0x00FFFFFFU)
14092 
14093 #define CSL_DSS_WB_ACCUV_1_RESERVED_MASK (0xFF000000U)
14094 #define CSL_DSS_WB_ACCUV_1_RESERVED_SHIFT (0x00000018U)
14095 #define CSL_DSS_WB_ACCUV_1_RESERVED_MAX (0x000000FFU)
14096 
14097 /* ACCUV2_0 */
14098 
14099 #define CSL_DSS_WB_ACCUV2_0_VERTICALACCU_MASK (0x00FFFFFFU)
14100 #define CSL_DSS_WB_ACCUV2_0_VERTICALACCU_SHIFT (0x00000000U)
14101 #define CSL_DSS_WB_ACCUV2_0_VERTICALACCU_MAX (0x00FFFFFFU)
14102 
14103 #define CSL_DSS_WB_ACCUV2_0_RESERVED_MASK (0xFF000000U)
14104 #define CSL_DSS_WB_ACCUV2_0_RESERVED_SHIFT (0x00000018U)
14105 #define CSL_DSS_WB_ACCUV2_0_RESERVED_MAX (0x000000FFU)
14106 
14107 /* ACCUV2_1 */
14108 
14109 #define CSL_DSS_WB_ACCUV2_1_VERTICALACCU_MASK (0x00FFFFFFU)
14110 #define CSL_DSS_WB_ACCUV2_1_VERTICALACCU_SHIFT (0x00000000U)
14111 #define CSL_DSS_WB_ACCUV2_1_VERTICALACCU_MAX (0x00FFFFFFU)
14112 
14113 #define CSL_DSS_WB_ACCUV2_1_RESERVED_MASK (0xFF000000U)
14114 #define CSL_DSS_WB_ACCUV2_1_RESERVED_SHIFT (0x00000018U)
14115 #define CSL_DSS_WB_ACCUV2_1_RESERVED_MAX (0x000000FFU)
14116 
14117 /* ATTRIBUTES */
14118 
14119 #define CSL_DSS_WB_ATTRIBUTES_ENABLE_MASK (0x00000001U)
14120 #define CSL_DSS_WB_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
14121 #define CSL_DSS_WB_ATTRIBUTES_ENABLE_MAX (0x00000001U)
14122 
14123 #define CSL_DSS_WB_ATTRIBUTES_ENABLE_VAL_WBDIS (0x0U)
14124 #define CSL_DSS_WB_ATTRIBUTES_ENABLE_VAL_WBENB (0x1U)
14125 
14126 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_MASK (0x0000007EU)
14127 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_SHIFT (0x00000001U)
14128 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_MAX (0x0000003FU)
14129 
14130 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_ARGB16_4444 (0x0U)
14131 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_ABGR16_4444 (0x1U)
14132 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_RGBA16_4444 (0x2U)
14133 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_RGB16_565 (0x3U)
14134 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_BGR16_565 (0x4U)
14135 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_ARGB16_1555 (0x5U)
14136 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_ABGR16_1555 (0x6U)
14137 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_ARGB32_8888 (0x7U)
14138 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_ABGR32_8888 (0x8U)
14139 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_RGBA32_8888 (0x9U)
14140 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_BGRA32_8888 (0xAU)
14141 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_RGB24P_888 (0xBU)
14142 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_ARGB64_16161616 (0x10U)
14143 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_RGBA64_16161616 (0x11U)
14144 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_RGB565A8 (0x16U)
14145 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_BGR565A8 (0x17U)
14146 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_XRGB16_4444 (0x20U)
14147 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_XBGR16_4444 (0x21U)
14148 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_RGBX16_4444 (0x22U)
14149 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_XRGB16_1555 (0x25U)
14150 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_XBGR16_1555 (0x26U)
14151 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_XRGB32_8888 (0x27U)
14152 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_XBGR32_8888 (0x28U)
14153 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_RGBX32_8888 (0x29U)
14154 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_BGRX32_8888 (0x2AU)
14155 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_XRGB64_16161616 (0x30U)
14156 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_RGBX64_16161616 (0x31U)
14157 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_YUV422_NV12 (0x3CU)
14158 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_YUV420_NV12 (0x3DU)
14159 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_YUV422_YUV2 (0x3EU)
14160 #define CSL_DSS_WB_ATTRIBUTES_FORMAT_VAL_YUV422_UYVY (0x3FU)
14161 
14162 #define CSL_DSS_WB_ATTRIBUTES_RESIZEENABLE_MASK (0x00000180U)
14163 #define CSL_DSS_WB_ATTRIBUTES_RESIZEENABLE_SHIFT (0x00000007U)
14164 #define CSL_DSS_WB_ATTRIBUTES_RESIZEENABLE_MAX (0x00000003U)
14165 
14166 #define CSL_DSS_WB_ATTRIBUTES_RESIZEENABLE_VAL_RESIZEPROC (0x0U)
14167 #define CSL_DSS_WB_ATTRIBUTES_RESIZEENABLE_VAL_HRESIZE (0x1U)
14168 #define CSL_DSS_WB_ATTRIBUTES_RESIZEENABLE_VAL_VRESIZE (0x2U)
14169 #define CSL_DSS_WB_ATTRIBUTES_RESIZEENABLE_VAL_HVRESIZE (0x3U)
14170 
14171 #define CSL_DSS_WB_ATTRIBUTES_ALPHAENABLE_MASK (0x00000200U)
14172 #define CSL_DSS_WB_ATTRIBUTES_ALPHAENABLE_SHIFT (0x00000009U)
14173 #define CSL_DSS_WB_ATTRIBUTES_ALPHAENABLE_MAX (0x00000001U)
14174 
14175 #define CSL_DSS_WB_ATTRIBUTES_ALPHAENABLE_VAL_DISABLE (0x0U)
14176 #define CSL_DSS_WB_ATTRIBUTES_ALPHAENABLE_VAL_ENABLE (0x1U)
14177 
14178 #define CSL_DSS_WB_ATTRIBUTES_RESERVED1_MASK (0x00000400U)
14179 #define CSL_DSS_WB_ATTRIBUTES_RESERVED1_SHIFT (0x0000000AU)
14180 #define CSL_DSS_WB_ATTRIBUTES_RESERVED1_MAX (0x00000001U)
14181 
14182 #define CSL_DSS_WB_ATTRIBUTES_COLORCONVENABLE_MASK (0x00000800U)
14183 #define CSL_DSS_WB_ATTRIBUTES_COLORCONVENABLE_SHIFT (0x0000000BU)
14184 #define CSL_DSS_WB_ATTRIBUTES_COLORCONVENABLE_MAX (0x00000001U)
14185 
14186 #define CSL_DSS_WB_ATTRIBUTES_COLORCONVENABLE_VAL_COLSPCDIS (0x0U)
14187 #define CSL_DSS_WB_ATTRIBUTES_COLORCONVENABLE_VAL_COLSPCENB (0x1U)
14188 
14189 #define CSL_DSS_WB_ATTRIBUTES_FULLRANGE_MASK (0x00001000U)
14190 #define CSL_DSS_WB_ATTRIBUTES_FULLRANGE_SHIFT (0x0000000CU)
14191 #define CSL_DSS_WB_ATTRIBUTES_FULLRANGE_MAX (0x00000001U)
14192 
14193 #define CSL_DSS_WB_ATTRIBUTES_FULLRANGE_VAL_LIMRANGE (0x0U)
14194 #define CSL_DSS_WB_ATTRIBUTES_FULLRANGE_VAL_FULLRANGE (0x1U)
14195 
14196 #define CSL_DSS_WB_ATTRIBUTES_RESERVED2_MASK (0x00002000U)
14197 #define CSL_DSS_WB_ATTRIBUTES_RESERVED2_SHIFT (0x0000000DU)
14198 #define CSL_DSS_WB_ATTRIBUTES_RESERVED2_MAX (0x00000001U)
14199 
14200 #define CSL_DSS_WB_ATTRIBUTES_RESERVED3_MASK (0x0007C000U)
14201 #define CSL_DSS_WB_ATTRIBUTES_RESERVED3_SHIFT (0x0000000EU)
14202 #define CSL_DSS_WB_ATTRIBUTES_RESERVED3_MAX (0x0000001FU)
14203 
14204 #define CSL_DSS_WB_ATTRIBUTES_WRITEBACKMODE_MASK (0x00080000U)
14205 #define CSL_DSS_WB_ATTRIBUTES_WRITEBACKMODE_SHIFT (0x00000013U)
14206 #define CSL_DSS_WB_ATTRIBUTES_WRITEBACKMODE_MAX (0x00000001U)
14207 
14208 #define CSL_DSS_WB_ATTRIBUTES_WRITEBACKMODE_VAL_CAPTURE (0x0U)
14209 #define CSL_DSS_WB_ATTRIBUTES_WRITEBACKMODE_VAL_MEM2MEM (0x1U)
14210 
14211 #define CSL_DSS_WB_ATTRIBUTES_GOBIT_MASK (0x00100000U)
14212 #define CSL_DSS_WB_ATTRIBUTES_GOBIT_SHIFT (0x00000014U)
14213 #define CSL_DSS_WB_ATTRIBUTES_GOBIT_SET (0x00000001U)
14214 #define CSL_DSS_WB_ATTRIBUTES_GOBIT_MAX (0x00000001U)
14215 
14216 #define CSL_DSS_WB_ATTRIBUTES_GOBIT_VAL_HFUISR (0x0U)
14217 #define CSL_DSS_WB_ATTRIBUTES_GOBIT_VAL_UFPSR (0x1U)
14218 
14219 #define CSL_DSS_WB_ATTRIBUTES_VERTICALTAPS_MASK (0x00200000U)
14220 #define CSL_DSS_WB_ATTRIBUTES_VERTICALTAPS_SHIFT (0x00000015U)
14221 #define CSL_DSS_WB_ATTRIBUTES_VERTICALTAPS_MAX (0x00000001U)
14222 
14223 #define CSL_DSS_WB_ATTRIBUTES_VERTICALTAPS_VAL_TAPS3 (0x0U)
14224 #define CSL_DSS_WB_ATTRIBUTES_VERTICALTAPS_VAL_TAPS5 (0x1U)
14225 
14226 #define CSL_DSS_WB_ATTRIBUTES_RESERVED4_MASK (0x00400000U)
14227 #define CSL_DSS_WB_ATTRIBUTES_RESERVED4_SHIFT (0x00000016U)
14228 #define CSL_DSS_WB_ATTRIBUTES_RESERVED4_MAX (0x00000001U)
14229 
14230 #define CSL_DSS_WB_ATTRIBUTES_ARBITRATION_MASK (0x00800000U)
14231 #define CSL_DSS_WB_ATTRIBUTES_ARBITRATION_SHIFT (0x00000017U)
14232 #define CSL_DSS_WB_ATTRIBUTES_ARBITRATION_MAX (0x00000001U)
14233 
14234 #define CSL_DSS_WB_ATTRIBUTES_ARBITRATION_VAL_NORMALPRIO (0x0U)
14235 #define CSL_DSS_WB_ATTRIBUTES_ARBITRATION_VAL_HIGHPRIO (0x1U)
14236 
14237 #define CSL_DSS_WB_ATTRIBUTES_CAPTUREMODE_MASK (0x07000000U)
14238 #define CSL_DSS_WB_ATTRIBUTES_CAPTUREMODE_SHIFT (0x00000018U)
14239 #define CSL_DSS_WB_ATTRIBUTES_CAPTUREMODE_MAX (0x00000007U)
14240 
14241 #define CSL_DSS_WB_ATTRIBUTES_CAPTUREMODE_VAL_ALL (0x0U)
14242 #define CSL_DSS_WB_ATTRIBUTES_CAPTUREMODE_VAL_ONLY1 (0x1U)
14243 #define CSL_DSS_WB_ATTRIBUTES_CAPTUREMODE_VAL_ONLY1_2 (0x2U)
14244 #define CSL_DSS_WB_ATTRIBUTES_CAPTUREMODE_VAL_ONLY1_3 (0x3U)
14245 #define CSL_DSS_WB_ATTRIBUTES_CAPTUREMODE_VAL_ONLY1_4 (0x4U)
14246 #define CSL_DSS_WB_ATTRIBUTES_CAPTUREMODE_VAL_ONLY1_5 (0x5U)
14247 #define CSL_DSS_WB_ATTRIBUTES_CAPTUREMODE_VAL_ONLY1_6 (0x6U)
14248 #define CSL_DSS_WB_ATTRIBUTES_CAPTUREMODE_VAL_ONLY1_7 (0x7U)
14249 
14250 #define CSL_DSS_WB_ATTRIBUTES_IDLESIZE_MASK (0x08000000U)
14251 #define CSL_DSS_WB_ATTRIBUTES_IDLESIZE_SHIFT (0x0000001BU)
14252 #define CSL_DSS_WB_ATTRIBUTES_IDLESIZE_MAX (0x00000001U)
14253 
14254 #define CSL_DSS_WB_ATTRIBUTES_IDLESIZE_VAL_IDLESINGLE (0x0U)
14255 #define CSL_DSS_WB_ATTRIBUTES_IDLESIZE_VAL_IDLEBURST (0x1U)
14256 
14257 #define CSL_DSS_WB_ATTRIBUTES_IDLENUMBER_MASK (0xF0000000U)
14258 #define CSL_DSS_WB_ATTRIBUTES_IDLENUMBER_SHIFT (0x0000001CU)
14259 #define CSL_DSS_WB_ATTRIBUTES_IDLENUMBER_MAX (0x0000000FU)
14260 
14261 /* ATTRIBUTES2 */
14262 
14263 #define CSL_DSS_WB_ATTRIBUTES2_RESERVED_MASK (0x00000001U)
14264 #define CSL_DSS_WB_ATTRIBUTES2_RESERVED_SHIFT (0x00000000U)
14265 #define CSL_DSS_WB_ATTRIBUTES2_RESERVED_MAX (0x00000001U)
14266 
14267 #define CSL_DSS_WB_ATTRIBUTES2_RESERVED0_MASK (0x0000007EU)
14268 #define CSL_DSS_WB_ATTRIBUTES2_RESERVED0_SHIFT (0x00000001U)
14269 #define CSL_DSS_WB_ATTRIBUTES2_RESERVED0_MAX (0x0000003FU)
14270 
14271 #define CSL_DSS_WB_ATTRIBUTES2_YUV_SIZE_MASK (0x00000180U)
14272 #define CSL_DSS_WB_ATTRIBUTES2_YUV_SIZE_SHIFT (0x00000007U)
14273 #define CSL_DSS_WB_ATTRIBUTES2_YUV_SIZE_MAX (0x00000003U)
14274 
14275 #define CSL_DSS_WB_ATTRIBUTES2_YUV_SIZE_VAL_8B (0x0U)
14276 #define CSL_DSS_WB_ATTRIBUTES2_YUV_SIZE_VAL_10B (0x1U)
14277 #define CSL_DSS_WB_ATTRIBUTES2_YUV_SIZE_VAL_12B (0x2U)
14278 
14279 #define CSL_DSS_WB_ATTRIBUTES2_YUV_MODE_MASK (0x00000200U)
14280 #define CSL_DSS_WB_ATTRIBUTES2_YUV_MODE_SHIFT (0x00000009U)
14281 #define CSL_DSS_WB_ATTRIBUTES2_YUV_MODE_MAX (0x00000001U)
14282 
14283 #define CSL_DSS_WB_ATTRIBUTES2_YUV_MODE_VAL_PACKED (0x0U)
14284 #define CSL_DSS_WB_ATTRIBUTES2_YUV_MODE_VAL_UNPACKED (0x1U)
14285 
14286 #define CSL_DSS_WB_ATTRIBUTES2_YUV_ALIGN_MASK (0x00000400U)
14287 #define CSL_DSS_WB_ATTRIBUTES2_YUV_ALIGN_SHIFT (0x0000000AU)
14288 #define CSL_DSS_WB_ATTRIBUTES2_YUV_ALIGN_MAX (0x00000001U)
14289 
14290 #define CSL_DSS_WB_ATTRIBUTES2_YUV_ALIGN_VAL_MSB (0x1U)
14291 #define CSL_DSS_WB_ATTRIBUTES2_YUV_ALIGN_VAL_LSB (0x0U)
14292 
14293 #define CSL_DSS_WB_ATTRIBUTES2_RESERVED1_MASK (0x03FFF800U)
14294 #define CSL_DSS_WB_ATTRIBUTES2_RESERVED1_SHIFT (0x0000000BU)
14295 #define CSL_DSS_WB_ATTRIBUTES2_RESERVED1_MAX (0x00007FFFU)
14296 
14297 #define CSL_DSS_WB_ATTRIBUTES2_TAGS_MASK (0x7C000000U)
14298 #define CSL_DSS_WB_ATTRIBUTES2_TAGS_SHIFT (0x0000001AU)
14299 #define CSL_DSS_WB_ATTRIBUTES2_TAGS_MAX (0x0000001FU)
14300 
14301 #define CSL_DSS_WB_ATTRIBUTES2_RESERVED2_MASK (0x80000000U)
14302 #define CSL_DSS_WB_ATTRIBUTES2_RESERVED2_SHIFT (0x0000001FU)
14303 #define CSL_DSS_WB_ATTRIBUTES2_RESERVED2_MAX (0x00000001U)
14304 
14305 /* BA_0 */
14306 
14307 #define CSL_DSS_WB_BA_0_BA_MASK (0xFFFFFFFFU)
14308 #define CSL_DSS_WB_BA_0_BA_SHIFT (0x00000000U)
14309 #define CSL_DSS_WB_BA_0_BA_MAX (0xFFFFFFFFU)
14310 
14311 /* BA_1 */
14312 
14313 #define CSL_DSS_WB_BA_1_BA_MASK (0xFFFFFFFFU)
14314 #define CSL_DSS_WB_BA_1_BA_SHIFT (0x00000000U)
14315 #define CSL_DSS_WB_BA_1_BA_MAX (0xFFFFFFFFU)
14316 
14317 /* BA_UV_0 */
14318 
14319 #define CSL_DSS_WB_BA_UV_0_BA_MASK (0xFFFFFFFFU)
14320 #define CSL_DSS_WB_BA_UV_0_BA_SHIFT (0x00000000U)
14321 #define CSL_DSS_WB_BA_UV_0_BA_MAX (0xFFFFFFFFU)
14322 
14323 /* BA_UV_1 */
14324 
14325 #define CSL_DSS_WB_BA_UV_1_BA_MASK (0xFFFFFFFFU)
14326 #define CSL_DSS_WB_BA_UV_1_BA_SHIFT (0x00000000U)
14327 #define CSL_DSS_WB_BA_UV_1_BA_MAX (0xFFFFFFFFU)
14328 
14329 /* BUF_SIZE_STATUS */
14330 
14331 #define CSL_DSS_WB_BUF_SIZE_STATUS_BUFSIZE_MASK (0x0000FFFFU)
14332 #define CSL_DSS_WB_BUF_SIZE_STATUS_BUFSIZE_SHIFT (0x00000000U)
14333 #define CSL_DSS_WB_BUF_SIZE_STATUS_BUFSIZE_MAX (0x0000FFFFU)
14334 
14335 #define CSL_DSS_WB_BUF_SIZE_STATUS_RESERVED_MASK (0xFFFF0000U)
14336 #define CSL_DSS_WB_BUF_SIZE_STATUS_RESERVED_SHIFT (0x00000010U)
14337 #define CSL_DSS_WB_BUF_SIZE_STATUS_RESERVED_MAX (0x0000FFFFU)
14338 
14339 /* BUF_THRESHOLD */
14340 
14341 #define CSL_DSS_WB_BUF_THRESHOLD_BUFLOWTHRESHOLD_MASK (0x0000FFFFU)
14342 #define CSL_DSS_WB_BUF_THRESHOLD_BUFLOWTHRESHOLD_SHIFT (0x00000000U)
14343 #define CSL_DSS_WB_BUF_THRESHOLD_BUFLOWTHRESHOLD_MAX (0x0000FFFFU)
14344 
14345 #define CSL_DSS_WB_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MASK (0xFFFF0000U)
14346 #define CSL_DSS_WB_BUF_THRESHOLD_BUFHIGHTHRESHOLD_SHIFT (0x00000010U)
14347 #define CSL_DSS_WB_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MAX (0x0000FFFFU)
14348 
14349 /* CSC_COEF0 */
14350 
14351 #define CSL_DSS_WB_CSC_COEF0_C00_MASK (0x000007FFU)
14352 #define CSL_DSS_WB_CSC_COEF0_C00_SHIFT (0x00000000U)
14353 #define CSL_DSS_WB_CSC_COEF0_C00_MAX (0x000007FFU)
14354 
14355 #define CSL_DSS_WB_CSC_COEF0_RESERVED_53_MASK (0x0000F800U)
14356 #define CSL_DSS_WB_CSC_COEF0_RESERVED_53_SHIFT (0x0000000BU)
14357 #define CSL_DSS_WB_CSC_COEF0_RESERVED_53_MAX (0x0000001FU)
14358 
14359 #define CSL_DSS_WB_CSC_COEF0_C01_MASK (0x07FF0000U)
14360 #define CSL_DSS_WB_CSC_COEF0_C01_SHIFT (0x00000010U)
14361 #define CSL_DSS_WB_CSC_COEF0_C01_MAX (0x000007FFU)
14362 
14363 #define CSL_DSS_WB_CSC_COEF0_RESERVED_52_MASK (0xF8000000U)
14364 #define CSL_DSS_WB_CSC_COEF0_RESERVED_52_SHIFT (0x0000001BU)
14365 #define CSL_DSS_WB_CSC_COEF0_RESERVED_52_MAX (0x0000001FU)
14366 
14367 /* CSC_COEF1 */
14368 
14369 #define CSL_DSS_WB_CSC_COEF1_C02_MASK (0x000007FFU)
14370 #define CSL_DSS_WB_CSC_COEF1_C02_SHIFT (0x00000000U)
14371 #define CSL_DSS_WB_CSC_COEF1_C02_MAX (0x000007FFU)
14372 
14373 #define CSL_DSS_WB_CSC_COEF1_RESERVED_55_MASK (0x0000F800U)
14374 #define CSL_DSS_WB_CSC_COEF1_RESERVED_55_SHIFT (0x0000000BU)
14375 #define CSL_DSS_WB_CSC_COEF1_RESERVED_55_MAX (0x0000001FU)
14376 
14377 #define CSL_DSS_WB_CSC_COEF1_C10_MASK (0x07FF0000U)
14378 #define CSL_DSS_WB_CSC_COEF1_C10_SHIFT (0x00000010U)
14379 #define CSL_DSS_WB_CSC_COEF1_C10_MAX (0x000007FFU)
14380 
14381 #define CSL_DSS_WB_CSC_COEF1_RESERVED_54_MASK (0xF8000000U)
14382 #define CSL_DSS_WB_CSC_COEF1_RESERVED_54_SHIFT (0x0000001BU)
14383 #define CSL_DSS_WB_CSC_COEF1_RESERVED_54_MAX (0x0000001FU)
14384 
14385 /* CSC_COEF2 */
14386 
14387 #define CSL_DSS_WB_CSC_COEF2_C11_MASK (0x000007FFU)
14388 #define CSL_DSS_WB_CSC_COEF2_C11_SHIFT (0x00000000U)
14389 #define CSL_DSS_WB_CSC_COEF2_C11_MAX (0x000007FFU)
14390 
14391 #define CSL_DSS_WB_CSC_COEF2_RESERVED_57_MASK (0x0000F800U)
14392 #define CSL_DSS_WB_CSC_COEF2_RESERVED_57_SHIFT (0x0000000BU)
14393 #define CSL_DSS_WB_CSC_COEF2_RESERVED_57_MAX (0x0000001FU)
14394 
14395 #define CSL_DSS_WB_CSC_COEF2_C12_MASK (0x07FF0000U)
14396 #define CSL_DSS_WB_CSC_COEF2_C12_SHIFT (0x00000010U)
14397 #define CSL_DSS_WB_CSC_COEF2_C12_MAX (0x000007FFU)
14398 
14399 #define CSL_DSS_WB_CSC_COEF2_RESERVED_56_MASK (0xF8000000U)
14400 #define CSL_DSS_WB_CSC_COEF2_RESERVED_56_SHIFT (0x0000001BU)
14401 #define CSL_DSS_WB_CSC_COEF2_RESERVED_56_MAX (0x0000001FU)
14402 
14403 /* CSC_COEF3 */
14404 
14405 #define CSL_DSS_WB_CSC_COEF3_C20_MASK (0x000007FFU)
14406 #define CSL_DSS_WB_CSC_COEF3_C20_SHIFT (0x00000000U)
14407 #define CSL_DSS_WB_CSC_COEF3_C20_MAX (0x000007FFU)
14408 
14409 #define CSL_DSS_WB_CSC_COEF3_RESERVED_59_MASK (0x0000F800U)
14410 #define CSL_DSS_WB_CSC_COEF3_RESERVED_59_SHIFT (0x0000000BU)
14411 #define CSL_DSS_WB_CSC_COEF3_RESERVED_59_MAX (0x0000001FU)
14412 
14413 #define CSL_DSS_WB_CSC_COEF3_C21_MASK (0x07FF0000U)
14414 #define CSL_DSS_WB_CSC_COEF3_C21_SHIFT (0x00000010U)
14415 #define CSL_DSS_WB_CSC_COEF3_C21_MAX (0x000007FFU)
14416 
14417 #define CSL_DSS_WB_CSC_COEF3_RESERVED_58_MASK (0xF8000000U)
14418 #define CSL_DSS_WB_CSC_COEF3_RESERVED_58_SHIFT (0x0000001BU)
14419 #define CSL_DSS_WB_CSC_COEF3_RESERVED_58_MAX (0x0000001FU)
14420 
14421 /* CSC_COEF4 */
14422 
14423 #define CSL_DSS_WB_CSC_COEF4_C22_MASK (0x000007FFU)
14424 #define CSL_DSS_WB_CSC_COEF4_C22_SHIFT (0x00000000U)
14425 #define CSL_DSS_WB_CSC_COEF4_C22_MAX (0x000007FFU)
14426 
14427 #define CSL_DSS_WB_CSC_COEF4_RESERVED_60_MASK (0xFFFFF800U)
14428 #define CSL_DSS_WB_CSC_COEF4_RESERVED_60_SHIFT (0x0000000BU)
14429 #define CSL_DSS_WB_CSC_COEF4_RESERVED_60_MAX (0x001FFFFFU)
14430 
14431 /* CSC_COEF5 */
14432 
14433 #define CSL_DSS_WB_CSC_COEF5_RESERVED_MASK (0x00000007U)
14434 #define CSL_DSS_WB_CSC_COEF5_RESERVED_SHIFT (0x00000000U)
14435 #define CSL_DSS_WB_CSC_COEF5_RESERVED_MAX (0x00000007U)
14436 
14437 #define CSL_DSS_WB_CSC_COEF5_PREOFFSET1_MASK (0x0000FFF8U)
14438 #define CSL_DSS_WB_CSC_COEF5_PREOFFSET1_SHIFT (0x00000003U)
14439 #define CSL_DSS_WB_CSC_COEF5_PREOFFSET1_MAX (0x00001FFFU)
14440 
14441 #define CSL_DSS_WB_CSC_COEF5_RESERVED1_MASK (0x00070000U)
14442 #define CSL_DSS_WB_CSC_COEF5_RESERVED1_SHIFT (0x00000010U)
14443 #define CSL_DSS_WB_CSC_COEF5_RESERVED1_MAX (0x00000007U)
14444 
14445 #define CSL_DSS_WB_CSC_COEF5_PREOFFSET2_MASK (0xFFF80000U)
14446 #define CSL_DSS_WB_CSC_COEF5_PREOFFSET2_SHIFT (0x00000013U)
14447 #define CSL_DSS_WB_CSC_COEF5_PREOFFSET2_MAX (0x00001FFFU)
14448 
14449 /* CSC_COEF6 */
14450 
14451 #define CSL_DSS_WB_CSC_COEF6_RESERVED_MASK (0x00000007U)
14452 #define CSL_DSS_WB_CSC_COEF6_RESERVED_SHIFT (0x00000000U)
14453 #define CSL_DSS_WB_CSC_COEF6_RESERVED_MAX (0x00000007U)
14454 
14455 #define CSL_DSS_WB_CSC_COEF6_PREOFFSET3_MASK (0x0000FFF8U)
14456 #define CSL_DSS_WB_CSC_COEF6_PREOFFSET3_SHIFT (0x00000003U)
14457 #define CSL_DSS_WB_CSC_COEF6_PREOFFSET3_MAX (0x00001FFFU)
14458 
14459 #define CSL_DSS_WB_CSC_COEF6_RESERVED1_MASK (0x00070000U)
14460 #define CSL_DSS_WB_CSC_COEF6_RESERVED1_SHIFT (0x00000010U)
14461 #define CSL_DSS_WB_CSC_COEF6_RESERVED1_MAX (0x00000007U)
14462 
14463 #define CSL_DSS_WB_CSC_COEF6_POSTOFFSET1_MASK (0xFFF80000U)
14464 #define CSL_DSS_WB_CSC_COEF6_POSTOFFSET1_SHIFT (0x00000013U)
14465 #define CSL_DSS_WB_CSC_COEF6_POSTOFFSET1_MAX (0x00001FFFU)
14466 
14467 /* FIRH */
14468 
14469 #define CSL_DSS_WB_FIRH_FIRHINC_MASK (0x00FFFFFFU)
14470 #define CSL_DSS_WB_FIRH_FIRHINC_SHIFT (0x00000000U)
14471 #define CSL_DSS_WB_FIRH_FIRHINC_MAX (0x00FFFFFFU)
14472 
14473 #define CSL_DSS_WB_FIRH_RESERVED_MASK (0xFF000000U)
14474 #define CSL_DSS_WB_FIRH_RESERVED_SHIFT (0x00000018U)
14475 #define CSL_DSS_WB_FIRH_RESERVED_MAX (0x000000FFU)
14476 
14477 /* FIRH2 */
14478 
14479 #define CSL_DSS_WB_FIRH2_FIRHINC_MASK (0x00FFFFFFU)
14480 #define CSL_DSS_WB_FIRH2_FIRHINC_SHIFT (0x00000000U)
14481 #define CSL_DSS_WB_FIRH2_FIRHINC_MAX (0x00FFFFFFU)
14482 
14483 #define CSL_DSS_WB_FIRH2_RESERVED_MASK (0xFF000000U)
14484 #define CSL_DSS_WB_FIRH2_RESERVED_SHIFT (0x00000018U)
14485 #define CSL_DSS_WB_FIRH2_RESERVED_MAX (0x000000FFU)
14486 
14487 /* FIRV */
14488 
14489 #define CSL_DSS_WB_FIRV_FIRVINC_MASK (0x00FFFFFFU)
14490 #define CSL_DSS_WB_FIRV_FIRVINC_SHIFT (0x00000000U)
14491 #define CSL_DSS_WB_FIRV_FIRVINC_MAX (0x00FFFFFFU)
14492 
14493 #define CSL_DSS_WB_FIRV_RESERVED_MASK (0xFF000000U)
14494 #define CSL_DSS_WB_FIRV_RESERVED_SHIFT (0x00000018U)
14495 #define CSL_DSS_WB_FIRV_RESERVED_MAX (0x000000FFU)
14496 
14497 /* FIRV2 */
14498 
14499 #define CSL_DSS_WB_FIRV2_FIRVINC_MASK (0x00FFFFFFU)
14500 #define CSL_DSS_WB_FIRV2_FIRVINC_SHIFT (0x00000000U)
14501 #define CSL_DSS_WB_FIRV2_FIRVINC_MAX (0x00FFFFFFU)
14502 
14503 #define CSL_DSS_WB_FIRV2_RESERVED_MASK (0xFF000000U)
14504 #define CSL_DSS_WB_FIRV2_RESERVED_SHIFT (0x00000018U)
14505 #define CSL_DSS_WB_FIRV2_RESERVED_MAX (0x000000FFU)
14506 
14507 /* FIR_COEF_H0 */
14508 
14509 #define CSL_DSS_WB_FIR_COEF_H0_FIRHC0_MASK (0x000003FFU)
14510 #define CSL_DSS_WB_FIR_COEF_H0_FIRHC0_SHIFT (0x00000000U)
14511 #define CSL_DSS_WB_FIR_COEF_H0_FIRHC0_MAX (0x000003FFU)
14512 
14513 #define CSL_DSS_WB_FIR_COEF_H0_RESERVED_MASK (0x3FFFFC00U)
14514 #define CSL_DSS_WB_FIR_COEF_H0_RESERVED_SHIFT (0x0000000AU)
14515 #define CSL_DSS_WB_FIR_COEF_H0_RESERVED_MAX (0x000FFFFFU)
14516 
14517 #define CSL_DSS_WB_FIR_COEF_H0_RESERVED1_MASK (0xC0000000U)
14518 #define CSL_DSS_WB_FIR_COEF_H0_RESERVED1_SHIFT (0x0000001EU)
14519 #define CSL_DSS_WB_FIR_COEF_H0_RESERVED1_MAX (0x00000003U)
14520 
14521 /* FIR_COEF_H0_C */
14522 
14523 #define CSL_DSS_WB_FIR_COEF_H0_C_FIRHC0_MASK (0x000003FFU)
14524 #define CSL_DSS_WB_FIR_COEF_H0_C_FIRHC0_SHIFT (0x00000000U)
14525 #define CSL_DSS_WB_FIR_COEF_H0_C_FIRHC0_MAX (0x000003FFU)
14526 
14527 #define CSL_DSS_WB_FIR_COEF_H0_C_RESERVED_MASK (0x3FFFFC00U)
14528 #define CSL_DSS_WB_FIR_COEF_H0_C_RESERVED_SHIFT (0x0000000AU)
14529 #define CSL_DSS_WB_FIR_COEF_H0_C_RESERVED_MAX (0x000FFFFFU)
14530 
14531 #define CSL_DSS_WB_FIR_COEF_H0_C_RESERVED1_MASK (0xC0000000U)
14532 #define CSL_DSS_WB_FIR_COEF_H0_C_RESERVED1_SHIFT (0x0000001EU)
14533 #define CSL_DSS_WB_FIR_COEF_H0_C_RESERVED1_MAX (0x00000003U)
14534 
14535 /* FIR_COEF_H12 */
14536 
14537 #define CSL_DSS_WB_FIR_COEF_H12_RESERVED_MASK (0x000003FFU)
14538 #define CSL_DSS_WB_FIR_COEF_H12_RESERVED_SHIFT (0x00000000U)
14539 #define CSL_DSS_WB_FIR_COEF_H12_RESERVED_MAX (0x000003FFU)
14540 
14541 #define CSL_DSS_WB_FIR_COEF_H12_FIRHC1_MASK (0x000FFC00U)
14542 #define CSL_DSS_WB_FIR_COEF_H12_FIRHC1_SHIFT (0x0000000AU)
14543 #define CSL_DSS_WB_FIR_COEF_H12_FIRHC1_MAX (0x000003FFU)
14544 
14545 #define CSL_DSS_WB_FIR_COEF_H12_FIRHC2_MASK (0x3FF00000U)
14546 #define CSL_DSS_WB_FIR_COEF_H12_FIRHC2_SHIFT (0x00000014U)
14547 #define CSL_DSS_WB_FIR_COEF_H12_FIRHC2_MAX (0x000003FFU)
14548 
14549 #define CSL_DSS_WB_FIR_COEF_H12_RESERVED1_MASK (0xC0000000U)
14550 #define CSL_DSS_WB_FIR_COEF_H12_RESERVED1_SHIFT (0x0000001EU)
14551 #define CSL_DSS_WB_FIR_COEF_H12_RESERVED1_MAX (0x00000003U)
14552 
14553 /* FIR_COEF_H12_C */
14554 
14555 #define CSL_DSS_WB_FIR_COEF_H12_C_RESERVED_MASK (0x000003FFU)
14556 #define CSL_DSS_WB_FIR_COEF_H12_C_RESERVED_SHIFT (0x00000000U)
14557 #define CSL_DSS_WB_FIR_COEF_H12_C_RESERVED_MAX (0x000003FFU)
14558 
14559 #define CSL_DSS_WB_FIR_COEF_H12_C_FIRHC1_MASK (0x000FFC00U)
14560 #define CSL_DSS_WB_FIR_COEF_H12_C_FIRHC1_SHIFT (0x0000000AU)
14561 #define CSL_DSS_WB_FIR_COEF_H12_C_FIRHC1_MAX (0x000003FFU)
14562 
14563 #define CSL_DSS_WB_FIR_COEF_H12_C_FIRHC2_MASK (0x3FF00000U)
14564 #define CSL_DSS_WB_FIR_COEF_H12_C_FIRHC2_SHIFT (0x00000014U)
14565 #define CSL_DSS_WB_FIR_COEF_H12_C_FIRHC2_MAX (0x000003FFU)
14566 
14567 #define CSL_DSS_WB_FIR_COEF_H12_C_RESERVED1_MASK (0xC0000000U)
14568 #define CSL_DSS_WB_FIR_COEF_H12_C_RESERVED1_SHIFT (0x0000001EU)
14569 #define CSL_DSS_WB_FIR_COEF_H12_C_RESERVED1_MAX (0x00000003U)
14570 
14571 /* FIR_COEF_V0 */
14572 
14573 #define CSL_DSS_WB_FIR_COEF_V0_FIRVC0_MASK (0x000003FFU)
14574 #define CSL_DSS_WB_FIR_COEF_V0_FIRVC0_SHIFT (0x00000000U)
14575 #define CSL_DSS_WB_FIR_COEF_V0_FIRVC0_MAX (0x000003FFU)
14576 
14577 #define CSL_DSS_WB_FIR_COEF_V0_RESERVED_MASK (0x3FFFFC00U)
14578 #define CSL_DSS_WB_FIR_COEF_V0_RESERVED_SHIFT (0x0000000AU)
14579 #define CSL_DSS_WB_FIR_COEF_V0_RESERVED_MAX (0x000FFFFFU)
14580 
14581 #define CSL_DSS_WB_FIR_COEF_V0_RESERVED1_MASK (0xC0000000U)
14582 #define CSL_DSS_WB_FIR_COEF_V0_RESERVED1_SHIFT (0x0000001EU)
14583 #define CSL_DSS_WB_FIR_COEF_V0_RESERVED1_MAX (0x00000003U)
14584 
14585 /* FIR_COEF_V0_C */
14586 
14587 #define CSL_DSS_WB_FIR_COEF_V0_C_FIRVC0_MASK (0x000003FFU)
14588 #define CSL_DSS_WB_FIR_COEF_V0_C_FIRVC0_SHIFT (0x00000000U)
14589 #define CSL_DSS_WB_FIR_COEF_V0_C_FIRVC0_MAX (0x000003FFU)
14590 
14591 #define CSL_DSS_WB_FIR_COEF_V0_C_RESERVED_MASK (0x3FFFFC00U)
14592 #define CSL_DSS_WB_FIR_COEF_V0_C_RESERVED_SHIFT (0x0000000AU)
14593 #define CSL_DSS_WB_FIR_COEF_V0_C_RESERVED_MAX (0x000FFFFFU)
14594 
14595 #define CSL_DSS_WB_FIR_COEF_V0_C_RESERVED1_MASK (0xC0000000U)
14596 #define CSL_DSS_WB_FIR_COEF_V0_C_RESERVED1_SHIFT (0x0000001EU)
14597 #define CSL_DSS_WB_FIR_COEF_V0_C_RESERVED1_MAX (0x00000003U)
14598 
14599 /* FIR_COEF_V12 */
14600 
14601 #define CSL_DSS_WB_FIR_COEF_V12_RESERVED_MASK (0x000003FFU)
14602 #define CSL_DSS_WB_FIR_COEF_V12_RESERVED_SHIFT (0x00000000U)
14603 #define CSL_DSS_WB_FIR_COEF_V12_RESERVED_MAX (0x000003FFU)
14604 
14605 #define CSL_DSS_WB_FIR_COEF_V12_FIRVC1_MASK (0x000FFC00U)
14606 #define CSL_DSS_WB_FIR_COEF_V12_FIRVC1_SHIFT (0x0000000AU)
14607 #define CSL_DSS_WB_FIR_COEF_V12_FIRVC1_MAX (0x000003FFU)
14608 
14609 #define CSL_DSS_WB_FIR_COEF_V12_FIRVC2_MASK (0x3FF00000U)
14610 #define CSL_DSS_WB_FIR_COEF_V12_FIRVC2_SHIFT (0x00000014U)
14611 #define CSL_DSS_WB_FIR_COEF_V12_FIRVC2_MAX (0x000003FFU)
14612 
14613 #define CSL_DSS_WB_FIR_COEF_V12_RESERVED1_MASK (0xC0000000U)
14614 #define CSL_DSS_WB_FIR_COEF_V12_RESERVED1_SHIFT (0x0000001EU)
14615 #define CSL_DSS_WB_FIR_COEF_V12_RESERVED1_MAX (0x00000003U)
14616 
14617 /* FIR_COEF_V12_C */
14618 
14619 #define CSL_DSS_WB_FIR_COEF_V12_C_RESERVED_MASK (0x000003FFU)
14620 #define CSL_DSS_WB_FIR_COEF_V12_C_RESERVED_SHIFT (0x00000000U)
14621 #define CSL_DSS_WB_FIR_COEF_V12_C_RESERVED_MAX (0x000003FFU)
14622 
14623 #define CSL_DSS_WB_FIR_COEF_V12_C_FIRVC1_MASK (0x000FFC00U)
14624 #define CSL_DSS_WB_FIR_COEF_V12_C_FIRVC1_SHIFT (0x0000000AU)
14625 #define CSL_DSS_WB_FIR_COEF_V12_C_FIRVC1_MAX (0x000003FFU)
14626 
14627 #define CSL_DSS_WB_FIR_COEF_V12_C_FIRVC2_MASK (0x3FF00000U)
14628 #define CSL_DSS_WB_FIR_COEF_V12_C_FIRVC2_SHIFT (0x00000014U)
14629 #define CSL_DSS_WB_FIR_COEF_V12_C_FIRVC2_MAX (0x000003FFU)
14630 
14631 #define CSL_DSS_WB_FIR_COEF_V12_C_RESERVED1_MASK (0xC0000000U)
14632 #define CSL_DSS_WB_FIR_COEF_V12_C_RESERVED1_SHIFT (0x0000001EU)
14633 #define CSL_DSS_WB_FIR_COEF_V12_C_RESERVED1_MAX (0x00000003U)
14634 
14635 /* MFLAG_THRESHOLD */
14636 
14637 #define CSL_DSS_WB_MFLAG_THRESHOLD_LT_MFLAG_MASK (0x0000FFFFU)
14638 #define CSL_DSS_WB_MFLAG_THRESHOLD_LT_MFLAG_SHIFT (0x00000000U)
14639 #define CSL_DSS_WB_MFLAG_THRESHOLD_LT_MFLAG_MAX (0x0000FFFFU)
14640 
14641 #define CSL_DSS_WB_MFLAG_THRESHOLD_HT_MFLAG_MASK (0xFFFF0000U)
14642 #define CSL_DSS_WB_MFLAG_THRESHOLD_HT_MFLAG_SHIFT (0x00000010U)
14643 #define CSL_DSS_WB_MFLAG_THRESHOLD_HT_MFLAG_MAX (0x0000FFFFU)
14644 
14645 /* PICTURE_SIZE */
14646 
14647 #define CSL_DSS_WB_PICTURE_SIZE_MEMSIZEX_MASK (0x00003FFFU)
14648 #define CSL_DSS_WB_PICTURE_SIZE_MEMSIZEX_SHIFT (0x00000000U)
14649 #define CSL_DSS_WB_PICTURE_SIZE_MEMSIZEX_MAX (0x00003FFFU)
14650 
14651 #define CSL_DSS_WB_PICTURE_SIZE_MEMSIZEY_MASK (0x3FFF0000U)
14652 #define CSL_DSS_WB_PICTURE_SIZE_MEMSIZEY_SHIFT (0x00000010U)
14653 #define CSL_DSS_WB_PICTURE_SIZE_MEMSIZEY_MAX (0x00003FFFU)
14654 
14655 /* SIZE */
14656 
14657 #define CSL_DSS_WB_SIZE_SIZEX_MASK (0x00003FFFU)
14658 #define CSL_DSS_WB_SIZE_SIZEX_SHIFT (0x00000000U)
14659 #define CSL_DSS_WB_SIZE_SIZEX_MAX (0x00003FFFU)
14660 
14661 #define CSL_DSS_WB_SIZE_SIZEY_MASK (0x3FFF0000U)
14662 #define CSL_DSS_WB_SIZE_SIZEY_SHIFT (0x00000010U)
14663 #define CSL_DSS_WB_SIZE_SIZEY_MAX (0x00003FFFU)
14664 
14665 /* POSITION */
14666 
14667 #define CSL_DSS_WB_POSITION_POSX_MASK (0x00003FFFU)
14668 #define CSL_DSS_WB_POSITION_POSX_SHIFT (0x00000000U)
14669 #define CSL_DSS_WB_POSITION_POSX_MAX (0x00003FFFU)
14670 
14671 #define CSL_DSS_WB_POSITION_RESERVED_MASK (0x0000C000U)
14672 #define CSL_DSS_WB_POSITION_RESERVED_SHIFT (0x0000000EU)
14673 #define CSL_DSS_WB_POSITION_RESERVED_MAX (0x00000003U)
14674 
14675 #define CSL_DSS_WB_POSITION_POSY_MASK (0x3FFF0000U)
14676 #define CSL_DSS_WB_POSITION_POSY_SHIFT (0x00000010U)
14677 #define CSL_DSS_WB_POSITION_POSY_MAX (0x00003FFFU)
14678 
14679 #define CSL_DSS_WB_POSITION_RESERVED1_MASK (0xC0000000U)
14680 #define CSL_DSS_WB_POSITION_RESERVED1_SHIFT (0x0000001EU)
14681 #define CSL_DSS_WB_POSITION_RESERVED1_MAX (0x00000003U)
14682 
14683 /* CSC_COEF7 */
14684 
14685 #define CSL_DSS_WB_CSC_COEF7_RESERVED_MASK (0x00000007U)
14686 #define CSL_DSS_WB_CSC_COEF7_RESERVED_SHIFT (0x00000000U)
14687 #define CSL_DSS_WB_CSC_COEF7_RESERVED_MAX (0x00000007U)
14688 
14689 #define CSL_DSS_WB_CSC_COEF7_POSTOFFSET2_MASK (0x0000FFF8U)
14690 #define CSL_DSS_WB_CSC_COEF7_POSTOFFSET2_SHIFT (0x00000003U)
14691 #define CSL_DSS_WB_CSC_COEF7_POSTOFFSET2_MAX (0x00001FFFU)
14692 
14693 #define CSL_DSS_WB_CSC_COEF7_RESERVED1_MASK (0x00070000U)
14694 #define CSL_DSS_WB_CSC_COEF7_RESERVED1_SHIFT (0x00000010U)
14695 #define CSL_DSS_WB_CSC_COEF7_RESERVED1_MAX (0x00000007U)
14696 
14697 #define CSL_DSS_WB_CSC_COEF7_POSTOFFSET3_MASK (0xFFF80000U)
14698 #define CSL_DSS_WB_CSC_COEF7_POSTOFFSET3_SHIFT (0x00000013U)
14699 #define CSL_DSS_WB_CSC_COEF7_POSTOFFSET3_MAX (0x00001FFFU)
14700 
14701 /* ROW_INC */
14702 
14703 #define CSL_DSS_WB_ROW_INC_ROWINC_MASK (0xFFFFFFFFU)
14704 #define CSL_DSS_WB_ROW_INC_ROWINC_SHIFT (0x00000000U)
14705 #define CSL_DSS_WB_ROW_INC_ROWINC_MAX (0xFFFFFFFFU)
14706 
14707 /* ROW_INC_UV */
14708 
14709 #define CSL_DSS_WB_ROW_INC_UV_ROWINC_MASK (0xFFFFFFFFU)
14710 #define CSL_DSS_WB_ROW_INC_UV_ROWINC_SHIFT (0x00000000U)
14711 #define CSL_DSS_WB_ROW_INC_UV_ROWINC_MAX (0xFFFFFFFFU)
14712 
14713 /* BA_EXT_0 */
14714 
14715 #define CSL_DSS_WB_BA_EXT_0_BA_EXT_MASK (0x0000FFFFU)
14716 #define CSL_DSS_WB_BA_EXT_0_BA_EXT_SHIFT (0x00000000U)
14717 #define CSL_DSS_WB_BA_EXT_0_BA_EXT_MAX (0x0000FFFFU)
14718 
14719 #define CSL_DSS_WB_BA_EXT_0_RESERVED_MASK (0xFFFF0000U)
14720 #define CSL_DSS_WB_BA_EXT_0_RESERVED_SHIFT (0x00000010U)
14721 #define CSL_DSS_WB_BA_EXT_0_RESERVED_MAX (0x0000FFFFU)
14722 
14723 /* BA_EXT_1 */
14724 
14725 #define CSL_DSS_WB_BA_EXT_1_BA_EXT_MASK (0x0000FFFFU)
14726 #define CSL_DSS_WB_BA_EXT_1_BA_EXT_SHIFT (0x00000000U)
14727 #define CSL_DSS_WB_BA_EXT_1_BA_EXT_MAX (0x0000FFFFU)
14728 
14729 #define CSL_DSS_WB_BA_EXT_1_RESERVED_MASK (0xFFFF0000U)
14730 #define CSL_DSS_WB_BA_EXT_1_RESERVED_SHIFT (0x00000010U)
14731 #define CSL_DSS_WB_BA_EXT_1_RESERVED_MAX (0x0000FFFFU)
14732 
14733 /* BA_UV_EXT_0 */
14734 
14735 #define CSL_DSS_WB_BA_UV_EXT_0_BA_UV_EXT_MASK (0x0000FFFFU)
14736 #define CSL_DSS_WB_BA_UV_EXT_0_BA_UV_EXT_SHIFT (0x00000000U)
14737 #define CSL_DSS_WB_BA_UV_EXT_0_BA_UV_EXT_MAX (0x0000FFFFU)
14738 
14739 #define CSL_DSS_WB_BA_UV_EXT_0_RESERVED_MASK (0xFFFF0000U)
14740 #define CSL_DSS_WB_BA_UV_EXT_0_RESERVED_SHIFT (0x00000010U)
14741 #define CSL_DSS_WB_BA_UV_EXT_0_RESERVED_MAX (0x0000FFFFU)
14742 
14743 /* BA_UV_EXT_1 */
14744 
14745 #define CSL_DSS_WB_BA_UV_EXT_1_BA_UV_EXT_MASK (0x0000FFFFU)
14746 #define CSL_DSS_WB_BA_UV_EXT_1_BA_UV_EXT_SHIFT (0x00000000U)
14747 #define CSL_DSS_WB_BA_UV_EXT_1_BA_UV_EXT_MAX (0x0000FFFFU)
14748 
14749 #define CSL_DSS_WB_BA_UV_EXT_1_RESERVED_MASK (0xFFFF0000U)
14750 #define CSL_DSS_WB_BA_UV_EXT_1_RESERVED_SHIFT (0x00000010U)
14751 #define CSL_DSS_WB_BA_UV_EXT_1_RESERVED_MAX (0x0000FFFFU)
14752 
14753 /* SECURE */
14754 
14755 #define CSL_DSS_WB_SECURE_SECURE_MASK (0x00000001U)
14756 #define CSL_DSS_WB_SECURE_SECURE_SHIFT (0x00000000U)
14757 #define CSL_DSS_WB_SECURE_SECURE_MAX (0x00000001U)
14758 
14759 #define CSL_DSS_WB_SECURE_SECURE_VAL_SECUREDIS (0x0U)
14760 #define CSL_DSS_WB_SECURE_SECURE_VAL_SECUREEN (0x1U)
14761 
14762 #define CSL_DSS_WB_SECURE_RESERVED_MASK (0xFFFFFFFEU)
14763 #define CSL_DSS_WB_SECURE_RESERVED_SHIFT (0x00000001U)
14764 #define CSL_DSS_WB_SECURE_RESERVED_MAX (0x7FFFFFFFU)
14765 
14766 /**************************************************************************
14767 * Hardware Region : COMMON_S1 Registers
14768 **************************************************************************/
14769 
14770 
14771 /**************************************************************************
14772 * Register Overlay Structure
14773 **************************************************************************/
14774 
14775 typedef struct {
14776  volatile uint8_t Resv_40[40];
14777  volatile uint32_t DISPC_IRQSTATUS_RAW; /* DISPC_IRQSTATUS_RAW */
14778  volatile uint32_t DISPC_IRQSTATUS; /* DISPC_IRQSTATUS */
14779  volatile uint32_t DISPC_IRQENABLE_SET; /* DISPC_IRQENABLE_SET */
14780  volatile uint32_t DISPC_IRQENABLE_CLR; /* DISPC_IRQENABLE_CLR */
14781  volatile uint32_t VID_IRQENABLE_0; /* VID_IRQENABLE_0 */
14782  volatile uint32_t VID_IRQENABLE_1; /* VID_IRQENABLE_1 */
14783  volatile uint32_t VID_IRQENABLE_2; /* VID_IRQENABLE_2 */
14784  volatile uint32_t VID_IRQENABLE_3; /* VID_IRQENABLE_3 */
14785  volatile uint32_t VID_IRQSTATUS_0; /* VID_IRQSTATUS_0 */
14786  volatile uint32_t VID_IRQSTATUS_1; /* VID_IRQSTATUS_1 */
14787  volatile uint32_t VID_IRQSTATUS_2; /* VID_IRQSTATUS_2 */
14788  volatile uint32_t VID_IRQSTATUS_3; /* VID_IRQSTATUS_3 */
14789  volatile uint32_t VP_IRQENABLE_0; /* VP_IRQENABLE_0 */
14790  volatile uint32_t VP_IRQENABLE_1; /* VP_IRQENABLE_1 */
14791  volatile uint32_t VP_IRQENABLE_2; /* VP_IRQENABLE_2 */
14792  volatile uint32_t VP_IRQENABLE_3; /* VP_IRQENABLE_3 */
14793  volatile uint32_t VP_IRQSTATUS_0; /* VP_IRQSTATUS_0 */
14794  volatile uint32_t VP_IRQSTATUS_1; /* VP_IRQSTATUS_1 */
14795  volatile uint32_t VP_IRQSTATUS_2; /* VP_IRQSTATUS_2 */
14796  volatile uint32_t VP_IRQSTATUS_3; /* VP_IRQSTATUS_3 */
14797  volatile uint32_t WB_IRQENABLE; /* WB_IRQENABLE */
14798  volatile uint32_t WB_IRQSTATUS; /* WB_IRQSTATUS */
14799  volatile uint32_t DISPC_IRQ_EOI_FUNC; /* DISPC_IRQ_EOI_FUNC */
14800  volatile uint32_t DISPC_IRQ_EOI_SAFETY; /* DISPC_IRQ_EOI_SAFETY */
14801  volatile uint32_t DISPC_IRQ_EOI_SECURITY; /* DISPC_IRQ_EOI_SECURITY */
14803 
14804 
14805 /**************************************************************************
14806 * Register Macros
14807 **************************************************************************/
14808 
14809 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW (0x00000028U)
14810 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS (0x0000002CU)
14811 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET (0x00000030U)
14812 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR (0x00000034U)
14813 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0 (0x00000038U)
14814 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1 (0x0000003CU)
14815 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2 (0x00000040U)
14816 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3 (0x00000044U)
14817 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0 (0x00000048U)
14818 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1 (0x0000004CU)
14819 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2 (0x00000050U)
14820 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3 (0x00000054U)
14821 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0 (0x00000058U)
14822 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1 (0x0000005CU)
14823 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2 (0x00000060U)
14824 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3 (0x00000064U)
14825 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0 (0x00000068U)
14826 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1 (0x0000006CU)
14827 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2 (0x00000070U)
14828 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3 (0x00000074U)
14829 #define CSL_DSS_COMMON_S1_WB_IRQENABLE (0x00000078U)
14830 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS (0x0000007CU)
14831 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_FUNC (0x00000080U)
14832 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_SAFETY (0x00000084U)
14833 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_SECURITY (0x00000088U)
14834 
14835 /**************************************************************************
14836 * Field Definition Macros
14837 **************************************************************************/
14838 
14839 
14840 /* DISPC_IRQSTATUS_RAW */
14841 
14842 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_VP_IRQ_MASK (0x0000000FU)
14843 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_VP_IRQ_SHIFT (0x00000000U)
14844 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_VP_IRQ_MAX (0x0000000FU)
14845 
14846 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_VP_IRQ_VAL_NOACTION (0x0U)
14847 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_VP_IRQ_VAL_SET_EVENT (0x1U)
14848 
14849 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_VID_IRQ_MASK (0x000000F0U)
14850 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_VID_IRQ_SHIFT (0x00000004U)
14851 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_VID_IRQ_MAX (0x0000000FU)
14852 
14853 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_VID_IRQ_VAL_NOACTION (0x0U)
14854 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_VID_IRQ_VAL_SET_EVENT (0x1U)
14855 
14856 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_RESERVED_VID_MASK (0x00001F00U)
14857 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_RESERVED_VID_SHIFT (0x00000008U)
14858 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_RESERVED_VID_MAX (0x0000001FU)
14859 
14860 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_RESERVED_CUR_MASK (0x00002000U)
14861 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_RESERVED_CUR_SHIFT (0x0000000DU)
14862 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_RESERVED_CUR_MAX (0x00000001U)
14863 
14864 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_WB_IRQ_MASK (0x00004000U)
14865 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_WB_IRQ_SHIFT (0x0000000EU)
14866 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_WB_IRQ_MAX (0x00000001U)
14867 
14868 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_WB_IRQ_VAL_NOACTION (0x0U)
14869 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_WB_IRQ_VAL_SET_EVENT (0x1U)
14870 
14871 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_DUMMY1_IRQ_MASK (0x00008000U)
14872 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_DUMMY1_IRQ_SHIFT (0x0000000FU)
14873 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_DUMMY1_IRQ_MAX (0x00000001U)
14874 
14875 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_DUMMY1_IRQ_VAL_NOACTION (0x0U)
14876 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_DUMMY1_IRQ_VAL_SET_EVENT (0x1U)
14877 
14878 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_DUMMY_IRQ_MASK (0x00010000U)
14879 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_DUMMY_IRQ_SHIFT (0x00000010U)
14880 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_DUMMY_IRQ_MAX (0x00000001U)
14881 
14882 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_DUMMY_IRQ_VAL_NOACTION (0x0U)
14883 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_DUMMY_IRQ_VAL_SET_EVENT (0x1U)
14884 
14885 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_RESERVED_MASK (0xFFFE0000U)
14886 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_RESERVED_SHIFT (0x00000011U)
14887 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RAW_RESERVED_MAX (0x00007FFFU)
14888 
14889 /* DISPC_IRQSTATUS */
14890 
14891 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_VP_IRQ_MASK (0x0000000FU)
14892 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_VP_IRQ_SHIFT (0x00000000U)
14893 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_VP_IRQ_MAX (0x0000000FU)
14894 
14895 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_VP_IRQ_VAL_NOACTION (0x0U)
14896 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_VP_IRQ_VAL_CLEAR (0x1U)
14897 
14898 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_VID_IRQ_MASK (0x000000F0U)
14899 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_VID_IRQ_SHIFT (0x00000004U)
14900 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_VID_IRQ_MAX (0x0000000FU)
14901 
14902 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_VID_IRQ_VAL_NOACTION (0x0U)
14903 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_VID_IRQ_VAL_CLEAR (0x1U)
14904 
14905 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RESERVED_VID_MASK (0x00001F00U)
14906 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RESERVED_VID_SHIFT (0x00000008U)
14907 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RESERVED_VID_MAX (0x0000001FU)
14908 
14909 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RESERVED_CUR_MASK (0x00002000U)
14910 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RESERVED_CUR_SHIFT (0x0000000DU)
14911 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RESERVED_CUR_MAX (0x00000001U)
14912 
14913 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_WB_IRQ_MASK (0x00004000U)
14914 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_WB_IRQ_SHIFT (0x0000000EU)
14915 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_WB_IRQ_MAX (0x00000001U)
14916 
14917 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_WB_IRQ_VAL_NOACTION (0x0U)
14918 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_WB_IRQ_VAL_CLEAR (0x1U)
14919 
14920 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_DUMMY1_IRQ_MASK (0x00008000U)
14921 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_DUMMY1_IRQ_SHIFT (0x0000000FU)
14922 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_DUMMY1_IRQ_MAX (0x00000001U)
14923 
14924 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_DUMMY1_IRQ_VAL_NOACTION (0x0U)
14925 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_DUMMY1_IRQ_VAL_CLEAR (0x1U)
14926 
14927 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_DUMMY_IRQ_MASK (0x00010000U)
14928 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_DUMMY_IRQ_SHIFT (0x00000010U)
14929 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_DUMMY_IRQ_MAX (0x00000001U)
14930 
14931 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_DUMMY_IRQ_VAL_NOACTION (0x0U)
14932 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_DUMMY_IRQ_VAL_CLEAR (0x1U)
14933 
14934 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RESERVED_MASK (0xFFFE0000U)
14935 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RESERVED_SHIFT (0x00000011U)
14936 #define CSL_DSS_COMMON_S1_DISPC_IRQSTATUS_RESERVED_MAX (0x00007FFFU)
14937 
14938 /* DISPC_IRQENABLE_SET */
14939 
14940 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_SET_VP_IRQ_MASK (0x0000000FU)
14941 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_SET_VP_IRQ_SHIFT (0x00000000U)
14942 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_SET_VP_IRQ_MAX (0x0000000FU)
14943 
14944 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_SET_VP_IRQ_VAL_NOACTION (0x0U)
14945 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_SET_VP_IRQ_VAL_ENABLE (0x1U)
14946 
14947 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_SET_VID_IRQ_MASK (0x000000F0U)
14948 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_SET_VID_IRQ_SHIFT (0x00000004U)
14949 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_SET_VID_IRQ_MAX (0x0000000FU)
14950 
14951 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_SET_VID_IRQ_VAL_NOACTION (0x0U)
14952 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_SET_VID_IRQ_VAL_ENABLE (0x1U)
14953 
14954 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_RESERVED_VID_MASK (0x00001F00U)
14955 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_RESERVED_VID_SHIFT (0x00000008U)
14956 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_RESERVED_VID_MAX (0x0000001FU)
14957 
14958 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_RESERVED_CUR_MASK (0x00002000U)
14959 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_RESERVED_CUR_SHIFT (0x0000000DU)
14960 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_RESERVED_CUR_MAX (0x00000001U)
14961 
14962 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_SET_WB_IRQ_MASK (0x00004000U)
14963 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_SET_WB_IRQ_SHIFT (0x0000000EU)
14964 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_SET_WB_IRQ_MAX (0x00000001U)
14965 
14966 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_SET_WB_IRQ_VAL_NOACTION (0x0U)
14967 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_SET_WB_IRQ_VAL_ENABLE (0x1U)
14968 
14969 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_SET_DUMMY1_IRQ_MASK (0x00008000U)
14970 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_SET_DUMMY1_IRQ_SHIFT (0x0000000FU)
14971 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_SET_DUMMY1_IRQ_MAX (0x00000001U)
14972 
14973 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_SET_DUMMY1_IRQ_VAL_NOACTION (0x0U)
14974 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_SET_DUMMY1_IRQ_VAL_ENABLE (0x1U)
14975 
14976 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_SET_DUMMY_IRQ_MASK (0x00010000U)
14977 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_SET_DUMMY_IRQ_SHIFT (0x00000010U)
14978 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_SET_DUMMY_IRQ_MAX (0x00000001U)
14979 
14980 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_SET_DUMMY_IRQ_VAL_NOACTION (0x0U)
14981 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_SET_DUMMY_IRQ_VAL_ENABLE (0x1U)
14982 
14983 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_RESERVED_MASK (0xFFFE0000U)
14984 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_RESERVED_SHIFT (0x00000011U)
14985 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_SET_RESERVED_MAX (0x00007FFFU)
14986 
14987 /* DISPC_IRQENABLE_CLR */
14988 
14989 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_MASK (0x0000000FU)
14990 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_SHIFT (0x00000000U)
14991 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_MAX (0x0000000FU)
14992 
14993 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_VAL_NOACTION (0x0U)
14994 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_VAL_CLEAR (0x1U)
14995 
14996 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_MASK (0x000000F0U)
14997 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_SHIFT (0x00000004U)
14998 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_MAX (0x0000000FU)
14999 
15000 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_VAL_NOACTION (0x0U)
15001 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_VAL_CLEAR (0x1U)
15002 
15003 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_RESERVED_VID_MASK (0x00001F00U)
15004 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_RESERVED_VID_SHIFT (0x00000008U)
15005 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_RESERVED_VID_MAX (0x0000001FU)
15006 
15007 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_RESERVED_CUR_MASK (0x00002000U)
15008 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_RESERVED_CUR_SHIFT (0x0000000DU)
15009 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_RESERVED_CUR_MAX (0x00000001U)
15010 
15011 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_CLR_WB_IRQ_MASK (0x00004000U)
15012 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_CLR_WB_IRQ_SHIFT (0x0000000EU)
15013 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_CLR_WB_IRQ_MAX (0x00000001U)
15014 
15015 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_CLR_WB_IRQ_VAL_NOACTION (0x0U)
15016 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_CLR_WB_IRQ_VAL_CLEAR (0x1U)
15017 
15018 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_CLR_DUMMY1_IRQ_MASK (0x00008000U)
15019 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_CLR_DUMMY1_IRQ_SHIFT (0x0000000FU)
15020 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_CLR_DUMMY1_IRQ_MAX (0x00000001U)
15021 
15022 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_CLR_DUMMY1_IRQ_VAL_NOACTION (0x0U)
15023 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_CLR_DUMMY1_IRQ_VAL_CLEAR (0x1U)
15024 
15025 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_CLR_DUMMY_IRQ_MASK (0x00010000U)
15026 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_CLR_DUMMY_IRQ_SHIFT (0x00000010U)
15027 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_CLR_DUMMY_IRQ_MAX (0x00000001U)
15028 
15029 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_CLR_DUMMY_IRQ_VAL_NOACTION (0x0U)
15030 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_CLR_DUMMY_IRQ_VAL_CLEAR (0x1U)
15031 
15032 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_RESERVED_MASK (0xFFFE0000U)
15033 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_RESERVED_SHIFT (0x00000011U)
15034 #define CSL_DSS_COMMON_S1_DISPC_IRQENABLE_CLR_RESERVED_MAX (0x00007FFFU)
15035 
15036 /* VID_IRQENABLE_0 */
15037 
15038 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_MASK (0x00000001U)
15039 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_SHIFT (0x00000000U)
15040 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_MAX (0x00000001U)
15041 
15042 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_VAL_MASKED (0x0U)
15043 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_VAL_GENINT (0x1U)
15044 
15045 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_VIDENDWINDOW_EN_MASK (0x00000002U)
15046 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_VIDENDWINDOW_EN_SHIFT (0x00000001U)
15047 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_VIDENDWINDOW_EN_MAX (0x00000001U)
15048 
15049 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_VIDENDWINDOW_EN_VAL_MASKED (0x0U)
15050 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_VIDENDWINDOW_EN_VAL_GENINT (0x1U)
15051 
15052 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_SAFETYREGION_EN_MASK (0x00000004U)
15053 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_SAFETYREGION_EN_SHIFT (0x00000002U)
15054 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_SAFETYREGION_EN_MAX (0x00000001U)
15055 
15056 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_SAFETYREGION_EN_VAL_MASKED (0x0U)
15057 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_SAFETYREGION_EN_VAL_GENINT (0x1U)
15058 
15059 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_FBDC_CORRUPTTILE_EN_MASK (0x00000008U)
15060 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_FBDC_CORRUPTTILE_EN_SHIFT (0x00000003U)
15061 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_FBDC_CORRUPTTILE_EN_MAX (0x00000001U)
15062 
15063 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_FBDC_CORRUPTTILE_EN_VAL_MASKED (0x0U)
15064 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_FBDC_CORRUPTTILE_EN_VAL_GENINT (0x1U)
15065 
15066 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_FBDC_ILLEGALTILEREQ_EN_MASK (0x00000010U)
15067 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_FBDC_ILLEGALTILEREQ_EN_SHIFT (0x00000004U)
15068 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_FBDC_ILLEGALTILEREQ_EN_MAX (0x00000001U)
15069 
15070 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_FBDC_ILLEGALTILEREQ_EN_VAL_MASKED (0x0U)
15071 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_FBDC_ILLEGALTILEREQ_EN_VAL_GENINT (0x1U)
15072 
15073 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_RESERVED_MASK (0xFFFFFFE0U)
15074 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_RESERVED_SHIFT (0x00000005U)
15075 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_0_RESERVED_MAX (0x07FFFFFFU)
15076 
15077 /* VID_IRQENABLE_1 */
15078 
15079 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_MASK (0x00000001U)
15080 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_SHIFT (0x00000000U)
15081 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_MAX (0x00000001U)
15082 
15083 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_VAL_MASKED (0x0U)
15084 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_VAL_GENINT (0x1U)
15085 
15086 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_VIDENDWINDOW_EN_MASK (0x00000002U)
15087 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_VIDENDWINDOW_EN_SHIFT (0x00000001U)
15088 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_VIDENDWINDOW_EN_MAX (0x00000001U)
15089 
15090 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_VIDENDWINDOW_EN_VAL_MASKED (0x0U)
15091 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_VIDENDWINDOW_EN_VAL_GENINT (0x1U)
15092 
15093 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_SAFETYREGION_EN_MASK (0x00000004U)
15094 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_SAFETYREGION_EN_SHIFT (0x00000002U)
15095 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_SAFETYREGION_EN_MAX (0x00000001U)
15096 
15097 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_SAFETYREGION_EN_VAL_MASKED (0x0U)
15098 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_SAFETYREGION_EN_VAL_GENINT (0x1U)
15099 
15100 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_FBDC_CORRUPTTILE_EN_MASK (0x00000008U)
15101 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_FBDC_CORRUPTTILE_EN_SHIFT (0x00000003U)
15102 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_FBDC_CORRUPTTILE_EN_MAX (0x00000001U)
15103 
15104 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_FBDC_CORRUPTTILE_EN_VAL_MASKED (0x0U)
15105 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_FBDC_CORRUPTTILE_EN_VAL_GENINT (0x1U)
15106 
15107 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_FBDC_ILLEGALTILEREQ_EN_MASK (0x00000010U)
15108 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_FBDC_ILLEGALTILEREQ_EN_SHIFT (0x00000004U)
15109 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_FBDC_ILLEGALTILEREQ_EN_MAX (0x00000001U)
15110 
15111 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_FBDC_ILLEGALTILEREQ_EN_VAL_MASKED (0x0U)
15112 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_FBDC_ILLEGALTILEREQ_EN_VAL_GENINT (0x1U)
15113 
15114 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_RESERVED_MASK (0xFFFFFFE0U)
15115 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_RESERVED_SHIFT (0x00000005U)
15116 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_1_RESERVED_MAX (0x07FFFFFFU)
15117 
15118 /* VID_IRQENABLE_2 */
15119 
15120 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_VIDBUFFERUNDERFLOW_EN_MASK (0x00000001U)
15121 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_VIDBUFFERUNDERFLOW_EN_SHIFT (0x00000000U)
15122 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_VIDBUFFERUNDERFLOW_EN_MAX (0x00000001U)
15123 
15124 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_VIDBUFFERUNDERFLOW_EN_VAL_MASKED (0x0U)
15125 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_VIDBUFFERUNDERFLOW_EN_VAL_GENINT (0x1U)
15126 
15127 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_VIDENDWINDOW_EN_MASK (0x00000002U)
15128 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_VIDENDWINDOW_EN_SHIFT (0x00000001U)
15129 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_VIDENDWINDOW_EN_MAX (0x00000001U)
15130 
15131 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_VIDENDWINDOW_EN_VAL_MASKED (0x0U)
15132 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_VIDENDWINDOW_EN_VAL_GENINT (0x1U)
15133 
15134 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_SAFETYREGION_EN_MASK (0x00000004U)
15135 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_SAFETYREGION_EN_SHIFT (0x00000002U)
15136 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_SAFETYREGION_EN_MAX (0x00000001U)
15137 
15138 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_SAFETYREGION_EN_VAL_MASKED (0x0U)
15139 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_SAFETYREGION_EN_VAL_GENINT (0x1U)
15140 
15141 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_FBDC_CORRUPTTILE_EN_MASK (0x00000008U)
15142 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_FBDC_CORRUPTTILE_EN_SHIFT (0x00000003U)
15143 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_FBDC_CORRUPTTILE_EN_MAX (0x00000001U)
15144 
15145 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_FBDC_CORRUPTTILE_EN_VAL_MASKED (0x0U)
15146 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_FBDC_CORRUPTTILE_EN_VAL_GENINT (0x1U)
15147 
15148 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_FBDC_ILLEGALTILEREQ_EN_MASK (0x00000010U)
15149 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_FBDC_ILLEGALTILEREQ_EN_SHIFT (0x00000004U)
15150 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_FBDC_ILLEGALTILEREQ_EN_MAX (0x00000001U)
15151 
15152 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_FBDC_ILLEGALTILEREQ_EN_VAL_MASKED (0x0U)
15153 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_FBDC_ILLEGALTILEREQ_EN_VAL_GENINT (0x1U)
15154 
15155 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_RESERVED_MASK (0xFFFFFFE0U)
15156 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_RESERVED_SHIFT (0x00000005U)
15157 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_2_RESERVED_MAX (0x07FFFFFFU)
15158 
15159 /* VID_IRQENABLE_3 */
15160 
15161 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_VIDBUFFERUNDERFLOW_EN_MASK (0x00000001U)
15162 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_VIDBUFFERUNDERFLOW_EN_SHIFT (0x00000000U)
15163 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_VIDBUFFERUNDERFLOW_EN_MAX (0x00000001U)
15164 
15165 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_VIDBUFFERUNDERFLOW_EN_VAL_MASKED (0x0U)
15166 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_VIDBUFFERUNDERFLOW_EN_VAL_GENINT (0x1U)
15167 
15168 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_VIDENDWINDOW_EN_MASK (0x00000002U)
15169 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_VIDENDWINDOW_EN_SHIFT (0x00000001U)
15170 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_VIDENDWINDOW_EN_MAX (0x00000001U)
15171 
15172 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_VIDENDWINDOW_EN_VAL_MASKED (0x0U)
15173 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_VIDENDWINDOW_EN_VAL_GENINT (0x1U)
15174 
15175 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_SAFETYREGION_EN_MASK (0x00000004U)
15176 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_SAFETYREGION_EN_SHIFT (0x00000002U)
15177 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_SAFETYREGION_EN_MAX (0x00000001U)
15178 
15179 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_SAFETYREGION_EN_VAL_MASKED (0x0U)
15180 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_SAFETYREGION_EN_VAL_GENINT (0x1U)
15181 
15182 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_FBDC_CORRUPTTILE_EN_MASK (0x00000008U)
15183 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_FBDC_CORRUPTTILE_EN_SHIFT (0x00000003U)
15184 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_FBDC_CORRUPTTILE_EN_MAX (0x00000001U)
15185 
15186 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_FBDC_CORRUPTTILE_EN_VAL_MASKED (0x0U)
15187 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_FBDC_CORRUPTTILE_EN_VAL_GENINT (0x1U)
15188 
15189 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_FBDC_ILLEGALTILEREQ_EN_MASK (0x00000010U)
15190 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_FBDC_ILLEGALTILEREQ_EN_SHIFT (0x00000004U)
15191 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_FBDC_ILLEGALTILEREQ_EN_MAX (0x00000001U)
15192 
15193 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_FBDC_ILLEGALTILEREQ_EN_VAL_MASKED (0x0U)
15194 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_FBDC_ILLEGALTILEREQ_EN_VAL_GENINT (0x1U)
15195 
15196 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_RESERVED_MASK (0xFFFFFFE0U)
15197 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_RESERVED_SHIFT (0x00000005U)
15198 #define CSL_DSS_COMMON_S1_VID_IRQENABLE_3_RESERVED_MAX (0x07FFFFFFU)
15199 
15200 /* VID_IRQSTATUS_0 */
15201 
15202 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_MASK (0x00000001U)
15203 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_SHIFT (0x00000000U)
15204 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_MAX (0x00000001U)
15205 
15206 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_VAL_NOPEND (0x0U)
15207 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_VAL_PEND (0x1U)
15208 
15209 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_MASK (0x00000002U)
15210 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_SHIFT (0x00000001U)
15211 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_MAX (0x00000001U)
15212 
15213 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_VAL_NOPEND (0x0U)
15214 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_VAL_PEND (0x1U)
15215 
15216 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_SAFETYREGION_IRQ_MASK (0x00000004U)
15217 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_SAFETYREGION_IRQ_SHIFT (0x00000002U)
15218 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_SAFETYREGION_IRQ_MAX (0x00000001U)
15219 
15220 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
15221 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_PEND (0x1U)
15222 
15223 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_FBDC_CORRUPTTILE_IRQ_MASK (0x00000008U)
15224 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_FBDC_CORRUPTTILE_IRQ_SHIFT (0x00000003U)
15225 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_FBDC_CORRUPTTILE_IRQ_MAX (0x00000001U)
15226 
15227 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_FBDC_CORRUPTTILE_IRQ_VAL_NOPEND (0x0U)
15228 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_FBDC_CORRUPTTILE_IRQ_VAL_PEND (0x1U)
15229 
15230 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_FBDC_ILLEGALTILEREQ_IRQ_MASK (0x00000010U)
15231 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_FBDC_ILLEGALTILEREQ_IRQ_SHIFT (0x00000004U)
15232 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_FBDC_ILLEGALTILEREQ_IRQ_MAX (0x00000001U)
15233 
15234 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_FBDC_ILLEGALTILEREQ_IRQ_VAL_NOPEND (0x0U)
15235 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_FBDC_ILLEGALTILEREQ_IRQ_VAL_PEND (0x1U)
15236 
15237 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_RESERVED_MASK (0xFFFFFFE0U)
15238 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_RESERVED_SHIFT (0x00000005U)
15239 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_0_RESERVED_MAX (0x07FFFFFFU)
15240 
15241 /* VID_IRQSTATUS_1 */
15242 
15243 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_MASK (0x00000001U)
15244 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_SHIFT (0x00000000U)
15245 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_MAX (0x00000001U)
15246 
15247 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_VAL_NOPEND (0x0U)
15248 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_VAL_PEND (0x1U)
15249 
15250 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_MASK (0x00000002U)
15251 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_SHIFT (0x00000001U)
15252 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_MAX (0x00000001U)
15253 
15254 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_VAL_NOPEND (0x0U)
15255 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_VAL_PEND (0x1U)
15256 
15257 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_SAFETYREGION_IRQ_MASK (0x00000004U)
15258 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_SAFETYREGION_IRQ_SHIFT (0x00000002U)
15259 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_SAFETYREGION_IRQ_MAX (0x00000001U)
15260 
15261 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
15262 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_PEND (0x1U)
15263 
15264 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_FBDC_CORRUPTTILE_IRQ_MASK (0x00000008U)
15265 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_FBDC_CORRUPTTILE_IRQ_SHIFT (0x00000003U)
15266 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_FBDC_CORRUPTTILE_IRQ_MAX (0x00000001U)
15267 
15268 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_FBDC_CORRUPTTILE_IRQ_VAL_NOPEND (0x0U)
15269 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_FBDC_CORRUPTTILE_IRQ_VAL_PEND (0x1U)
15270 
15271 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_FBDC_ILLEGALTILEREQ_IRQ_MASK (0x00000010U)
15272 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_FBDC_ILLEGALTILEREQ_IRQ_SHIFT (0x00000004U)
15273 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_FBDC_ILLEGALTILEREQ_IRQ_MAX (0x00000001U)
15274 
15275 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_FBDC_ILLEGALTILEREQ_IRQ_VAL_NOPEND (0x0U)
15276 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_FBDC_ILLEGALTILEREQ_IRQ_VAL_PEND (0x1U)
15277 
15278 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_RESERVED_MASK (0xFFFFFFE0U)
15279 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_RESERVED_SHIFT (0x00000005U)
15280 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_1_RESERVED_MAX (0x07FFFFFFU)
15281 
15282 /* VID_IRQSTATUS_2 */
15283 
15284 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_VIDBUFFERUNDERFLOW_IRQ_MASK (0x00000001U)
15285 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_VIDBUFFERUNDERFLOW_IRQ_SHIFT (0x00000000U)
15286 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_VIDBUFFERUNDERFLOW_IRQ_MAX (0x00000001U)
15287 
15288 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_VIDBUFFERUNDERFLOW_IRQ_VAL_NOPEND (0x0U)
15289 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_VIDBUFFERUNDERFLOW_IRQ_VAL_PEND (0x1U)
15290 
15291 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_VIDENDWINDOW_IRQ_MASK (0x00000002U)
15292 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_VIDENDWINDOW_IRQ_SHIFT (0x00000001U)
15293 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_VIDENDWINDOW_IRQ_MAX (0x00000001U)
15294 
15295 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_VIDENDWINDOW_IRQ_VAL_NOPEND (0x0U)
15296 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_VIDENDWINDOW_IRQ_VAL_PEND (0x1U)
15297 
15298 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_SAFETYREGION_IRQ_MASK (0x00000004U)
15299 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_SAFETYREGION_IRQ_SHIFT (0x00000002U)
15300 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_SAFETYREGION_IRQ_MAX (0x00000001U)
15301 
15302 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
15303 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_SAFETYREGION_IRQ_VAL_PEND (0x1U)
15304 
15305 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_FBDC_CORRUPTTILE_IRQ_MASK (0x00000008U)
15306 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_FBDC_CORRUPTTILE_IRQ_SHIFT (0x00000003U)
15307 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_FBDC_CORRUPTTILE_IRQ_MAX (0x00000001U)
15308 
15309 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_FBDC_CORRUPTTILE_IRQ_VAL_NOPEND (0x0U)
15310 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_FBDC_CORRUPTTILE_IRQ_VAL_PEND (0x1U)
15311 
15312 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_FBDC_ILLEGALTILEREQ_IRQ_MASK (0x00000010U)
15313 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_FBDC_ILLEGALTILEREQ_IRQ_SHIFT (0x00000004U)
15314 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_FBDC_ILLEGALTILEREQ_IRQ_MAX (0x00000001U)
15315 
15316 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_FBDC_ILLEGALTILEREQ_IRQ_VAL_NOPEND (0x0U)
15317 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_FBDC_ILLEGALTILEREQ_IRQ_VAL_PEND (0x1U)
15318 
15319 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_RESERVED_MASK (0xFFFFFFE0U)
15320 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_RESERVED_SHIFT (0x00000005U)
15321 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_2_RESERVED_MAX (0x07FFFFFFU)
15322 
15323 /* VID_IRQSTATUS_3 */
15324 
15325 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_VIDBUFFERUNDERFLOW_IRQ_MASK (0x00000001U)
15326 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_VIDBUFFERUNDERFLOW_IRQ_SHIFT (0x00000000U)
15327 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_VIDBUFFERUNDERFLOW_IRQ_MAX (0x00000001U)
15328 
15329 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_VIDBUFFERUNDERFLOW_IRQ_VAL_NOPEND (0x0U)
15330 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_VIDBUFFERUNDERFLOW_IRQ_VAL_PEND (0x1U)
15331 
15332 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_VIDENDWINDOW_IRQ_MASK (0x00000002U)
15333 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_VIDENDWINDOW_IRQ_SHIFT (0x00000001U)
15334 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_VIDENDWINDOW_IRQ_MAX (0x00000001U)
15335 
15336 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_VIDENDWINDOW_IRQ_VAL_NOPEND (0x0U)
15337 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_VIDENDWINDOW_IRQ_VAL_PEND (0x1U)
15338 
15339 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_SAFETYREGION_IRQ_MASK (0x00000004U)
15340 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_SAFETYREGION_IRQ_SHIFT (0x00000002U)
15341 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_SAFETYREGION_IRQ_MAX (0x00000001U)
15342 
15343 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
15344 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_SAFETYREGION_IRQ_VAL_PEND (0x1U)
15345 
15346 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_FBDC_CORRUPTTILE_IRQ_MASK (0x00000008U)
15347 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_FBDC_CORRUPTTILE_IRQ_SHIFT (0x00000003U)
15348 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_FBDC_CORRUPTTILE_IRQ_MAX (0x00000001U)
15349 
15350 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_FBDC_CORRUPTTILE_IRQ_VAL_NOPEND (0x0U)
15351 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_FBDC_CORRUPTTILE_IRQ_VAL_PEND (0x1U)
15352 
15353 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_FBDC_ILLEGALTILEREQ_IRQ_MASK (0x00000010U)
15354 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_FBDC_ILLEGALTILEREQ_IRQ_SHIFT (0x00000004U)
15355 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_FBDC_ILLEGALTILEREQ_IRQ_MAX (0x00000001U)
15356 
15357 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_FBDC_ILLEGALTILEREQ_IRQ_VAL_NOPEND (0x0U)
15358 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_FBDC_ILLEGALTILEREQ_IRQ_VAL_PEND (0x1U)
15359 
15360 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_RESERVED_MASK (0xFFFFFFE0U)
15361 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_RESERVED_SHIFT (0x00000005U)
15362 #define CSL_DSS_COMMON_S1_VID_IRQSTATUS_3_RESERVED_MAX (0x07FFFFFFU)
15363 
15364 /* VP_IRQENABLE_0 */
15365 
15366 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPFRAMEDONE_EN_MASK (0x00000001U)
15367 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPFRAMEDONE_EN_SHIFT (0x00000000U)
15368 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPFRAMEDONE_EN_MAX (0x00000001U)
15369 
15370 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPFRAMEDONE_EN_VAL_MASKED (0x0U)
15371 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPFRAMEDONE_EN_VAL_GENINT (0x1U)
15372 
15373 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPVSYNC_EN_MASK (0x00000002U)
15374 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPVSYNC_EN_SHIFT (0x00000001U)
15375 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPVSYNC_EN_MAX (0x00000001U)
15376 
15377 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPVSYNC_EN_VAL_MASKED (0x0U)
15378 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPVSYNC_EN_VAL_GENINT (0x1U)
15379 
15380 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPVSYNC_ODD_EN_MASK (0x00000004U)
15381 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPVSYNC_ODD_EN_SHIFT (0x00000002U)
15382 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPVSYNC_ODD_EN_MAX (0x00000001U)
15383 
15384 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPVSYNC_ODD_EN_VAL_MASKED (0x0U)
15385 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPVSYNC_ODD_EN_VAL_GENINT (0x1U)
15386 
15387 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_MASK (0x00000008U)
15388 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_SHIFT (0x00000003U)
15389 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_MAX (0x00000001U)
15390 
15391 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_VAL_MASKED (0x0U)
15392 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_VAL_GENINT (0x1U)
15393 
15394 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPSYNCLOST_EN_MASK (0x00000010U)
15395 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPSYNCLOST_EN_SHIFT (0x00000004U)
15396 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPSYNCLOST_EN_MAX (0x00000001U)
15397 
15398 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPSYNCLOST_EN_VAL_MASKED (0x0U)
15399 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPSYNCLOST_EN_VAL_GENINT (0x1U)
15400 
15401 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_MASK (0x00000020U)
15402 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_SHIFT (0x00000005U)
15403 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_MAX (0x00000001U)
15404 
15405 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_VAL_MASKED (0x0U)
15406 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_VAL_GENINT (0x1U)
15407 
15408 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_SAFETYREGION_EN_MASK (0x000003C0U)
15409 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_SAFETYREGION_EN_SHIFT (0x00000006U)
15410 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_SAFETYREGION_EN_MAX (0x0000000FU)
15411 
15412 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_SAFETYREGION_EN_VAL_MASKED (0x0U)
15413 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_SAFETYREGION_EN_VAL_GENINT (0x1U)
15414 
15415 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_SECURITYVIOLATION_EN_MASK (0x00000400U)
15416 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_SECURITYVIOLATION_EN_SHIFT (0x0000000AU)
15417 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_SECURITYVIOLATION_EN_MAX (0x00000001U)
15418 
15419 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
15420 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
15421 
15422 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPSYNC_EN_MASK (0x00000800U)
15423 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPSYNC_EN_SHIFT (0x0000000BU)
15424 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPSYNC_EN_MAX (0x00000001U)
15425 
15426 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPSYNC_EN_VAL_MASKED (0x0U)
15427 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_VPSYNC_EN_VAL_GENINT (0x1U)
15428 
15429 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_DUMMY_EN_MASK (0x00001000U)
15430 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_DUMMY_EN_SHIFT (0x0000000CU)
15431 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_DUMMY_EN_MAX (0x00000001U)
15432 
15433 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_DUMMY_EN_VAL_MASKED (0x0U)
15434 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_DUMMY_EN_VAL_GENINT (0x1U)
15435 
15436 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_SAFETYREGION1_EN_MASK (0x0001E000U)
15437 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_SAFETYREGION1_EN_SHIFT (0x0000000DU)
15438 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_SAFETYREGION1_EN_MAX (0x0000000FU)
15439 
15440 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_SAFETYREGION1_EN_VAL_MASKED (0x0U)
15441 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_SAFETYREGION1_EN_VAL_GENINT (0x1U)
15442 
15443 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_RESERVED_MASK (0xFFFE0000U)
15444 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_RESERVED_SHIFT (0x00000011U)
15445 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_0_RESERVED_MAX (0x00007FFFU)
15446 
15447 /* VP_IRQENABLE_1 */
15448 
15449 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPFRAMEDONE_EN_MASK (0x00000001U)
15450 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPFRAMEDONE_EN_SHIFT (0x00000000U)
15451 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPFRAMEDONE_EN_MAX (0x00000001U)
15452 
15453 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPFRAMEDONE_EN_VAL_MASKED (0x0U)
15454 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPFRAMEDONE_EN_VAL_GENINT (0x1U)
15455 
15456 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPVSYNC_EN_MASK (0x00000002U)
15457 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPVSYNC_EN_SHIFT (0x00000001U)
15458 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPVSYNC_EN_MAX (0x00000001U)
15459 
15460 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPVSYNC_EN_VAL_MASKED (0x0U)
15461 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPVSYNC_EN_VAL_GENINT (0x1U)
15462 
15463 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPVSYNC_ODD_EN_MASK (0x00000004U)
15464 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPVSYNC_ODD_EN_SHIFT (0x00000002U)
15465 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPVSYNC_ODD_EN_MAX (0x00000001U)
15466 
15467 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPVSYNC_ODD_EN_VAL_MASKED (0x0U)
15468 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPVSYNC_ODD_EN_VAL_GENINT (0x1U)
15469 
15470 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_MASK (0x00000008U)
15471 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_SHIFT (0x00000003U)
15472 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_MAX (0x00000001U)
15473 
15474 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_VAL_MASKED (0x0U)
15475 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_VAL_GENINT (0x1U)
15476 
15477 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPSYNCLOST_EN_MASK (0x00000010U)
15478 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPSYNCLOST_EN_SHIFT (0x00000004U)
15479 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPSYNCLOST_EN_MAX (0x00000001U)
15480 
15481 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPSYNCLOST_EN_VAL_MASKED (0x0U)
15482 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPSYNCLOST_EN_VAL_GENINT (0x1U)
15483 
15484 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_MASK (0x00000020U)
15485 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_SHIFT (0x00000005U)
15486 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_MAX (0x00000001U)
15487 
15488 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_VAL_MASKED (0x0U)
15489 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_VAL_GENINT (0x1U)
15490 
15491 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_SAFETYREGION_EN_MASK (0x000003C0U)
15492 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_SAFETYREGION_EN_SHIFT (0x00000006U)
15493 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_SAFETYREGION_EN_MAX (0x0000000FU)
15494 
15495 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_SAFETYREGION_EN_VAL_MASKED (0x0U)
15496 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_SAFETYREGION_EN_VAL_GENINT (0x1U)
15497 
15498 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_SECURITYVIOLATION_EN_MASK (0x00000400U)
15499 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_SECURITYVIOLATION_EN_SHIFT (0x0000000AU)
15500 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_SECURITYVIOLATION_EN_MAX (0x00000001U)
15501 
15502 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
15503 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
15504 
15505 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPSYNC_EN_MASK (0x00000800U)
15506 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPSYNC_EN_SHIFT (0x0000000BU)
15507 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPSYNC_EN_MAX (0x00000001U)
15508 
15509 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPSYNC_EN_VAL_MASKED (0x0U)
15510 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_VPSYNC_EN_VAL_GENINT (0x1U)
15511 
15512 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_DUMMY_EN_MASK (0x00001000U)
15513 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_DUMMY_EN_SHIFT (0x0000000CU)
15514 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_DUMMY_EN_MAX (0x00000001U)
15515 
15516 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_DUMMY_EN_VAL_MASKED (0x0U)
15517 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_DUMMY_EN_VAL_GENINT (0x1U)
15518 
15519 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_SAFETYREGION1_EN_MASK (0x0001E000U)
15520 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_SAFETYREGION1_EN_SHIFT (0x0000000DU)
15521 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_SAFETYREGION1_EN_MAX (0x0000000FU)
15522 
15523 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_SAFETYREGION1_EN_VAL_MASKED (0x0U)
15524 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_SAFETYREGION1_EN_VAL_GENINT (0x1U)
15525 
15526 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_RESERVED_MASK (0xFFFE0000U)
15527 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_RESERVED_SHIFT (0x00000011U)
15528 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_1_RESERVED_MAX (0x00007FFFU)
15529 
15530 /* VP_IRQENABLE_2 */
15531 
15532 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPFRAMEDONE_EN_MASK (0x00000001U)
15533 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPFRAMEDONE_EN_SHIFT (0x00000000U)
15534 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPFRAMEDONE_EN_MAX (0x00000001U)
15535 
15536 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPFRAMEDONE_EN_VAL_MASKED (0x0U)
15537 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPFRAMEDONE_EN_VAL_GENINT (0x1U)
15538 
15539 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPVSYNC_EN_MASK (0x00000002U)
15540 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPVSYNC_EN_SHIFT (0x00000001U)
15541 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPVSYNC_EN_MAX (0x00000001U)
15542 
15543 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPVSYNC_EN_VAL_MASKED (0x0U)
15544 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPVSYNC_EN_VAL_GENINT (0x1U)
15545 
15546 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPVSYNC_ODD_EN_MASK (0x00000004U)
15547 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPVSYNC_ODD_EN_SHIFT (0x00000002U)
15548 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPVSYNC_ODD_EN_MAX (0x00000001U)
15549 
15550 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPVSYNC_ODD_EN_VAL_MASKED (0x0U)
15551 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPVSYNC_ODD_EN_VAL_GENINT (0x1U)
15552 
15553 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPPROGRAMMEDLINENUMBER_EN_MASK (0x00000008U)
15554 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPPROGRAMMEDLINENUMBER_EN_SHIFT (0x00000003U)
15555 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPPROGRAMMEDLINENUMBER_EN_MAX (0x00000001U)
15556 
15557 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPPROGRAMMEDLINENUMBER_EN_VAL_MASKED (0x0U)
15558 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPPROGRAMMEDLINENUMBER_EN_VAL_GENINT (0x1U)
15559 
15560 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPSYNCLOST_EN_MASK (0x00000010U)
15561 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPSYNCLOST_EN_SHIFT (0x00000004U)
15562 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPSYNCLOST_EN_MAX (0x00000001U)
15563 
15564 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPSYNCLOST_EN_VAL_MASKED (0x0U)
15565 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPSYNCLOST_EN_VAL_GENINT (0x1U)
15566 
15567 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_ACBIASCOUNTSTATUS_EN_MASK (0x00000020U)
15568 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_ACBIASCOUNTSTATUS_EN_SHIFT (0x00000005U)
15569 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_ACBIASCOUNTSTATUS_EN_MAX (0x00000001U)
15570 
15571 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_ACBIASCOUNTSTATUS_EN_VAL_MASKED (0x0U)
15572 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_ACBIASCOUNTSTATUS_EN_VAL_GENINT (0x1U)
15573 
15574 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_SAFETYREGION_EN_MASK (0x000003C0U)
15575 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_SAFETYREGION_EN_SHIFT (0x00000006U)
15576 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_SAFETYREGION_EN_MAX (0x0000000FU)
15577 
15578 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_SAFETYREGION_EN_VAL_MASKED (0x0U)
15579 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_SAFETYREGION_EN_VAL_GENINT (0x1U)
15580 
15581 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_SECURITYVIOLATION_EN_MASK (0x00000400U)
15582 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_SECURITYVIOLATION_EN_SHIFT (0x0000000AU)
15583 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_SECURITYVIOLATION_EN_MAX (0x00000001U)
15584 
15585 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
15586 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
15587 
15588 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPSYNC_EN_MASK (0x00000800U)
15589 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPSYNC_EN_SHIFT (0x0000000BU)
15590 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPSYNC_EN_MAX (0x00000001U)
15591 
15592 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPSYNC_EN_VAL_MASKED (0x0U)
15593 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_VPSYNC_EN_VAL_GENINT (0x1U)
15594 
15595 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_DUMMY_EN_MASK (0x00001000U)
15596 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_DUMMY_EN_SHIFT (0x0000000CU)
15597 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_DUMMY_EN_MAX (0x00000001U)
15598 
15599 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_DUMMY_EN_VAL_MASKED (0x0U)
15600 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_DUMMY_EN_VAL_GENINT (0x1U)
15601 
15602 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_SAFETYREGION1_EN_MASK (0x0001E000U)
15603 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_SAFETYREGION1_EN_SHIFT (0x0000000DU)
15604 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_SAFETYREGION1_EN_MAX (0x0000000FU)
15605 
15606 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_SAFETYREGION1_EN_VAL_MASKED (0x0U)
15607 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_SAFETYREGION1_EN_VAL_GENINT (0x1U)
15608 
15609 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_RESERVED_MASK (0xFFFE0000U)
15610 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_RESERVED_SHIFT (0x00000011U)
15611 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_2_RESERVED_MAX (0x00007FFFU)
15612 
15613 /* VP_IRQENABLE_3 */
15614 
15615 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPFRAMEDONE_EN_MASK (0x00000001U)
15616 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPFRAMEDONE_EN_SHIFT (0x00000000U)
15617 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPFRAMEDONE_EN_MAX (0x00000001U)
15618 
15619 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPFRAMEDONE_EN_VAL_MASKED (0x0U)
15620 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPFRAMEDONE_EN_VAL_GENINT (0x1U)
15621 
15622 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPVSYNC_EN_MASK (0x00000002U)
15623 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPVSYNC_EN_SHIFT (0x00000001U)
15624 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPVSYNC_EN_MAX (0x00000001U)
15625 
15626 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPVSYNC_EN_VAL_MASKED (0x0U)
15627 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPVSYNC_EN_VAL_GENINT (0x1U)
15628 
15629 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPVSYNC_ODD_EN_MASK (0x00000004U)
15630 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPVSYNC_ODD_EN_SHIFT (0x00000002U)
15631 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPVSYNC_ODD_EN_MAX (0x00000001U)
15632 
15633 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPVSYNC_ODD_EN_VAL_MASKED (0x0U)
15634 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPVSYNC_ODD_EN_VAL_GENINT (0x1U)
15635 
15636 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPPROGRAMMEDLINENUMBER_EN_MASK (0x00000008U)
15637 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPPROGRAMMEDLINENUMBER_EN_SHIFT (0x00000003U)
15638 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPPROGRAMMEDLINENUMBER_EN_MAX (0x00000001U)
15639 
15640 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPPROGRAMMEDLINENUMBER_EN_VAL_MASKED (0x0U)
15641 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPPROGRAMMEDLINENUMBER_EN_VAL_GENINT (0x1U)
15642 
15643 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPSYNCLOST_EN_MASK (0x00000010U)
15644 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPSYNCLOST_EN_SHIFT (0x00000004U)
15645 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPSYNCLOST_EN_MAX (0x00000001U)
15646 
15647 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPSYNCLOST_EN_VAL_MASKED (0x0U)
15648 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPSYNCLOST_EN_VAL_GENINT (0x1U)
15649 
15650 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_ACBIASCOUNTSTATUS_EN_MASK (0x00000020U)
15651 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_ACBIASCOUNTSTATUS_EN_SHIFT (0x00000005U)
15652 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_ACBIASCOUNTSTATUS_EN_MAX (0x00000001U)
15653 
15654 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_ACBIASCOUNTSTATUS_EN_VAL_MASKED (0x0U)
15655 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_ACBIASCOUNTSTATUS_EN_VAL_GENINT (0x1U)
15656 
15657 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_SAFETYREGION_EN_MASK (0x000003C0U)
15658 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_SAFETYREGION_EN_SHIFT (0x00000006U)
15659 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_SAFETYREGION_EN_MAX (0x0000000FU)
15660 
15661 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_SAFETYREGION_EN_VAL_MASKED (0x0U)
15662 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_SAFETYREGION_EN_VAL_GENINT (0x1U)
15663 
15664 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_SECURITYVIOLATION_EN_MASK (0x00000400U)
15665 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_SECURITYVIOLATION_EN_SHIFT (0x0000000AU)
15666 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_SECURITYVIOLATION_EN_MAX (0x00000001U)
15667 
15668 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
15669 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
15670 
15671 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPSYNC_EN_MASK (0x00000800U)
15672 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPSYNC_EN_SHIFT (0x0000000BU)
15673 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPSYNC_EN_MAX (0x00000001U)
15674 
15675 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPSYNC_EN_VAL_MASKED (0x0U)
15676 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_VPSYNC_EN_VAL_GENINT (0x1U)
15677 
15678 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_DUMMY_EN_MASK (0x00001000U)
15679 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_DUMMY_EN_SHIFT (0x0000000CU)
15680 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_DUMMY_EN_MAX (0x00000001U)
15681 
15682 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_DUMMY_EN_VAL_MASKED (0x0U)
15683 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_DUMMY_EN_VAL_GENINT (0x1U)
15684 
15685 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_SAFETYREGION1_EN_MASK (0x0001E000U)
15686 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_SAFETYREGION1_EN_SHIFT (0x0000000DU)
15687 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_SAFETYREGION1_EN_MAX (0x0000000FU)
15688 
15689 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_SAFETYREGION1_EN_VAL_MASKED (0x0U)
15690 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_SAFETYREGION1_EN_VAL_GENINT (0x1U)
15691 
15692 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_RESERVED_MASK (0xFFFE0000U)
15693 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_RESERVED_SHIFT (0x00000011U)
15694 #define CSL_DSS_COMMON_S1_VP_IRQENABLE_3_RESERVED_MAX (0x00007FFFU)
15695 
15696 /* VP_IRQSTATUS_0 */
15697 
15698 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_MASK (0x00000001U)
15699 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_SHIFT (0x00000000U)
15700 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_MAX (0x00000001U)
15701 
15702 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
15703 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_VAL_PEND (0x1U)
15704 
15705 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPVSYNC_IRQ_MASK (0x00000002U)
15706 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPVSYNC_IRQ_SHIFT (0x00000001U)
15707 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPVSYNC_IRQ_MAX (0x00000001U)
15708 
15709 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPVSYNC_IRQ_VAL_NOPEND (0x0U)
15710 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPVSYNC_IRQ_VAL_PEND (0x1U)
15711 
15712 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_MASK (0x00000004U)
15713 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_SHIFT (0x00000002U)
15714 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_MAX (0x00000001U)
15715 
15716 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_VAL_NOPEND (0x0U)
15717 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_VAL_PEND (0x1U)
15718 
15719 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_MASK (0x00000008U)
15720 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_SHIFT (0x00000003U)
15721 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_MAX (0x00000001U)
15722 
15723 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_VAL_NOPEND (0x0U)
15724 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_VAL_PEND (0x1U)
15725 
15726 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_MASK (0x00000010U)
15727 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_SHIFT (0x00000004U)
15728 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_MAX (0x00000001U)
15729 
15730 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_VAL_NOPEND (0x0U)
15731 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_VAL_PEND (0x1U)
15732 
15733 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_MASK (0x00000020U)
15734 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_SHIFT (0x00000005U)
15735 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_MAX (0x00000001U)
15736 
15737 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_VAL_NOPEND (0x0U)
15738 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_VAL_PEND (0x1U)
15739 
15740 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_SAFETYREGION_IRQ_MASK (0x000003C0U)
15741 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_SAFETYREGION_IRQ_SHIFT (0x00000006U)
15742 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_SAFETYREGION_IRQ_MAX (0x0000000FU)
15743 
15744 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
15745 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_PEND (0x1U)
15746 
15747 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_MASK (0x00000400U)
15748 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_SHIFT (0x0000000AU)
15749 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
15750 
15751 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
15752 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
15753 
15754 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPSYNC_IRQ_MASK (0x00000800U)
15755 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPSYNC_IRQ_SHIFT (0x0000000BU)
15756 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPSYNC_IRQ_MAX (0x00000001U)
15757 
15758 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPSYNC_IRQ_VAL_NOPEND (0x0U)
15759 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_VPSYNC_IRQ_VAL_PEND (0x1U)
15760 
15761 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_DUMMY_IRQ_MASK (0x00001000U)
15762 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_DUMMY_IRQ_SHIFT (0x0000000CU)
15763 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_DUMMY_IRQ_MAX (0x00000001U)
15764 
15765 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_DUMMY_IRQ_VAL_NOPEND (0x0U)
15766 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_DUMMY_IRQ_VAL_PEND (0x1U)
15767 
15768 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_SAFETYREGION1_IRQ_MASK (0x0001E000U)
15769 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_SAFETYREGION1_IRQ_SHIFT (0x0000000DU)
15770 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_SAFETYREGION1_IRQ_MAX (0x0000000FU)
15771 
15772 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_SAFETYREGION1_IRQ_VAL_NOPEND (0x0U)
15773 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_SAFETYREGION1_IRQ_VAL_PEND (0x1U)
15774 
15775 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_RESERVED_MASK (0xFFFE0000U)
15776 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_RESERVED_SHIFT (0x00000011U)
15777 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_0_RESERVED_MAX (0x00007FFFU)
15778 
15779 /* VP_IRQSTATUS_1 */
15780 
15781 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_MASK (0x00000001U)
15782 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_SHIFT (0x00000000U)
15783 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_MAX (0x00000001U)
15784 
15785 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
15786 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_VAL_PEND (0x1U)
15787 
15788 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPVSYNC_IRQ_MASK (0x00000002U)
15789 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPVSYNC_IRQ_SHIFT (0x00000001U)
15790 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPVSYNC_IRQ_MAX (0x00000001U)
15791 
15792 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPVSYNC_IRQ_VAL_NOPEND (0x0U)
15793 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPVSYNC_IRQ_VAL_PEND (0x1U)
15794 
15795 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_MASK (0x00000004U)
15796 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_SHIFT (0x00000002U)
15797 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_MAX (0x00000001U)
15798 
15799 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_VAL_NOPEND (0x0U)
15800 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_VAL_PEND (0x1U)
15801 
15802 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_MASK (0x00000008U)
15803 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_SHIFT (0x00000003U)
15804 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_MAX (0x00000001U)
15805 
15806 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_VAL_NOPEND (0x0U)
15807 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_VAL_PEND (0x1U)
15808 
15809 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_MASK (0x00000010U)
15810 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_SHIFT (0x00000004U)
15811 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_MAX (0x00000001U)
15812 
15813 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_VAL_NOPEND (0x0U)
15814 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_VAL_PEND (0x1U)
15815 
15816 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_MASK (0x00000020U)
15817 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_SHIFT (0x00000005U)
15818 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_MAX (0x00000001U)
15819 
15820 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_VAL_NOPEND (0x0U)
15821 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_VAL_PEND (0x1U)
15822 
15823 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_SAFETYREGION_IRQ_MASK (0x000003C0U)
15824 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_SAFETYREGION_IRQ_SHIFT (0x00000006U)
15825 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_SAFETYREGION_IRQ_MAX (0x0000000FU)
15826 
15827 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
15828 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_PEND (0x1U)
15829 
15830 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_MASK (0x00000400U)
15831 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_SHIFT (0x0000000AU)
15832 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
15833 
15834 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
15835 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
15836 
15837 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPSYNC_IRQ_MASK (0x00000800U)
15838 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPSYNC_IRQ_SHIFT (0x0000000BU)
15839 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPSYNC_IRQ_MAX (0x00000001U)
15840 
15841 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPSYNC_IRQ_VAL_NOPEND (0x0U)
15842 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_VPSYNC_IRQ_VAL_PEND (0x1U)
15843 
15844 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_DUMMY_IRQ_MASK (0x00001000U)
15845 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_DUMMY_IRQ_SHIFT (0x0000000CU)
15846 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_DUMMY_IRQ_MAX (0x00000001U)
15847 
15848 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_DUMMY_IRQ_VAL_NOPEND (0x0U)
15849 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_DUMMY_IRQ_VAL_PEND (0x1U)
15850 
15851 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_SAFETYREGION1_IRQ_MASK (0x0001E000U)
15852 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_SAFETYREGION1_IRQ_SHIFT (0x0000000DU)
15853 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_SAFETYREGION1_IRQ_MAX (0x0000000FU)
15854 
15855 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_SAFETYREGION1_IRQ_VAL_NOPEND (0x0U)
15856 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_SAFETYREGION1_IRQ_VAL_PEND (0x1U)
15857 
15858 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_RESERVED_MASK (0xFFFE0000U)
15859 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_RESERVED_SHIFT (0x00000011U)
15860 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_1_RESERVED_MAX (0x00007FFFU)
15861 
15862 /* VP_IRQSTATUS_2 */
15863 
15864 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPFRAMEDONE_IRQ_MASK (0x00000001U)
15865 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPFRAMEDONE_IRQ_SHIFT (0x00000000U)
15866 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPFRAMEDONE_IRQ_MAX (0x00000001U)
15867 
15868 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
15869 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPFRAMEDONE_IRQ_VAL_PEND (0x1U)
15870 
15871 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPVSYNC_IRQ_MASK (0x00000002U)
15872 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPVSYNC_IRQ_SHIFT (0x00000001U)
15873 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPVSYNC_IRQ_MAX (0x00000001U)
15874 
15875 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPVSYNC_IRQ_VAL_NOPEND (0x0U)
15876 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPVSYNC_IRQ_VAL_PEND (0x1U)
15877 
15878 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPVSYNC_ODD_IRQ_MASK (0x00000004U)
15879 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPVSYNC_ODD_IRQ_SHIFT (0x00000002U)
15880 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPVSYNC_ODD_IRQ_MAX (0x00000001U)
15881 
15882 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPVSYNC_ODD_IRQ_VAL_NOPEND (0x0U)
15883 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPVSYNC_ODD_IRQ_VAL_PEND (0x1U)
15884 
15885 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPPROGRAMMEDLINENUMBER_IRQ_MASK (0x00000008U)
15886 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPPROGRAMMEDLINENUMBER_IRQ_SHIFT (0x00000003U)
15887 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPPROGRAMMEDLINENUMBER_IRQ_MAX (0x00000001U)
15888 
15889 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPPROGRAMMEDLINENUMBER_IRQ_VAL_NOPEND (0x0U)
15890 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPPROGRAMMEDLINENUMBER_IRQ_VAL_PEND (0x1U)
15891 
15892 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPSYNCLOST_IRQ_MASK (0x00000010U)
15893 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPSYNCLOST_IRQ_SHIFT (0x00000004U)
15894 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPSYNCLOST_IRQ_MAX (0x00000001U)
15895 
15896 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPSYNCLOST_IRQ_VAL_NOPEND (0x0U)
15897 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPSYNCLOST_IRQ_VAL_PEND (0x1U)
15898 
15899 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_ACBIASCOUNTSTATUS_IRQ_MASK (0x00000020U)
15900 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_ACBIASCOUNTSTATUS_IRQ_SHIFT (0x00000005U)
15901 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_ACBIASCOUNTSTATUS_IRQ_MAX (0x00000001U)
15902 
15903 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_ACBIASCOUNTSTATUS_IRQ_VAL_NOPEND (0x0U)
15904 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_ACBIASCOUNTSTATUS_IRQ_VAL_PEND (0x1U)
15905 
15906 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_SAFETYREGION_IRQ_MASK (0x000003C0U)
15907 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_SAFETYREGION_IRQ_SHIFT (0x00000006U)
15908 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_SAFETYREGION_IRQ_MAX (0x0000000FU)
15909 
15910 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
15911 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_SAFETYREGION_IRQ_VAL_PEND (0x1U)
15912 
15913 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_SECURITYVIOLATION_IRQ_MASK (0x00000400U)
15914 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_SECURITYVIOLATION_IRQ_SHIFT (0x0000000AU)
15915 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
15916 
15917 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
15918 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
15919 
15920 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPSYNC_IRQ_MASK (0x00000800U)
15921 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPSYNC_IRQ_SHIFT (0x0000000BU)
15922 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPSYNC_IRQ_MAX (0x00000001U)
15923 
15924 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPSYNC_IRQ_VAL_NOPEND (0x0U)
15925 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_VPSYNC_IRQ_VAL_PEND (0x1U)
15926 
15927 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_DUMMY_IRQ_MASK (0x00001000U)
15928 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_DUMMY_IRQ_SHIFT (0x0000000CU)
15929 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_DUMMY_IRQ_MAX (0x00000001U)
15930 
15931 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_DUMMY_IRQ_VAL_NOPEND (0x0U)
15932 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_DUMMY_IRQ_VAL_PEND (0x1U)
15933 
15934 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_SAFETYREGION1_IRQ_MASK (0x0001E000U)
15935 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_SAFETYREGION1_IRQ_SHIFT (0x0000000DU)
15936 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_SAFETYREGION1_IRQ_MAX (0x0000000FU)
15937 
15938 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_SAFETYREGION1_IRQ_VAL_NOPEND (0x0U)
15939 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_SAFETYREGION1_IRQ_VAL_PEND (0x1U)
15940 
15941 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_RESERVED_MASK (0xFFFE0000U)
15942 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_RESERVED_SHIFT (0x00000011U)
15943 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_2_RESERVED_MAX (0x00007FFFU)
15944 
15945 /* VP_IRQSTATUS_3 */
15946 
15947 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPFRAMEDONE_IRQ_MASK (0x00000001U)
15948 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPFRAMEDONE_IRQ_SHIFT (0x00000000U)
15949 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPFRAMEDONE_IRQ_MAX (0x00000001U)
15950 
15951 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
15952 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPFRAMEDONE_IRQ_VAL_PEND (0x1U)
15953 
15954 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPVSYNC_IRQ_MASK (0x00000002U)
15955 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPVSYNC_IRQ_SHIFT (0x00000001U)
15956 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPVSYNC_IRQ_MAX (0x00000001U)
15957 
15958 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPVSYNC_IRQ_VAL_NOPEND (0x0U)
15959 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPVSYNC_IRQ_VAL_PEND (0x1U)
15960 
15961 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPVSYNC_ODD_IRQ_MASK (0x00000004U)
15962 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPVSYNC_ODD_IRQ_SHIFT (0x00000002U)
15963 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPVSYNC_ODD_IRQ_MAX (0x00000001U)
15964 
15965 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPVSYNC_ODD_IRQ_VAL_NOPEND (0x0U)
15966 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPVSYNC_ODD_IRQ_VAL_PEND (0x1U)
15967 
15968 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPPROGRAMMEDLINENUMBER_IRQ_MASK (0x00000008U)
15969 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPPROGRAMMEDLINENUMBER_IRQ_SHIFT (0x00000003U)
15970 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPPROGRAMMEDLINENUMBER_IRQ_MAX (0x00000001U)
15971 
15972 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPPROGRAMMEDLINENUMBER_IRQ_VAL_NOPEND (0x0U)
15973 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPPROGRAMMEDLINENUMBER_IRQ_VAL_PEND (0x1U)
15974 
15975 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPSYNCLOST_IRQ_MASK (0x00000010U)
15976 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPSYNCLOST_IRQ_SHIFT (0x00000004U)
15977 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPSYNCLOST_IRQ_MAX (0x00000001U)
15978 
15979 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPSYNCLOST_IRQ_VAL_NOPEND (0x0U)
15980 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPSYNCLOST_IRQ_VAL_PEND (0x1U)
15981 
15982 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_ACBIASCOUNTSTATUS_IRQ_MASK (0x00000020U)
15983 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_ACBIASCOUNTSTATUS_IRQ_SHIFT (0x00000005U)
15984 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_ACBIASCOUNTSTATUS_IRQ_MAX (0x00000001U)
15985 
15986 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_ACBIASCOUNTSTATUS_IRQ_VAL_NOPEND (0x0U)
15987 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_ACBIASCOUNTSTATUS_IRQ_VAL_PEND (0x1U)
15988 
15989 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_SAFETYREGION_IRQ_MASK (0x000003C0U)
15990 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_SAFETYREGION_IRQ_SHIFT (0x00000006U)
15991 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_SAFETYREGION_IRQ_MAX (0x0000000FU)
15992 
15993 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
15994 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_SAFETYREGION_IRQ_VAL_PEND (0x1U)
15995 
15996 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_SECURITYVIOLATION_IRQ_MASK (0x00000400U)
15997 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_SECURITYVIOLATION_IRQ_SHIFT (0x0000000AU)
15998 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
15999 
16000 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
16001 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
16002 
16003 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPSYNC_IRQ_MASK (0x00000800U)
16004 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPSYNC_IRQ_SHIFT (0x0000000BU)
16005 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPSYNC_IRQ_MAX (0x00000001U)
16006 
16007 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPSYNC_IRQ_VAL_NOPEND (0x0U)
16008 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_VPSYNC_IRQ_VAL_PEND (0x1U)
16009 
16010 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_DUMMY_IRQ_MASK (0x00001000U)
16011 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_DUMMY_IRQ_SHIFT (0x0000000CU)
16012 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_DUMMY_IRQ_MAX (0x00000001U)
16013 
16014 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_DUMMY_IRQ_VAL_NOPEND (0x0U)
16015 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_DUMMY_IRQ_VAL_PEND (0x1U)
16016 
16017 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_SAFETYREGION1_IRQ_MASK (0x0001E000U)
16018 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_SAFETYREGION1_IRQ_SHIFT (0x0000000DU)
16019 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_SAFETYREGION1_IRQ_MAX (0x0000000FU)
16020 
16021 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_SAFETYREGION1_IRQ_VAL_NOPEND (0x0U)
16022 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_SAFETYREGION1_IRQ_VAL_PEND (0x1U)
16023 
16024 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_RESERVED_MASK (0xFFFE0000U)
16025 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_RESERVED_SHIFT (0x00000011U)
16026 #define CSL_DSS_COMMON_S1_VP_IRQSTATUS_3_RESERVED_MAX (0x00007FFFU)
16027 
16028 /* WB_IRQENABLE */
16029 
16030 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_WBBUFFEROVERFLOW_EN_MASK (0x00000001U)
16031 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_WBBUFFEROVERFLOW_EN_SHIFT (0x00000000U)
16032 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_WBBUFFEROVERFLOW_EN_MAX (0x00000001U)
16033 
16034 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_WBBUFFEROVERFLOW_EN_VAL_MASKED (0x0U)
16035 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_WBBUFFEROVERFLOW_EN_VAL_GENINT (0x1U)
16036 
16037 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_WBUNCOMPLETEERROR_EN_MASK (0x00000002U)
16038 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_WBUNCOMPLETEERROR_EN_SHIFT (0x00000001U)
16039 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_WBUNCOMPLETEERROR_EN_MAX (0x00000001U)
16040 
16041 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_WBUNCOMPLETEERROR_EN_VAL_MASKED (0x0U)
16042 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_WBUNCOMPLETEERROR_EN_VAL_GENINT (0x1U)
16043 
16044 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_WBFRAMEDONE_EN_MASK (0x00000004U)
16045 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_WBFRAMEDONE_EN_SHIFT (0x00000002U)
16046 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_WBFRAMEDONE_EN_MAX (0x00000001U)
16047 
16048 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_WBFRAMEDONE_EN_VAL_MASKED (0x0U)
16049 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_WBFRAMEDONE_EN_VAL_GENINT (0x1U)
16050 
16051 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_SECURITYVIOLATION_EN_MASK (0x00000008U)
16052 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_SECURITYVIOLATION_EN_SHIFT (0x00000003U)
16053 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_SECURITYVIOLATION_EN_MAX (0x00000001U)
16054 
16055 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
16056 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
16057 
16058 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_WBSYNC_EN_MASK (0x00000010U)
16059 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_WBSYNC_EN_SHIFT (0x00000004U)
16060 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_WBSYNC_EN_MAX (0x00000001U)
16061 
16062 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_WBSYNC_EN_VAL_MASKED (0x0U)
16063 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_WBSYNC_EN_VAL_GENINT (0x1U)
16064 
16065 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_RESERVED_MASK (0xFFFFFFE0U)
16066 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_RESERVED_SHIFT (0x00000005U)
16067 #define CSL_DSS_COMMON_S1_WB_IRQENABLE_RESERVED_MAX (0x07FFFFFFU)
16068 
16069 /* WB_IRQSTATUS */
16070 
16071 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_WBBUFFEROVERFLOW_IRQ_MASK (0x00000001U)
16072 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_WBBUFFEROVERFLOW_IRQ_SHIFT (0x00000000U)
16073 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_WBBUFFEROVERFLOW_IRQ_MAX (0x00000001U)
16074 
16075 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_WBBUFFEROVERFLOW_IRQ_VAL_NOPEND (0x0U)
16076 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_WBBUFFEROVERFLOW_IRQ_VAL_PEND (0x1U)
16077 
16078 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_WBUNCOMPLETEERROR_IRQ_MASK (0x00000002U)
16079 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_WBUNCOMPLETEERROR_IRQ_SHIFT (0x00000001U)
16080 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_WBUNCOMPLETEERROR_IRQ_MAX (0x00000001U)
16081 
16082 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_WBUNCOMPLETEERROR_IRQ_VAL_NOPEND (0x0U)
16083 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_WBUNCOMPLETEERROR_IRQ_VAL_PEND (0x1U)
16084 
16085 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_WBFRAMEDONE_IRQ_MASK (0x00000004U)
16086 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_WBFRAMEDONE_IRQ_SHIFT (0x00000002U)
16087 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_WBFRAMEDONE_IRQ_MAX (0x00000001U)
16088 
16089 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_WBFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
16090 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_WBFRAMEDONE_IRQ_VAL_PEND (0x1U)
16091 
16092 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_SECURITYVIOLATION_IRQ_MASK (0x00000008U)
16093 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_SECURITYVIOLATION_IRQ_SHIFT (0x00000003U)
16094 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
16095 
16096 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
16097 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
16098 
16099 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_WBSYNC_IRQ_MASK (0x00000010U)
16100 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_WBSYNC_IRQ_SHIFT (0x00000004U)
16101 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_WBSYNC_IRQ_MAX (0x00000001U)
16102 
16103 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_WBSYNC_IRQ_VAL_NOPEND (0x0U)
16104 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_WBSYNC_IRQ_VAL_PEND (0x1U)
16105 
16106 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_RESERVED_MASK (0xFFFFFFE0U)
16107 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_RESERVED_SHIFT (0x00000005U)
16108 #define CSL_DSS_COMMON_S1_WB_IRQSTATUS_RESERVED_MAX (0x07FFFFFFU)
16109 
16110 /* DISPC_IRQ_EOI_FUNC */
16111 
16112 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_FUNC_EOI_MASK (0x00000001U)
16113 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_FUNC_EOI_SHIFT (0x00000000U)
16114 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_FUNC_EOI_MAX (0x00000001U)
16115 
16116 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_FUNC_EOI_VAL_NOACTION (0x0U)
16117 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_FUNC_EOI_VAL_EOI (0x1U)
16118 
16119 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_FUNC_RESERVED_MASK (0xFFFFFFFEU)
16120 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_FUNC_RESERVED_SHIFT (0x00000001U)
16121 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_FUNC_RESERVED_MAX (0x7FFFFFFFU)
16122 
16123 /* DISPC_IRQ_EOI_SAFETY */
16124 
16125 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_SAFETY_EOI_MASK (0x00000001U)
16126 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_SAFETY_EOI_SHIFT (0x00000000U)
16127 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_SAFETY_EOI_MAX (0x00000001U)
16128 
16129 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_SAFETY_EOI_VAL_NOACTION (0x0U)
16130 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_SAFETY_EOI_VAL_EOI (0x1U)
16131 
16132 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_SAFETY_RESERVED_MASK (0xFFFFFFFEU)
16133 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_SAFETY_RESERVED_SHIFT (0x00000001U)
16134 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_SAFETY_RESERVED_MAX (0x7FFFFFFFU)
16135 
16136 /* DISPC_IRQ_EOI_SECURITY */
16137 
16138 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_SECURITY_EOI_MASK (0x00000001U)
16139 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_SECURITY_EOI_SHIFT (0x00000000U)
16140 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_SECURITY_EOI_MAX (0x00000001U)
16141 
16142 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_SECURITY_EOI_VAL_NOACTION (0x0U)
16143 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_SECURITY_EOI_VAL_EOI (0x1U)
16144 
16145 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_SECURITY_RESERVED_MASK (0xFFFFFFFEU)
16146 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_SECURITY_RESERVED_SHIFT (0x00000001U)
16147 #define CSL_DSS_COMMON_S1_DISPC_IRQ_EOI_SECURITY_RESERVED_MAX (0x7FFFFFFFU)
16148 
16149 /**************************************************************************
16150 * Hardware Region : COMMON_S2 Registers
16151 **************************************************************************/
16152 
16153 
16154 /**************************************************************************
16155 * Register Overlay Structure
16156 **************************************************************************/
16157 
16158 typedef struct {
16159  volatile uint8_t Resv_40[40];
16160  volatile uint32_t DISPC_IRQSTATUS_RAW; /* DISPC_IRQSTATUS_RAW */
16161  volatile uint32_t DISPC_IRQSTATUS; /* DISPC_IRQSTATUS */
16162  volatile uint32_t DISPC_IRQENABLE_SET; /* DISPC_IRQENABLE_SET */
16163  volatile uint32_t DISPC_IRQENABLE_CLR; /* DISPC_IRQENABLE_CLR */
16164  volatile uint32_t VID_IRQENABLE_0; /* VID_IRQENABLE_0 */
16165  volatile uint32_t VID_IRQENABLE_1; /* VID_IRQENABLE_1 */
16166  volatile uint32_t VID_IRQENABLE_2; /* VID_IRQENABLE_2 */
16167  volatile uint32_t VID_IRQENABLE_3; /* VID_IRQENABLE_3 */
16168  volatile uint32_t VID_IRQSTATUS_0; /* VID_IRQSTATUS_0 */
16169  volatile uint32_t VID_IRQSTATUS_1; /* VID_IRQSTATUS_1 */
16170  volatile uint32_t VID_IRQSTATUS_2; /* VID_IRQSTATUS_2 */
16171  volatile uint32_t VID_IRQSTATUS_3; /* VID_IRQSTATUS_3 */
16172  volatile uint32_t VP_IRQENABLE_0; /* VP_IRQENABLE_0 */
16173  volatile uint32_t VP_IRQENABLE_1; /* VP_IRQENABLE_1 */
16174  volatile uint32_t VP_IRQENABLE_2; /* VP_IRQENABLE_2 */
16175  volatile uint32_t VP_IRQENABLE_3; /* VP_IRQENABLE_3 */
16176  volatile uint32_t VP_IRQSTATUS_0; /* VP_IRQSTATUS_0 */
16177  volatile uint32_t VP_IRQSTATUS_1; /* VP_IRQSTATUS_1 */
16178  volatile uint32_t VP_IRQSTATUS_2; /* VP_IRQSTATUS_2 */
16179  volatile uint32_t VP_IRQSTATUS_3; /* VP_IRQSTATUS_3 */
16180  volatile uint32_t WB_IRQENABLE; /* WB_IRQENABLE */
16181  volatile uint32_t WB_IRQSTATUS; /* WB_IRQSTATUS */
16182  volatile uint32_t DISPC_IRQ_EOI_FUNC; /* DISPC_IRQ_EOI_FUNC */
16183  volatile uint32_t DISPC_IRQ_EOI_SAFETY; /* DISPC_IRQ_EOI_SAFETY */
16184  volatile uint32_t DISPC_IRQ_EOI_SECURITY; /* DISPC_IRQ_EOI_SECURITY */
16186 
16187 
16188 /**************************************************************************
16189 * Register Macros
16190 **************************************************************************/
16191 
16192 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW (0x00000028U)
16193 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS (0x0000002CU)
16194 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET (0x00000030U)
16195 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR (0x00000034U)
16196 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0 (0x00000038U)
16197 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1 (0x0000003CU)
16198 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2 (0x00000040U)
16199 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3 (0x00000044U)
16200 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0 (0x00000048U)
16201 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1 (0x0000004CU)
16202 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2 (0x00000050U)
16203 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3 (0x00000054U)
16204 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0 (0x00000058U)
16205 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1 (0x0000005CU)
16206 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2 (0x00000060U)
16207 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3 (0x00000064U)
16208 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0 (0x00000068U)
16209 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1 (0x0000006CU)
16210 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2 (0x00000070U)
16211 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3 (0x00000074U)
16212 #define CSL_DSS_COMMON_S2_WB_IRQENABLE (0x00000078U)
16213 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS (0x0000007CU)
16214 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_FUNC (0x00000080U)
16215 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_SAFETY (0x00000084U)
16216 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_SECURITY (0x00000088U)
16217 
16218 /**************************************************************************
16219 * Field Definition Macros
16220 **************************************************************************/
16221 
16222 
16223 /* DISPC_IRQSTATUS_RAW */
16224 
16225 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_VP_IRQ_MASK (0x0000000FU)
16226 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_VP_IRQ_SHIFT (0x00000000U)
16227 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_VP_IRQ_MAX (0x0000000FU)
16228 
16229 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_VP_IRQ_VAL_NOACTION (0x0U)
16230 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_VP_IRQ_VAL_SET_EVENT (0x1U)
16231 
16232 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_VID_IRQ_MASK (0x000000F0U)
16233 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_VID_IRQ_SHIFT (0x00000004U)
16234 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_VID_IRQ_MAX (0x0000000FU)
16235 
16236 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_VID_IRQ_VAL_NOACTION (0x0U)
16237 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_VID_IRQ_VAL_SET_EVENT (0x1U)
16238 
16239 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_RESERVED_VID_MASK (0x00001F00U)
16240 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_RESERVED_VID_SHIFT (0x00000008U)
16241 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_RESERVED_VID_MAX (0x0000001FU)
16242 
16243 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_RESERVED_CUR_MASK (0x00002000U)
16244 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_RESERVED_CUR_SHIFT (0x0000000DU)
16245 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_RESERVED_CUR_MAX (0x00000001U)
16246 
16247 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_WB_IRQ_MASK (0x00004000U)
16248 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_WB_IRQ_SHIFT (0x0000000EU)
16249 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_WB_IRQ_MAX (0x00000001U)
16250 
16251 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_WB_IRQ_VAL_NOACTION (0x0U)
16252 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_WB_IRQ_VAL_SET_EVENT (0x1U)
16253 
16254 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_DUMMY1_IRQ_MASK (0x00008000U)
16255 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_DUMMY1_IRQ_SHIFT (0x0000000FU)
16256 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_DUMMY1_IRQ_MAX (0x00000001U)
16257 
16258 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_DUMMY1_IRQ_VAL_NOACTION (0x0U)
16259 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_DUMMY1_IRQ_VAL_SET_EVENT (0x1U)
16260 
16261 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_DUMMY_IRQ_MASK (0x00010000U)
16262 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_DUMMY_IRQ_SHIFT (0x00000010U)
16263 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_DUMMY_IRQ_MAX (0x00000001U)
16264 
16265 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_DUMMY_IRQ_VAL_NOACTION (0x0U)
16266 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_DUMMY_IRQ_VAL_SET_EVENT (0x1U)
16267 
16268 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_RESERVED_MASK (0xFFFE0000U)
16269 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_RESERVED_SHIFT (0x00000011U)
16270 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RAW_RESERVED_MAX (0x00007FFFU)
16271 
16272 /* DISPC_IRQSTATUS */
16273 
16274 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_VP_IRQ_MASK (0x0000000FU)
16275 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_VP_IRQ_SHIFT (0x00000000U)
16276 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_VP_IRQ_MAX (0x0000000FU)
16277 
16278 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_VP_IRQ_VAL_NOACTION (0x0U)
16279 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_VP_IRQ_VAL_CLEAR (0x1U)
16280 
16281 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_VID_IRQ_MASK (0x000000F0U)
16282 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_VID_IRQ_SHIFT (0x00000004U)
16283 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_VID_IRQ_MAX (0x0000000FU)
16284 
16285 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_VID_IRQ_VAL_NOACTION (0x0U)
16286 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_VID_IRQ_VAL_CLEAR (0x1U)
16287 
16288 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RESERVED_VID_MASK (0x00001F00U)
16289 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RESERVED_VID_SHIFT (0x00000008U)
16290 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RESERVED_VID_MAX (0x0000001FU)
16291 
16292 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RESERVED_CUR_MASK (0x00002000U)
16293 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RESERVED_CUR_SHIFT (0x0000000DU)
16294 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RESERVED_CUR_MAX (0x00000001U)
16295 
16296 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_WB_IRQ_MASK (0x00004000U)
16297 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_WB_IRQ_SHIFT (0x0000000EU)
16298 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_WB_IRQ_MAX (0x00000001U)
16299 
16300 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_WB_IRQ_VAL_NOACTION (0x0U)
16301 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_WB_IRQ_VAL_CLEAR (0x1U)
16302 
16303 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_DUMMY1_IRQ_MASK (0x00008000U)
16304 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_DUMMY1_IRQ_SHIFT (0x0000000FU)
16305 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_DUMMY1_IRQ_MAX (0x00000001U)
16306 
16307 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_DUMMY1_IRQ_VAL_NOACTION (0x0U)
16308 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_DUMMY1_IRQ_VAL_CLEAR (0x1U)
16309 
16310 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_DUMMY_IRQ_MASK (0x00010000U)
16311 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_DUMMY_IRQ_SHIFT (0x00000010U)
16312 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_DUMMY_IRQ_MAX (0x00000001U)
16313 
16314 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_DUMMY_IRQ_VAL_NOACTION (0x0U)
16315 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_DUMMY_IRQ_VAL_CLEAR (0x1U)
16316 
16317 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RESERVED_MASK (0xFFFE0000U)
16318 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RESERVED_SHIFT (0x00000011U)
16319 #define CSL_DSS_COMMON_S2_DISPC_IRQSTATUS_RESERVED_MAX (0x00007FFFU)
16320 
16321 /* DISPC_IRQENABLE_SET */
16322 
16323 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_SET_VP_IRQ_MASK (0x0000000FU)
16324 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_SET_VP_IRQ_SHIFT (0x00000000U)
16325 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_SET_VP_IRQ_MAX (0x0000000FU)
16326 
16327 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_SET_VP_IRQ_VAL_NOACTION (0x0U)
16328 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_SET_VP_IRQ_VAL_ENABLE (0x1U)
16329 
16330 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_SET_VID_IRQ_MASK (0x000000F0U)
16331 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_SET_VID_IRQ_SHIFT (0x00000004U)
16332 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_SET_VID_IRQ_MAX (0x0000000FU)
16333 
16334 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_SET_VID_IRQ_VAL_NOACTION (0x0U)
16335 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_SET_VID_IRQ_VAL_ENABLE (0x1U)
16336 
16337 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_RESERVED_VID_MASK (0x00001F00U)
16338 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_RESERVED_VID_SHIFT (0x00000008U)
16339 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_RESERVED_VID_MAX (0x0000001FU)
16340 
16341 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_RESERVED_CUR_MASK (0x00002000U)
16342 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_RESERVED_CUR_SHIFT (0x0000000DU)
16343 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_RESERVED_CUR_MAX (0x00000001U)
16344 
16345 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_SET_WB_IRQ_MASK (0x00004000U)
16346 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_SET_WB_IRQ_SHIFT (0x0000000EU)
16347 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_SET_WB_IRQ_MAX (0x00000001U)
16348 
16349 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_SET_WB_IRQ_VAL_NOACTION (0x0U)
16350 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_SET_WB_IRQ_VAL_ENABLE (0x1U)
16351 
16352 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_SET_DUMMY1_IRQ_MASK (0x00008000U)
16353 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_SET_DUMMY1_IRQ_SHIFT (0x0000000FU)
16354 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_SET_DUMMY1_IRQ_MAX (0x00000001U)
16355 
16356 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_SET_DUMMY1_IRQ_VAL_NOACTION (0x0U)
16357 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_SET_DUMMY1_IRQ_VAL_ENABLE (0x1U)
16358 
16359 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_SET_DUMMY_IRQ_MASK (0x00010000U)
16360 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_SET_DUMMY_IRQ_SHIFT (0x00000010U)
16361 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_SET_DUMMY_IRQ_MAX (0x00000001U)
16362 
16363 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_SET_DUMMY_IRQ_VAL_NOACTION (0x0U)
16364 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_SET_DUMMY_IRQ_VAL_ENABLE (0x1U)
16365 
16366 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_RESERVED_MASK (0xFFFE0000U)
16367 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_RESERVED_SHIFT (0x00000011U)
16368 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_SET_RESERVED_MAX (0x00007FFFU)
16369 
16370 /* DISPC_IRQENABLE_CLR */
16371 
16372 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_MASK (0x0000000FU)
16373 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_SHIFT (0x00000000U)
16374 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_MAX (0x0000000FU)
16375 
16376 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_VAL_NOACTION (0x0U)
16377 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_VAL_CLEAR (0x1U)
16378 
16379 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_MASK (0x000000F0U)
16380 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_SHIFT (0x00000004U)
16381 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_MAX (0x0000000FU)
16382 
16383 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_VAL_NOACTION (0x0U)
16384 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_VAL_CLEAR (0x1U)
16385 
16386 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_RESERVED_VID_MASK (0x00001F00U)
16387 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_RESERVED_VID_SHIFT (0x00000008U)
16388 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_RESERVED_VID_MAX (0x0000001FU)
16389 
16390 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_RESERVED_CUR_MASK (0x00002000U)
16391 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_RESERVED_CUR_SHIFT (0x0000000DU)
16392 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_RESERVED_CUR_MAX (0x00000001U)
16393 
16394 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_CLR_WB_IRQ_MASK (0x00004000U)
16395 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_CLR_WB_IRQ_SHIFT (0x0000000EU)
16396 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_CLR_WB_IRQ_MAX (0x00000001U)
16397 
16398 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_CLR_WB_IRQ_VAL_NOACTION (0x0U)
16399 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_CLR_WB_IRQ_VAL_CLEAR (0x1U)
16400 
16401 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_CLR_DUMMY1_IRQ_MASK (0x00008000U)
16402 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_CLR_DUMMY1_IRQ_SHIFT (0x0000000FU)
16403 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_CLR_DUMMY1_IRQ_MAX (0x00000001U)
16404 
16405 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_CLR_DUMMY1_IRQ_VAL_NOACTION (0x0U)
16406 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_CLR_DUMMY1_IRQ_VAL_CLEAR (0x1U)
16407 
16408 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_CLR_DUMMY_IRQ_MASK (0x00010000U)
16409 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_CLR_DUMMY_IRQ_SHIFT (0x00000010U)
16410 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_CLR_DUMMY_IRQ_MAX (0x00000001U)
16411 
16412 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_CLR_DUMMY_IRQ_VAL_NOACTION (0x0U)
16413 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_CLR_DUMMY_IRQ_VAL_CLEAR (0x1U)
16414 
16415 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_RESERVED_MASK (0xFFFE0000U)
16416 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_RESERVED_SHIFT (0x00000011U)
16417 #define CSL_DSS_COMMON_S2_DISPC_IRQENABLE_CLR_RESERVED_MAX (0x00007FFFU)
16418 
16419 /* VID_IRQENABLE_0 */
16420 
16421 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_MASK (0x00000001U)
16422 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_SHIFT (0x00000000U)
16423 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_MAX (0x00000001U)
16424 
16425 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_VAL_MASKED (0x0U)
16426 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_VAL_GENINT (0x1U)
16427 
16428 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_VIDENDWINDOW_EN_MASK (0x00000002U)
16429 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_VIDENDWINDOW_EN_SHIFT (0x00000001U)
16430 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_VIDENDWINDOW_EN_MAX (0x00000001U)
16431 
16432 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_VIDENDWINDOW_EN_VAL_MASKED (0x0U)
16433 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_VIDENDWINDOW_EN_VAL_GENINT (0x1U)
16434 
16435 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_SAFETYREGION_EN_MASK (0x00000004U)
16436 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_SAFETYREGION_EN_SHIFT (0x00000002U)
16437 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_SAFETYREGION_EN_MAX (0x00000001U)
16438 
16439 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_SAFETYREGION_EN_VAL_MASKED (0x0U)
16440 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_SAFETYREGION_EN_VAL_GENINT (0x1U)
16441 
16442 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_FBDC_CORRUPTTILE_EN_MASK (0x00000008U)
16443 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_FBDC_CORRUPTTILE_EN_SHIFT (0x00000003U)
16444 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_FBDC_CORRUPTTILE_EN_MAX (0x00000001U)
16445 
16446 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_FBDC_CORRUPTTILE_EN_VAL_MASKED (0x0U)
16447 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_FBDC_CORRUPTTILE_EN_VAL_GENINT (0x1U)
16448 
16449 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_FBDC_ILLEGALTILEREQ_EN_MASK (0x00000010U)
16450 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_FBDC_ILLEGALTILEREQ_EN_SHIFT (0x00000004U)
16451 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_FBDC_ILLEGALTILEREQ_EN_MAX (0x00000001U)
16452 
16453 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_FBDC_ILLEGALTILEREQ_EN_VAL_MASKED (0x0U)
16454 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_FBDC_ILLEGALTILEREQ_EN_VAL_GENINT (0x1U)
16455 
16456 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_RESERVED_MASK (0xFFFFFFE0U)
16457 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_RESERVED_SHIFT (0x00000005U)
16458 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_0_RESERVED_MAX (0x07FFFFFFU)
16459 
16460 /* VID_IRQENABLE_1 */
16461 
16462 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_MASK (0x00000001U)
16463 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_SHIFT (0x00000000U)
16464 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_MAX (0x00000001U)
16465 
16466 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_VAL_MASKED (0x0U)
16467 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_VAL_GENINT (0x1U)
16468 
16469 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_VIDENDWINDOW_EN_MASK (0x00000002U)
16470 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_VIDENDWINDOW_EN_SHIFT (0x00000001U)
16471 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_VIDENDWINDOW_EN_MAX (0x00000001U)
16472 
16473 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_VIDENDWINDOW_EN_VAL_MASKED (0x0U)
16474 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_VIDENDWINDOW_EN_VAL_GENINT (0x1U)
16475 
16476 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_SAFETYREGION_EN_MASK (0x00000004U)
16477 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_SAFETYREGION_EN_SHIFT (0x00000002U)
16478 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_SAFETYREGION_EN_MAX (0x00000001U)
16479 
16480 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_SAFETYREGION_EN_VAL_MASKED (0x0U)
16481 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_SAFETYREGION_EN_VAL_GENINT (0x1U)
16482 
16483 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_FBDC_CORRUPTTILE_EN_MASK (0x00000008U)
16484 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_FBDC_CORRUPTTILE_EN_SHIFT (0x00000003U)
16485 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_FBDC_CORRUPTTILE_EN_MAX (0x00000001U)
16486 
16487 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_FBDC_CORRUPTTILE_EN_VAL_MASKED (0x0U)
16488 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_FBDC_CORRUPTTILE_EN_VAL_GENINT (0x1U)
16489 
16490 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_FBDC_ILLEGALTILEREQ_EN_MASK (0x00000010U)
16491 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_FBDC_ILLEGALTILEREQ_EN_SHIFT (0x00000004U)
16492 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_FBDC_ILLEGALTILEREQ_EN_MAX (0x00000001U)
16493 
16494 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_FBDC_ILLEGALTILEREQ_EN_VAL_MASKED (0x0U)
16495 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_FBDC_ILLEGALTILEREQ_EN_VAL_GENINT (0x1U)
16496 
16497 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_RESERVED_MASK (0xFFFFFFE0U)
16498 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_RESERVED_SHIFT (0x00000005U)
16499 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_1_RESERVED_MAX (0x07FFFFFFU)
16500 
16501 /* VID_IRQENABLE_2 */
16502 
16503 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_VIDBUFFERUNDERFLOW_EN_MASK (0x00000001U)
16504 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_VIDBUFFERUNDERFLOW_EN_SHIFT (0x00000000U)
16505 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_VIDBUFFERUNDERFLOW_EN_MAX (0x00000001U)
16506 
16507 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_VIDBUFFERUNDERFLOW_EN_VAL_MASKED (0x0U)
16508 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_VIDBUFFERUNDERFLOW_EN_VAL_GENINT (0x1U)
16509 
16510 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_VIDENDWINDOW_EN_MASK (0x00000002U)
16511 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_VIDENDWINDOW_EN_SHIFT (0x00000001U)
16512 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_VIDENDWINDOW_EN_MAX (0x00000001U)
16513 
16514 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_VIDENDWINDOW_EN_VAL_MASKED (0x0U)
16515 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_VIDENDWINDOW_EN_VAL_GENINT (0x1U)
16516 
16517 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_SAFETYREGION_EN_MASK (0x00000004U)
16518 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_SAFETYREGION_EN_SHIFT (0x00000002U)
16519 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_SAFETYREGION_EN_MAX (0x00000001U)
16520 
16521 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_SAFETYREGION_EN_VAL_MASKED (0x0U)
16522 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_SAFETYREGION_EN_VAL_GENINT (0x1U)
16523 
16524 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_FBDC_CORRUPTTILE_EN_MASK (0x00000008U)
16525 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_FBDC_CORRUPTTILE_EN_SHIFT (0x00000003U)
16526 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_FBDC_CORRUPTTILE_EN_MAX (0x00000001U)
16527 
16528 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_FBDC_CORRUPTTILE_EN_VAL_MASKED (0x0U)
16529 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_FBDC_CORRUPTTILE_EN_VAL_GENINT (0x1U)
16530 
16531 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_FBDC_ILLEGALTILEREQ_EN_MASK (0x00000010U)
16532 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_FBDC_ILLEGALTILEREQ_EN_SHIFT (0x00000004U)
16533 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_FBDC_ILLEGALTILEREQ_EN_MAX (0x00000001U)
16534 
16535 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_FBDC_ILLEGALTILEREQ_EN_VAL_MASKED (0x0U)
16536 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_FBDC_ILLEGALTILEREQ_EN_VAL_GENINT (0x1U)
16537 
16538 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_RESERVED_MASK (0xFFFFFFE0U)
16539 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_RESERVED_SHIFT (0x00000005U)
16540 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_2_RESERVED_MAX (0x07FFFFFFU)
16541 
16542 /* VID_IRQENABLE_3 */
16543 
16544 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_VIDBUFFERUNDERFLOW_EN_MASK (0x00000001U)
16545 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_VIDBUFFERUNDERFLOW_EN_SHIFT (0x00000000U)
16546 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_VIDBUFFERUNDERFLOW_EN_MAX (0x00000001U)
16547 
16548 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_VIDBUFFERUNDERFLOW_EN_VAL_MASKED (0x0U)
16549 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_VIDBUFFERUNDERFLOW_EN_VAL_GENINT (0x1U)
16550 
16551 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_VIDENDWINDOW_EN_MASK (0x00000002U)
16552 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_VIDENDWINDOW_EN_SHIFT (0x00000001U)
16553 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_VIDENDWINDOW_EN_MAX (0x00000001U)
16554 
16555 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_VIDENDWINDOW_EN_VAL_MASKED (0x0U)
16556 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_VIDENDWINDOW_EN_VAL_GENINT (0x1U)
16557 
16558 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_SAFETYREGION_EN_MASK (0x00000004U)
16559 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_SAFETYREGION_EN_SHIFT (0x00000002U)
16560 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_SAFETYREGION_EN_MAX (0x00000001U)
16561 
16562 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_SAFETYREGION_EN_VAL_MASKED (0x0U)
16563 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_SAFETYREGION_EN_VAL_GENINT (0x1U)
16564 
16565 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_FBDC_CORRUPTTILE_EN_MASK (0x00000008U)
16566 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_FBDC_CORRUPTTILE_EN_SHIFT (0x00000003U)
16567 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_FBDC_CORRUPTTILE_EN_MAX (0x00000001U)
16568 
16569 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_FBDC_CORRUPTTILE_EN_VAL_MASKED (0x0U)
16570 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_FBDC_CORRUPTTILE_EN_VAL_GENINT (0x1U)
16571 
16572 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_FBDC_ILLEGALTILEREQ_EN_MASK (0x00000010U)
16573 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_FBDC_ILLEGALTILEREQ_EN_SHIFT (0x00000004U)
16574 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_FBDC_ILLEGALTILEREQ_EN_MAX (0x00000001U)
16575 
16576 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_FBDC_ILLEGALTILEREQ_EN_VAL_MASKED (0x0U)
16577 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_FBDC_ILLEGALTILEREQ_EN_VAL_GENINT (0x1U)
16578 
16579 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_RESERVED_MASK (0xFFFFFFE0U)
16580 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_RESERVED_SHIFT (0x00000005U)
16581 #define CSL_DSS_COMMON_S2_VID_IRQENABLE_3_RESERVED_MAX (0x07FFFFFFU)
16582 
16583 /* VID_IRQSTATUS_0 */
16584 
16585 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_MASK (0x00000001U)
16586 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_SHIFT (0x00000000U)
16587 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_MAX (0x00000001U)
16588 
16589 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_VAL_NOPEND (0x0U)
16590 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_VAL_PEND (0x1U)
16591 
16592 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_MASK (0x00000002U)
16593 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_SHIFT (0x00000001U)
16594 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_MAX (0x00000001U)
16595 
16596 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_VAL_NOPEND (0x0U)
16597 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_VAL_PEND (0x1U)
16598 
16599 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_SAFETYREGION_IRQ_MASK (0x00000004U)
16600 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_SAFETYREGION_IRQ_SHIFT (0x00000002U)
16601 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_SAFETYREGION_IRQ_MAX (0x00000001U)
16602 
16603 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
16604 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_PEND (0x1U)
16605 
16606 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_FBDC_CORRUPTTILE_IRQ_MASK (0x00000008U)
16607 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_FBDC_CORRUPTTILE_IRQ_SHIFT (0x00000003U)
16608 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_FBDC_CORRUPTTILE_IRQ_MAX (0x00000001U)
16609 
16610 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_FBDC_CORRUPTTILE_IRQ_VAL_NOPEND (0x0U)
16611 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_FBDC_CORRUPTTILE_IRQ_VAL_PEND (0x1U)
16612 
16613 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_FBDC_ILLEGALTILEREQ_IRQ_MASK (0x00000010U)
16614 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_FBDC_ILLEGALTILEREQ_IRQ_SHIFT (0x00000004U)
16615 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_FBDC_ILLEGALTILEREQ_IRQ_MAX (0x00000001U)
16616 
16617 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_FBDC_ILLEGALTILEREQ_IRQ_VAL_NOPEND (0x0U)
16618 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_FBDC_ILLEGALTILEREQ_IRQ_VAL_PEND (0x1U)
16619 
16620 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_RESERVED_MASK (0xFFFFFFE0U)
16621 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_RESERVED_SHIFT (0x00000005U)
16622 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_0_RESERVED_MAX (0x07FFFFFFU)
16623 
16624 /* VID_IRQSTATUS_1 */
16625 
16626 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_MASK (0x00000001U)
16627 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_SHIFT (0x00000000U)
16628 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_MAX (0x00000001U)
16629 
16630 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_VAL_NOPEND (0x0U)
16631 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_VAL_PEND (0x1U)
16632 
16633 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_MASK (0x00000002U)
16634 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_SHIFT (0x00000001U)
16635 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_MAX (0x00000001U)
16636 
16637 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_VAL_NOPEND (0x0U)
16638 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_VAL_PEND (0x1U)
16639 
16640 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_SAFETYREGION_IRQ_MASK (0x00000004U)
16641 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_SAFETYREGION_IRQ_SHIFT (0x00000002U)
16642 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_SAFETYREGION_IRQ_MAX (0x00000001U)
16643 
16644 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
16645 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_PEND (0x1U)
16646 
16647 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_FBDC_CORRUPTTILE_IRQ_MASK (0x00000008U)
16648 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_FBDC_CORRUPTTILE_IRQ_SHIFT (0x00000003U)
16649 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_FBDC_CORRUPTTILE_IRQ_MAX (0x00000001U)
16650 
16651 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_FBDC_CORRUPTTILE_IRQ_VAL_NOPEND (0x0U)
16652 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_FBDC_CORRUPTTILE_IRQ_VAL_PEND (0x1U)
16653 
16654 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_FBDC_ILLEGALTILEREQ_IRQ_MASK (0x00000010U)
16655 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_FBDC_ILLEGALTILEREQ_IRQ_SHIFT (0x00000004U)
16656 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_FBDC_ILLEGALTILEREQ_IRQ_MAX (0x00000001U)
16657 
16658 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_FBDC_ILLEGALTILEREQ_IRQ_VAL_NOPEND (0x0U)
16659 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_FBDC_ILLEGALTILEREQ_IRQ_VAL_PEND (0x1U)
16660 
16661 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_RESERVED_MASK (0xFFFFFFE0U)
16662 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_RESERVED_SHIFT (0x00000005U)
16663 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_1_RESERVED_MAX (0x07FFFFFFU)
16664 
16665 /* VID_IRQSTATUS_2 */
16666 
16667 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_VIDBUFFERUNDERFLOW_IRQ_MASK (0x00000001U)
16668 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_VIDBUFFERUNDERFLOW_IRQ_SHIFT (0x00000000U)
16669 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_VIDBUFFERUNDERFLOW_IRQ_MAX (0x00000001U)
16670 
16671 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_VIDBUFFERUNDERFLOW_IRQ_VAL_NOPEND (0x0U)
16672 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_VIDBUFFERUNDERFLOW_IRQ_VAL_PEND (0x1U)
16673 
16674 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_VIDENDWINDOW_IRQ_MASK (0x00000002U)
16675 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_VIDENDWINDOW_IRQ_SHIFT (0x00000001U)
16676 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_VIDENDWINDOW_IRQ_MAX (0x00000001U)
16677 
16678 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_VIDENDWINDOW_IRQ_VAL_NOPEND (0x0U)
16679 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_VIDENDWINDOW_IRQ_VAL_PEND (0x1U)
16680 
16681 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_SAFETYREGION_IRQ_MASK (0x00000004U)
16682 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_SAFETYREGION_IRQ_SHIFT (0x00000002U)
16683 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_SAFETYREGION_IRQ_MAX (0x00000001U)
16684 
16685 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
16686 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_SAFETYREGION_IRQ_VAL_PEND (0x1U)
16687 
16688 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_FBDC_CORRUPTTILE_IRQ_MASK (0x00000008U)
16689 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_FBDC_CORRUPTTILE_IRQ_SHIFT (0x00000003U)
16690 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_FBDC_CORRUPTTILE_IRQ_MAX (0x00000001U)
16691 
16692 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_FBDC_CORRUPTTILE_IRQ_VAL_NOPEND (0x0U)
16693 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_FBDC_CORRUPTTILE_IRQ_VAL_PEND (0x1U)
16694 
16695 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_FBDC_ILLEGALTILEREQ_IRQ_MASK (0x00000010U)
16696 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_FBDC_ILLEGALTILEREQ_IRQ_SHIFT (0x00000004U)
16697 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_FBDC_ILLEGALTILEREQ_IRQ_MAX (0x00000001U)
16698 
16699 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_FBDC_ILLEGALTILEREQ_IRQ_VAL_NOPEND (0x0U)
16700 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_FBDC_ILLEGALTILEREQ_IRQ_VAL_PEND (0x1U)
16701 
16702 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_RESERVED_MASK (0xFFFFFFE0U)
16703 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_RESERVED_SHIFT (0x00000005U)
16704 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_2_RESERVED_MAX (0x07FFFFFFU)
16705 
16706 /* VID_IRQSTATUS_3 */
16707 
16708 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_VIDBUFFERUNDERFLOW_IRQ_MASK (0x00000001U)
16709 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_VIDBUFFERUNDERFLOW_IRQ_SHIFT (0x00000000U)
16710 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_VIDBUFFERUNDERFLOW_IRQ_MAX (0x00000001U)
16711 
16712 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_VIDBUFFERUNDERFLOW_IRQ_VAL_NOPEND (0x0U)
16713 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_VIDBUFFERUNDERFLOW_IRQ_VAL_PEND (0x1U)
16714 
16715 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_VIDENDWINDOW_IRQ_MASK (0x00000002U)
16716 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_VIDENDWINDOW_IRQ_SHIFT (0x00000001U)
16717 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_VIDENDWINDOW_IRQ_MAX (0x00000001U)
16718 
16719 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_VIDENDWINDOW_IRQ_VAL_NOPEND (0x0U)
16720 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_VIDENDWINDOW_IRQ_VAL_PEND (0x1U)
16721 
16722 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_SAFETYREGION_IRQ_MASK (0x00000004U)
16723 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_SAFETYREGION_IRQ_SHIFT (0x00000002U)
16724 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_SAFETYREGION_IRQ_MAX (0x00000001U)
16725 
16726 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
16727 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_SAFETYREGION_IRQ_VAL_PEND (0x1U)
16728 
16729 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_FBDC_CORRUPTTILE_IRQ_MASK (0x00000008U)
16730 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_FBDC_CORRUPTTILE_IRQ_SHIFT (0x00000003U)
16731 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_FBDC_CORRUPTTILE_IRQ_MAX (0x00000001U)
16732 
16733 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_FBDC_CORRUPTTILE_IRQ_VAL_NOPEND (0x0U)
16734 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_FBDC_CORRUPTTILE_IRQ_VAL_PEND (0x1U)
16735 
16736 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_FBDC_ILLEGALTILEREQ_IRQ_MASK (0x00000010U)
16737 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_FBDC_ILLEGALTILEREQ_IRQ_SHIFT (0x00000004U)
16738 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_FBDC_ILLEGALTILEREQ_IRQ_MAX (0x00000001U)
16739 
16740 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_FBDC_ILLEGALTILEREQ_IRQ_VAL_NOPEND (0x0U)
16741 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_FBDC_ILLEGALTILEREQ_IRQ_VAL_PEND (0x1U)
16742 
16743 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_RESERVED_MASK (0xFFFFFFE0U)
16744 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_RESERVED_SHIFT (0x00000005U)
16745 #define CSL_DSS_COMMON_S2_VID_IRQSTATUS_3_RESERVED_MAX (0x07FFFFFFU)
16746 
16747 /* VP_IRQENABLE_0 */
16748 
16749 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPFRAMEDONE_EN_MASK (0x00000001U)
16750 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPFRAMEDONE_EN_SHIFT (0x00000000U)
16751 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPFRAMEDONE_EN_MAX (0x00000001U)
16752 
16753 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPFRAMEDONE_EN_VAL_MASKED (0x0U)
16754 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPFRAMEDONE_EN_VAL_GENINT (0x1U)
16755 
16756 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPVSYNC_EN_MASK (0x00000002U)
16757 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPVSYNC_EN_SHIFT (0x00000001U)
16758 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPVSYNC_EN_MAX (0x00000001U)
16759 
16760 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPVSYNC_EN_VAL_MASKED (0x0U)
16761 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPVSYNC_EN_VAL_GENINT (0x1U)
16762 
16763 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPVSYNC_ODD_EN_MASK (0x00000004U)
16764 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPVSYNC_ODD_EN_SHIFT (0x00000002U)
16765 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPVSYNC_ODD_EN_MAX (0x00000001U)
16766 
16767 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPVSYNC_ODD_EN_VAL_MASKED (0x0U)
16768 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPVSYNC_ODD_EN_VAL_GENINT (0x1U)
16769 
16770 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_MASK (0x00000008U)
16771 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_SHIFT (0x00000003U)
16772 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_MAX (0x00000001U)
16773 
16774 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_VAL_MASKED (0x0U)
16775 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_VAL_GENINT (0x1U)
16776 
16777 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPSYNCLOST_EN_MASK (0x00000010U)
16778 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPSYNCLOST_EN_SHIFT (0x00000004U)
16779 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPSYNCLOST_EN_MAX (0x00000001U)
16780 
16781 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPSYNCLOST_EN_VAL_MASKED (0x0U)
16782 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPSYNCLOST_EN_VAL_GENINT (0x1U)
16783 
16784 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_MASK (0x00000020U)
16785 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_SHIFT (0x00000005U)
16786 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_MAX (0x00000001U)
16787 
16788 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_VAL_MASKED (0x0U)
16789 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_VAL_GENINT (0x1U)
16790 
16791 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_SAFETYREGION_EN_MASK (0x000003C0U)
16792 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_SAFETYREGION_EN_SHIFT (0x00000006U)
16793 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_SAFETYREGION_EN_MAX (0x0000000FU)
16794 
16795 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_SAFETYREGION_EN_VAL_MASKED (0x0U)
16796 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_SAFETYREGION_EN_VAL_GENINT (0x1U)
16797 
16798 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_SECURITYVIOLATION_EN_MASK (0x00000400U)
16799 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_SECURITYVIOLATION_EN_SHIFT (0x0000000AU)
16800 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_SECURITYVIOLATION_EN_MAX (0x00000001U)
16801 
16802 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
16803 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
16804 
16805 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPSYNC_EN_MASK (0x00000800U)
16806 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPSYNC_EN_SHIFT (0x0000000BU)
16807 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPSYNC_EN_MAX (0x00000001U)
16808 
16809 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPSYNC_EN_VAL_MASKED (0x0U)
16810 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_VPSYNC_EN_VAL_GENINT (0x1U)
16811 
16812 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_DUMMY_EN_MASK (0x00001000U)
16813 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_DUMMY_EN_SHIFT (0x0000000CU)
16814 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_DUMMY_EN_MAX (0x00000001U)
16815 
16816 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_DUMMY_EN_VAL_MASKED (0x0U)
16817 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_DUMMY_EN_VAL_GENINT (0x1U)
16818 
16819 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_SAFETYREGION1_EN_MASK (0x0001E000U)
16820 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_SAFETYREGION1_EN_SHIFT (0x0000000DU)
16821 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_SAFETYREGION1_EN_MAX (0x0000000FU)
16822 
16823 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_SAFETYREGION1_EN_VAL_MASKED (0x0U)
16824 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_SAFETYREGION1_EN_VAL_GENINT (0x1U)
16825 
16826 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_RESERVED_MASK (0xFFFE0000U)
16827 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_RESERVED_SHIFT (0x00000011U)
16828 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_0_RESERVED_MAX (0x00007FFFU)
16829 
16830 /* VP_IRQENABLE_1 */
16831 
16832 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPFRAMEDONE_EN_MASK (0x00000001U)
16833 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPFRAMEDONE_EN_SHIFT (0x00000000U)
16834 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPFRAMEDONE_EN_MAX (0x00000001U)
16835 
16836 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPFRAMEDONE_EN_VAL_MASKED (0x0U)
16837 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPFRAMEDONE_EN_VAL_GENINT (0x1U)
16838 
16839 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPVSYNC_EN_MASK (0x00000002U)
16840 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPVSYNC_EN_SHIFT (0x00000001U)
16841 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPVSYNC_EN_MAX (0x00000001U)
16842 
16843 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPVSYNC_EN_VAL_MASKED (0x0U)
16844 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPVSYNC_EN_VAL_GENINT (0x1U)
16845 
16846 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPVSYNC_ODD_EN_MASK (0x00000004U)
16847 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPVSYNC_ODD_EN_SHIFT (0x00000002U)
16848 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPVSYNC_ODD_EN_MAX (0x00000001U)
16849 
16850 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPVSYNC_ODD_EN_VAL_MASKED (0x0U)
16851 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPVSYNC_ODD_EN_VAL_GENINT (0x1U)
16852 
16853 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_MASK (0x00000008U)
16854 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_SHIFT (0x00000003U)
16855 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_MAX (0x00000001U)
16856 
16857 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_VAL_MASKED (0x0U)
16858 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_VAL_GENINT (0x1U)
16859 
16860 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPSYNCLOST_EN_MASK (0x00000010U)
16861 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPSYNCLOST_EN_SHIFT (0x00000004U)
16862 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPSYNCLOST_EN_MAX (0x00000001U)
16863 
16864 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPSYNCLOST_EN_VAL_MASKED (0x0U)
16865 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPSYNCLOST_EN_VAL_GENINT (0x1U)
16866 
16867 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_MASK (0x00000020U)
16868 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_SHIFT (0x00000005U)
16869 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_MAX (0x00000001U)
16870 
16871 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_VAL_MASKED (0x0U)
16872 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_VAL_GENINT (0x1U)
16873 
16874 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_SAFETYREGION_EN_MASK (0x000003C0U)
16875 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_SAFETYREGION_EN_SHIFT (0x00000006U)
16876 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_SAFETYREGION_EN_MAX (0x0000000FU)
16877 
16878 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_SAFETYREGION_EN_VAL_MASKED (0x0U)
16879 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_SAFETYREGION_EN_VAL_GENINT (0x1U)
16880 
16881 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_SECURITYVIOLATION_EN_MASK (0x00000400U)
16882 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_SECURITYVIOLATION_EN_SHIFT (0x0000000AU)
16883 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_SECURITYVIOLATION_EN_MAX (0x00000001U)
16884 
16885 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
16886 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
16887 
16888 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPSYNC_EN_MASK (0x00000800U)
16889 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPSYNC_EN_SHIFT (0x0000000BU)
16890 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPSYNC_EN_MAX (0x00000001U)
16891 
16892 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPSYNC_EN_VAL_MASKED (0x0U)
16893 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_VPSYNC_EN_VAL_GENINT (0x1U)
16894 
16895 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_DUMMY_EN_MASK (0x00001000U)
16896 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_DUMMY_EN_SHIFT (0x0000000CU)
16897 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_DUMMY_EN_MAX (0x00000001U)
16898 
16899 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_DUMMY_EN_VAL_MASKED (0x0U)
16900 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_DUMMY_EN_VAL_GENINT (0x1U)
16901 
16902 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_SAFETYREGION1_EN_MASK (0x0001E000U)
16903 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_SAFETYREGION1_EN_SHIFT (0x0000000DU)
16904 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_SAFETYREGION1_EN_MAX (0x0000000FU)
16905 
16906 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_SAFETYREGION1_EN_VAL_MASKED (0x0U)
16907 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_SAFETYREGION1_EN_VAL_GENINT (0x1U)
16908 
16909 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_RESERVED_MASK (0xFFFE0000U)
16910 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_RESERVED_SHIFT (0x00000011U)
16911 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_1_RESERVED_MAX (0x00007FFFU)
16912 
16913 /* VP_IRQENABLE_2 */
16914 
16915 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPFRAMEDONE_EN_MASK (0x00000001U)
16916 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPFRAMEDONE_EN_SHIFT (0x00000000U)
16917 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPFRAMEDONE_EN_MAX (0x00000001U)
16918 
16919 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPFRAMEDONE_EN_VAL_MASKED (0x0U)
16920 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPFRAMEDONE_EN_VAL_GENINT (0x1U)
16921 
16922 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPVSYNC_EN_MASK (0x00000002U)
16923 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPVSYNC_EN_SHIFT (0x00000001U)
16924 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPVSYNC_EN_MAX (0x00000001U)
16925 
16926 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPVSYNC_EN_VAL_MASKED (0x0U)
16927 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPVSYNC_EN_VAL_GENINT (0x1U)
16928 
16929 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPVSYNC_ODD_EN_MASK (0x00000004U)
16930 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPVSYNC_ODD_EN_SHIFT (0x00000002U)
16931 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPVSYNC_ODD_EN_MAX (0x00000001U)
16932 
16933 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPVSYNC_ODD_EN_VAL_MASKED (0x0U)
16934 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPVSYNC_ODD_EN_VAL_GENINT (0x1U)
16935 
16936 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPPROGRAMMEDLINENUMBER_EN_MASK (0x00000008U)
16937 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPPROGRAMMEDLINENUMBER_EN_SHIFT (0x00000003U)
16938 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPPROGRAMMEDLINENUMBER_EN_MAX (0x00000001U)
16939 
16940 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPPROGRAMMEDLINENUMBER_EN_VAL_MASKED (0x0U)
16941 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPPROGRAMMEDLINENUMBER_EN_VAL_GENINT (0x1U)
16942 
16943 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPSYNCLOST_EN_MASK (0x00000010U)
16944 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPSYNCLOST_EN_SHIFT (0x00000004U)
16945 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPSYNCLOST_EN_MAX (0x00000001U)
16946 
16947 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPSYNCLOST_EN_VAL_MASKED (0x0U)
16948 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPSYNCLOST_EN_VAL_GENINT (0x1U)
16949 
16950 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_ACBIASCOUNTSTATUS_EN_MASK (0x00000020U)
16951 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_ACBIASCOUNTSTATUS_EN_SHIFT (0x00000005U)
16952 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_ACBIASCOUNTSTATUS_EN_MAX (0x00000001U)
16953 
16954 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_ACBIASCOUNTSTATUS_EN_VAL_MASKED (0x0U)
16955 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_ACBIASCOUNTSTATUS_EN_VAL_GENINT (0x1U)
16956 
16957 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_SAFETYREGION_EN_MASK (0x000003C0U)
16958 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_SAFETYREGION_EN_SHIFT (0x00000006U)
16959 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_SAFETYREGION_EN_MAX (0x0000000FU)
16960 
16961 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_SAFETYREGION_EN_VAL_MASKED (0x0U)
16962 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_SAFETYREGION_EN_VAL_GENINT (0x1U)
16963 
16964 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_SECURITYVIOLATION_EN_MASK (0x00000400U)
16965 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_SECURITYVIOLATION_EN_SHIFT (0x0000000AU)
16966 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_SECURITYVIOLATION_EN_MAX (0x00000001U)
16967 
16968 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
16969 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
16970 
16971 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPSYNC_EN_MASK (0x00000800U)
16972 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPSYNC_EN_SHIFT (0x0000000BU)
16973 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPSYNC_EN_MAX (0x00000001U)
16974 
16975 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPSYNC_EN_VAL_MASKED (0x0U)
16976 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_VPSYNC_EN_VAL_GENINT (0x1U)
16977 
16978 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_DUMMY_EN_MASK (0x00001000U)
16979 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_DUMMY_EN_SHIFT (0x0000000CU)
16980 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_DUMMY_EN_MAX (0x00000001U)
16981 
16982 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_DUMMY_EN_VAL_MASKED (0x0U)
16983 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_DUMMY_EN_VAL_GENINT (0x1U)
16984 
16985 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_SAFETYREGION1_EN_MASK (0x0001E000U)
16986 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_SAFETYREGION1_EN_SHIFT (0x0000000DU)
16987 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_SAFETYREGION1_EN_MAX (0x0000000FU)
16988 
16989 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_SAFETYREGION1_EN_VAL_MASKED (0x0U)
16990 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_SAFETYREGION1_EN_VAL_GENINT (0x1U)
16991 
16992 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_RESERVED_MASK (0xFFFE0000U)
16993 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_RESERVED_SHIFT (0x00000011U)
16994 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_2_RESERVED_MAX (0x00007FFFU)
16995 
16996 /* VP_IRQENABLE_3 */
16997 
16998 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPFRAMEDONE_EN_MASK (0x00000001U)
16999 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPFRAMEDONE_EN_SHIFT (0x00000000U)
17000 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPFRAMEDONE_EN_MAX (0x00000001U)
17001 
17002 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPFRAMEDONE_EN_VAL_MASKED (0x0U)
17003 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPFRAMEDONE_EN_VAL_GENINT (0x1U)
17004 
17005 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPVSYNC_EN_MASK (0x00000002U)
17006 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPVSYNC_EN_SHIFT (0x00000001U)
17007 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPVSYNC_EN_MAX (0x00000001U)
17008 
17009 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPVSYNC_EN_VAL_MASKED (0x0U)
17010 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPVSYNC_EN_VAL_GENINT (0x1U)
17011 
17012 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPVSYNC_ODD_EN_MASK (0x00000004U)
17013 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPVSYNC_ODD_EN_SHIFT (0x00000002U)
17014 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPVSYNC_ODD_EN_MAX (0x00000001U)
17015 
17016 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPVSYNC_ODD_EN_VAL_MASKED (0x0U)
17017 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPVSYNC_ODD_EN_VAL_GENINT (0x1U)
17018 
17019 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPPROGRAMMEDLINENUMBER_EN_MASK (0x00000008U)
17020 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPPROGRAMMEDLINENUMBER_EN_SHIFT (0x00000003U)
17021 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPPROGRAMMEDLINENUMBER_EN_MAX (0x00000001U)
17022 
17023 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPPROGRAMMEDLINENUMBER_EN_VAL_MASKED (0x0U)
17024 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPPROGRAMMEDLINENUMBER_EN_VAL_GENINT (0x1U)
17025 
17026 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPSYNCLOST_EN_MASK (0x00000010U)
17027 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPSYNCLOST_EN_SHIFT (0x00000004U)
17028 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPSYNCLOST_EN_MAX (0x00000001U)
17029 
17030 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPSYNCLOST_EN_VAL_MASKED (0x0U)
17031 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPSYNCLOST_EN_VAL_GENINT (0x1U)
17032 
17033 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_ACBIASCOUNTSTATUS_EN_MASK (0x00000020U)
17034 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_ACBIASCOUNTSTATUS_EN_SHIFT (0x00000005U)
17035 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_ACBIASCOUNTSTATUS_EN_MAX (0x00000001U)
17036 
17037 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_ACBIASCOUNTSTATUS_EN_VAL_MASKED (0x0U)
17038 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_ACBIASCOUNTSTATUS_EN_VAL_GENINT (0x1U)
17039 
17040 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_SAFETYREGION_EN_MASK (0x000003C0U)
17041 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_SAFETYREGION_EN_SHIFT (0x00000006U)
17042 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_SAFETYREGION_EN_MAX (0x0000000FU)
17043 
17044 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_SAFETYREGION_EN_VAL_MASKED (0x0U)
17045 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_SAFETYREGION_EN_VAL_GENINT (0x1U)
17046 
17047 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_SECURITYVIOLATION_EN_MASK (0x00000400U)
17048 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_SECURITYVIOLATION_EN_SHIFT (0x0000000AU)
17049 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_SECURITYVIOLATION_EN_MAX (0x00000001U)
17050 
17051 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
17052 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
17053 
17054 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPSYNC_EN_MASK (0x00000800U)
17055 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPSYNC_EN_SHIFT (0x0000000BU)
17056 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPSYNC_EN_MAX (0x00000001U)
17057 
17058 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPSYNC_EN_VAL_MASKED (0x0U)
17059 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_VPSYNC_EN_VAL_GENINT (0x1U)
17060 
17061 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_DUMMY_EN_MASK (0x00001000U)
17062 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_DUMMY_EN_SHIFT (0x0000000CU)
17063 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_DUMMY_EN_MAX (0x00000001U)
17064 
17065 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_DUMMY_EN_VAL_MASKED (0x0U)
17066 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_DUMMY_EN_VAL_GENINT (0x1U)
17067 
17068 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_SAFETYREGION1_EN_MASK (0x0001E000U)
17069 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_SAFETYREGION1_EN_SHIFT (0x0000000DU)
17070 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_SAFETYREGION1_EN_MAX (0x0000000FU)
17071 
17072 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_SAFETYREGION1_EN_VAL_MASKED (0x0U)
17073 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_SAFETYREGION1_EN_VAL_GENINT (0x1U)
17074 
17075 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_RESERVED_MASK (0xFFFE0000U)
17076 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_RESERVED_SHIFT (0x00000011U)
17077 #define CSL_DSS_COMMON_S2_VP_IRQENABLE_3_RESERVED_MAX (0x00007FFFU)
17078 
17079 /* VP_IRQSTATUS_0 */
17080 
17081 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_MASK (0x00000001U)
17082 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_SHIFT (0x00000000U)
17083 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_MAX (0x00000001U)
17084 
17085 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
17086 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_VAL_PEND (0x1U)
17087 
17088 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPVSYNC_IRQ_MASK (0x00000002U)
17089 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPVSYNC_IRQ_SHIFT (0x00000001U)
17090 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPVSYNC_IRQ_MAX (0x00000001U)
17091 
17092 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPVSYNC_IRQ_VAL_NOPEND (0x0U)
17093 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPVSYNC_IRQ_VAL_PEND (0x1U)
17094 
17095 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_MASK (0x00000004U)
17096 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_SHIFT (0x00000002U)
17097 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_MAX (0x00000001U)
17098 
17099 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_VAL_NOPEND (0x0U)
17100 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_VAL_PEND (0x1U)
17101 
17102 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_MASK (0x00000008U)
17103 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_SHIFT (0x00000003U)
17104 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_MAX (0x00000001U)
17105 
17106 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_VAL_NOPEND (0x0U)
17107 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_VAL_PEND (0x1U)
17108 
17109 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_MASK (0x00000010U)
17110 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_SHIFT (0x00000004U)
17111 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_MAX (0x00000001U)
17112 
17113 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_VAL_NOPEND (0x0U)
17114 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_VAL_PEND (0x1U)
17115 
17116 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_MASK (0x00000020U)
17117 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_SHIFT (0x00000005U)
17118 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_MAX (0x00000001U)
17119 
17120 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_VAL_NOPEND (0x0U)
17121 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_VAL_PEND (0x1U)
17122 
17123 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_SAFETYREGION_IRQ_MASK (0x000003C0U)
17124 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_SAFETYREGION_IRQ_SHIFT (0x00000006U)
17125 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_SAFETYREGION_IRQ_MAX (0x0000000FU)
17126 
17127 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
17128 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_PEND (0x1U)
17129 
17130 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_MASK (0x00000400U)
17131 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_SHIFT (0x0000000AU)
17132 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
17133 
17134 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
17135 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
17136 
17137 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPSYNC_IRQ_MASK (0x00000800U)
17138 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPSYNC_IRQ_SHIFT (0x0000000BU)
17139 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPSYNC_IRQ_MAX (0x00000001U)
17140 
17141 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPSYNC_IRQ_VAL_NOPEND (0x0U)
17142 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_VPSYNC_IRQ_VAL_PEND (0x1U)
17143 
17144 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_DUMMY_IRQ_MASK (0x00001000U)
17145 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_DUMMY_IRQ_SHIFT (0x0000000CU)
17146 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_DUMMY_IRQ_MAX (0x00000001U)
17147 
17148 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_DUMMY_IRQ_VAL_NOPEND (0x0U)
17149 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_DUMMY_IRQ_VAL_PEND (0x1U)
17150 
17151 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_SAFETYREGION1_IRQ_MASK (0x0001E000U)
17152 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_SAFETYREGION1_IRQ_SHIFT (0x0000000DU)
17153 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_SAFETYREGION1_IRQ_MAX (0x0000000FU)
17154 
17155 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_SAFETYREGION1_IRQ_VAL_NOPEND (0x0U)
17156 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_SAFETYREGION1_IRQ_VAL_PEND (0x1U)
17157 
17158 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_RESERVED_MASK (0xFFFE0000U)
17159 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_RESERVED_SHIFT (0x00000011U)
17160 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_0_RESERVED_MAX (0x00007FFFU)
17161 
17162 /* VP_IRQSTATUS_1 */
17163 
17164 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_MASK (0x00000001U)
17165 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_SHIFT (0x00000000U)
17166 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_MAX (0x00000001U)
17167 
17168 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
17169 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_VAL_PEND (0x1U)
17170 
17171 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPVSYNC_IRQ_MASK (0x00000002U)
17172 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPVSYNC_IRQ_SHIFT (0x00000001U)
17173 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPVSYNC_IRQ_MAX (0x00000001U)
17174 
17175 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPVSYNC_IRQ_VAL_NOPEND (0x0U)
17176 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPVSYNC_IRQ_VAL_PEND (0x1U)
17177 
17178 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_MASK (0x00000004U)
17179 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_SHIFT (0x00000002U)
17180 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_MAX (0x00000001U)
17181 
17182 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_VAL_NOPEND (0x0U)
17183 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_VAL_PEND (0x1U)
17184 
17185 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_MASK (0x00000008U)
17186 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_SHIFT (0x00000003U)
17187 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_MAX (0x00000001U)
17188 
17189 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_VAL_NOPEND (0x0U)
17190 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_VAL_PEND (0x1U)
17191 
17192 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_MASK (0x00000010U)
17193 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_SHIFT (0x00000004U)
17194 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_MAX (0x00000001U)
17195 
17196 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_VAL_NOPEND (0x0U)
17197 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_VAL_PEND (0x1U)
17198 
17199 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_MASK (0x00000020U)
17200 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_SHIFT (0x00000005U)
17201 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_MAX (0x00000001U)
17202 
17203 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_VAL_NOPEND (0x0U)
17204 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_VAL_PEND (0x1U)
17205 
17206 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_SAFETYREGION_IRQ_MASK (0x000003C0U)
17207 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_SAFETYREGION_IRQ_SHIFT (0x00000006U)
17208 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_SAFETYREGION_IRQ_MAX (0x0000000FU)
17209 
17210 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
17211 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_PEND (0x1U)
17212 
17213 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_MASK (0x00000400U)
17214 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_SHIFT (0x0000000AU)
17215 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
17216 
17217 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
17218 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
17219 
17220 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPSYNC_IRQ_MASK (0x00000800U)
17221 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPSYNC_IRQ_SHIFT (0x0000000BU)
17222 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPSYNC_IRQ_MAX (0x00000001U)
17223 
17224 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPSYNC_IRQ_VAL_NOPEND (0x0U)
17225 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_VPSYNC_IRQ_VAL_PEND (0x1U)
17226 
17227 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_DUMMY_IRQ_MASK (0x00001000U)
17228 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_DUMMY_IRQ_SHIFT (0x0000000CU)
17229 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_DUMMY_IRQ_MAX (0x00000001U)
17230 
17231 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_DUMMY_IRQ_VAL_NOPEND (0x0U)
17232 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_DUMMY_IRQ_VAL_PEND (0x1U)
17233 
17234 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_SAFETYREGION1_IRQ_MASK (0x0001E000U)
17235 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_SAFETYREGION1_IRQ_SHIFT (0x0000000DU)
17236 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_SAFETYREGION1_IRQ_MAX (0x0000000FU)
17237 
17238 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_SAFETYREGION1_IRQ_VAL_NOPEND (0x0U)
17239 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_SAFETYREGION1_IRQ_VAL_PEND (0x1U)
17240 
17241 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_RESERVED_MASK (0xFFFE0000U)
17242 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_RESERVED_SHIFT (0x00000011U)
17243 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_1_RESERVED_MAX (0x00007FFFU)
17244 
17245 /* VP_IRQSTATUS_2 */
17246 
17247 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPFRAMEDONE_IRQ_MASK (0x00000001U)
17248 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPFRAMEDONE_IRQ_SHIFT (0x00000000U)
17249 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPFRAMEDONE_IRQ_MAX (0x00000001U)
17250 
17251 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
17252 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPFRAMEDONE_IRQ_VAL_PEND (0x1U)
17253 
17254 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPVSYNC_IRQ_MASK (0x00000002U)
17255 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPVSYNC_IRQ_SHIFT (0x00000001U)
17256 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPVSYNC_IRQ_MAX (0x00000001U)
17257 
17258 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPVSYNC_IRQ_VAL_NOPEND (0x0U)
17259 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPVSYNC_IRQ_VAL_PEND (0x1U)
17260 
17261 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPVSYNC_ODD_IRQ_MASK (0x00000004U)
17262 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPVSYNC_ODD_IRQ_SHIFT (0x00000002U)
17263 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPVSYNC_ODD_IRQ_MAX (0x00000001U)
17264 
17265 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPVSYNC_ODD_IRQ_VAL_NOPEND (0x0U)
17266 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPVSYNC_ODD_IRQ_VAL_PEND (0x1U)
17267 
17268 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPPROGRAMMEDLINENUMBER_IRQ_MASK (0x00000008U)
17269 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPPROGRAMMEDLINENUMBER_IRQ_SHIFT (0x00000003U)
17270 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPPROGRAMMEDLINENUMBER_IRQ_MAX (0x00000001U)
17271 
17272 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPPROGRAMMEDLINENUMBER_IRQ_VAL_NOPEND (0x0U)
17273 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPPROGRAMMEDLINENUMBER_IRQ_VAL_PEND (0x1U)
17274 
17275 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPSYNCLOST_IRQ_MASK (0x00000010U)
17276 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPSYNCLOST_IRQ_SHIFT (0x00000004U)
17277 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPSYNCLOST_IRQ_MAX (0x00000001U)
17278 
17279 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPSYNCLOST_IRQ_VAL_NOPEND (0x0U)
17280 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPSYNCLOST_IRQ_VAL_PEND (0x1U)
17281 
17282 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_ACBIASCOUNTSTATUS_IRQ_MASK (0x00000020U)
17283 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_ACBIASCOUNTSTATUS_IRQ_SHIFT (0x00000005U)
17284 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_ACBIASCOUNTSTATUS_IRQ_MAX (0x00000001U)
17285 
17286 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_ACBIASCOUNTSTATUS_IRQ_VAL_NOPEND (0x0U)
17287 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_ACBIASCOUNTSTATUS_IRQ_VAL_PEND (0x1U)
17288 
17289 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_SAFETYREGION_IRQ_MASK (0x000003C0U)
17290 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_SAFETYREGION_IRQ_SHIFT (0x00000006U)
17291 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_SAFETYREGION_IRQ_MAX (0x0000000FU)
17292 
17293 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
17294 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_SAFETYREGION_IRQ_VAL_PEND (0x1U)
17295 
17296 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_SECURITYVIOLATION_IRQ_MASK (0x00000400U)
17297 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_SECURITYVIOLATION_IRQ_SHIFT (0x0000000AU)
17298 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
17299 
17300 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
17301 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
17302 
17303 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPSYNC_IRQ_MASK (0x00000800U)
17304 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPSYNC_IRQ_SHIFT (0x0000000BU)
17305 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPSYNC_IRQ_MAX (0x00000001U)
17306 
17307 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPSYNC_IRQ_VAL_NOPEND (0x0U)
17308 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_VPSYNC_IRQ_VAL_PEND (0x1U)
17309 
17310 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_DUMMY_IRQ_MASK (0x00001000U)
17311 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_DUMMY_IRQ_SHIFT (0x0000000CU)
17312 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_DUMMY_IRQ_MAX (0x00000001U)
17313 
17314 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_DUMMY_IRQ_VAL_NOPEND (0x0U)
17315 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_DUMMY_IRQ_VAL_PEND (0x1U)
17316 
17317 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_SAFETYREGION1_IRQ_MASK (0x0001E000U)
17318 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_SAFETYREGION1_IRQ_SHIFT (0x0000000DU)
17319 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_SAFETYREGION1_IRQ_MAX (0x0000000FU)
17320 
17321 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_SAFETYREGION1_IRQ_VAL_NOPEND (0x0U)
17322 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_SAFETYREGION1_IRQ_VAL_PEND (0x1U)
17323 
17324 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_RESERVED_MASK (0xFFFE0000U)
17325 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_RESERVED_SHIFT (0x00000011U)
17326 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_2_RESERVED_MAX (0x00007FFFU)
17327 
17328 /* VP_IRQSTATUS_3 */
17329 
17330 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPFRAMEDONE_IRQ_MASK (0x00000001U)
17331 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPFRAMEDONE_IRQ_SHIFT (0x00000000U)
17332 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPFRAMEDONE_IRQ_MAX (0x00000001U)
17333 
17334 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
17335 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPFRAMEDONE_IRQ_VAL_PEND (0x1U)
17336 
17337 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPVSYNC_IRQ_MASK (0x00000002U)
17338 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPVSYNC_IRQ_SHIFT (0x00000001U)
17339 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPVSYNC_IRQ_MAX (0x00000001U)
17340 
17341 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPVSYNC_IRQ_VAL_NOPEND (0x0U)
17342 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPVSYNC_IRQ_VAL_PEND (0x1U)
17343 
17344 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPVSYNC_ODD_IRQ_MASK (0x00000004U)
17345 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPVSYNC_ODD_IRQ_SHIFT (0x00000002U)
17346 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPVSYNC_ODD_IRQ_MAX (0x00000001U)
17347 
17348 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPVSYNC_ODD_IRQ_VAL_NOPEND (0x0U)
17349 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPVSYNC_ODD_IRQ_VAL_PEND (0x1U)
17350 
17351 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPPROGRAMMEDLINENUMBER_IRQ_MASK (0x00000008U)
17352 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPPROGRAMMEDLINENUMBER_IRQ_SHIFT (0x00000003U)
17353 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPPROGRAMMEDLINENUMBER_IRQ_MAX (0x00000001U)
17354 
17355 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPPROGRAMMEDLINENUMBER_IRQ_VAL_NOPEND (0x0U)
17356 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPPROGRAMMEDLINENUMBER_IRQ_VAL_PEND (0x1U)
17357 
17358 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPSYNCLOST_IRQ_MASK (0x00000010U)
17359 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPSYNCLOST_IRQ_SHIFT (0x00000004U)
17360 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPSYNCLOST_IRQ_MAX (0x00000001U)
17361 
17362 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPSYNCLOST_IRQ_VAL_NOPEND (0x0U)
17363 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPSYNCLOST_IRQ_VAL_PEND (0x1U)
17364 
17365 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_ACBIASCOUNTSTATUS_IRQ_MASK (0x00000020U)
17366 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_ACBIASCOUNTSTATUS_IRQ_SHIFT (0x00000005U)
17367 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_ACBIASCOUNTSTATUS_IRQ_MAX (0x00000001U)
17368 
17369 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_ACBIASCOUNTSTATUS_IRQ_VAL_NOPEND (0x0U)
17370 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_ACBIASCOUNTSTATUS_IRQ_VAL_PEND (0x1U)
17371 
17372 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_SAFETYREGION_IRQ_MASK (0x000003C0U)
17373 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_SAFETYREGION_IRQ_SHIFT (0x00000006U)
17374 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_SAFETYREGION_IRQ_MAX (0x0000000FU)
17375 
17376 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
17377 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_SAFETYREGION_IRQ_VAL_PEND (0x1U)
17378 
17379 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_SECURITYVIOLATION_IRQ_MASK (0x00000400U)
17380 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_SECURITYVIOLATION_IRQ_SHIFT (0x0000000AU)
17381 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
17382 
17383 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
17384 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
17385 
17386 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPSYNC_IRQ_MASK (0x00000800U)
17387 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPSYNC_IRQ_SHIFT (0x0000000BU)
17388 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPSYNC_IRQ_MAX (0x00000001U)
17389 
17390 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPSYNC_IRQ_VAL_NOPEND (0x0U)
17391 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_VPSYNC_IRQ_VAL_PEND (0x1U)
17392 
17393 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_DUMMY_IRQ_MASK (0x00001000U)
17394 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_DUMMY_IRQ_SHIFT (0x0000000CU)
17395 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_DUMMY_IRQ_MAX (0x00000001U)
17396 
17397 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_DUMMY_IRQ_VAL_NOPEND (0x0U)
17398 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_DUMMY_IRQ_VAL_PEND (0x1U)
17399 
17400 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_SAFETYREGION1_IRQ_MASK (0x0001E000U)
17401 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_SAFETYREGION1_IRQ_SHIFT (0x0000000DU)
17402 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_SAFETYREGION1_IRQ_MAX (0x0000000FU)
17403 
17404 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_SAFETYREGION1_IRQ_VAL_NOPEND (0x0U)
17405 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_SAFETYREGION1_IRQ_VAL_PEND (0x1U)
17406 
17407 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_RESERVED_MASK (0xFFFE0000U)
17408 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_RESERVED_SHIFT (0x00000011U)
17409 #define CSL_DSS_COMMON_S2_VP_IRQSTATUS_3_RESERVED_MAX (0x00007FFFU)
17410 
17411 /* WB_IRQENABLE */
17412 
17413 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_WBBUFFEROVERFLOW_EN_MASK (0x00000001U)
17414 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_WBBUFFEROVERFLOW_EN_SHIFT (0x00000000U)
17415 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_WBBUFFEROVERFLOW_EN_MAX (0x00000001U)
17416 
17417 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_WBBUFFEROVERFLOW_EN_VAL_MASKED (0x0U)
17418 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_WBBUFFEROVERFLOW_EN_VAL_GENINT (0x1U)
17419 
17420 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_WBUNCOMPLETEERROR_EN_MASK (0x00000002U)
17421 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_WBUNCOMPLETEERROR_EN_SHIFT (0x00000001U)
17422 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_WBUNCOMPLETEERROR_EN_MAX (0x00000001U)
17423 
17424 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_WBUNCOMPLETEERROR_EN_VAL_MASKED (0x0U)
17425 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_WBUNCOMPLETEERROR_EN_VAL_GENINT (0x1U)
17426 
17427 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_WBFRAMEDONE_EN_MASK (0x00000004U)
17428 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_WBFRAMEDONE_EN_SHIFT (0x00000002U)
17429 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_WBFRAMEDONE_EN_MAX (0x00000001U)
17430 
17431 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_WBFRAMEDONE_EN_VAL_MASKED (0x0U)
17432 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_WBFRAMEDONE_EN_VAL_GENINT (0x1U)
17433 
17434 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_SECURITYVIOLATION_EN_MASK (0x00000008U)
17435 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_SECURITYVIOLATION_EN_SHIFT (0x00000003U)
17436 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_SECURITYVIOLATION_EN_MAX (0x00000001U)
17437 
17438 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
17439 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
17440 
17441 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_WBSYNC_EN_MASK (0x00000010U)
17442 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_WBSYNC_EN_SHIFT (0x00000004U)
17443 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_WBSYNC_EN_MAX (0x00000001U)
17444 
17445 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_WBSYNC_EN_VAL_MASKED (0x0U)
17446 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_WBSYNC_EN_VAL_GENINT (0x1U)
17447 
17448 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_RESERVED_MASK (0xFFFFFFE0U)
17449 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_RESERVED_SHIFT (0x00000005U)
17450 #define CSL_DSS_COMMON_S2_WB_IRQENABLE_RESERVED_MAX (0x07FFFFFFU)
17451 
17452 /* WB_IRQSTATUS */
17453 
17454 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_WBBUFFEROVERFLOW_IRQ_MASK (0x00000001U)
17455 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_WBBUFFEROVERFLOW_IRQ_SHIFT (0x00000000U)
17456 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_WBBUFFEROVERFLOW_IRQ_MAX (0x00000001U)
17457 
17458 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_WBBUFFEROVERFLOW_IRQ_VAL_NOPEND (0x0U)
17459 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_WBBUFFEROVERFLOW_IRQ_VAL_PEND (0x1U)
17460 
17461 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_WBUNCOMPLETEERROR_IRQ_MASK (0x00000002U)
17462 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_WBUNCOMPLETEERROR_IRQ_SHIFT (0x00000001U)
17463 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_WBUNCOMPLETEERROR_IRQ_MAX (0x00000001U)
17464 
17465 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_WBUNCOMPLETEERROR_IRQ_VAL_NOPEND (0x0U)
17466 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_WBUNCOMPLETEERROR_IRQ_VAL_PEND (0x1U)
17467 
17468 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_WBFRAMEDONE_IRQ_MASK (0x00000004U)
17469 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_WBFRAMEDONE_IRQ_SHIFT (0x00000002U)
17470 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_WBFRAMEDONE_IRQ_MAX (0x00000001U)
17471 
17472 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_WBFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
17473 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_WBFRAMEDONE_IRQ_VAL_PEND (0x1U)
17474 
17475 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_SECURITYVIOLATION_IRQ_MASK (0x00000008U)
17476 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_SECURITYVIOLATION_IRQ_SHIFT (0x00000003U)
17477 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
17478 
17479 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
17480 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
17481 
17482 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_WBSYNC_IRQ_MASK (0x00000010U)
17483 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_WBSYNC_IRQ_SHIFT (0x00000004U)
17484 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_WBSYNC_IRQ_MAX (0x00000001U)
17485 
17486 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_WBSYNC_IRQ_VAL_NOPEND (0x0U)
17487 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_WBSYNC_IRQ_VAL_PEND (0x1U)
17488 
17489 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_RESERVED_MASK (0xFFFFFFE0U)
17490 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_RESERVED_SHIFT (0x00000005U)
17491 #define CSL_DSS_COMMON_S2_WB_IRQSTATUS_RESERVED_MAX (0x07FFFFFFU)
17492 
17493 /* DISPC_IRQ_EOI_FUNC */
17494 
17495 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_FUNC_EOI_MASK (0x00000001U)
17496 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_FUNC_EOI_SHIFT (0x00000000U)
17497 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_FUNC_EOI_MAX (0x00000001U)
17498 
17499 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_FUNC_EOI_VAL_NOACTION (0x0U)
17500 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_FUNC_EOI_VAL_EOI (0x1U)
17501 
17502 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_FUNC_RESERVED_MASK (0xFFFFFFFEU)
17503 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_FUNC_RESERVED_SHIFT (0x00000001U)
17504 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_FUNC_RESERVED_MAX (0x7FFFFFFFU)
17505 
17506 /* DISPC_IRQ_EOI_SAFETY */
17507 
17508 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_SAFETY_EOI_MASK (0x00000001U)
17509 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_SAFETY_EOI_SHIFT (0x00000000U)
17510 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_SAFETY_EOI_MAX (0x00000001U)
17511 
17512 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_SAFETY_EOI_VAL_NOACTION (0x0U)
17513 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_SAFETY_EOI_VAL_EOI (0x1U)
17514 
17515 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_SAFETY_RESERVED_MASK (0xFFFFFFFEU)
17516 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_SAFETY_RESERVED_SHIFT (0x00000001U)
17517 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_SAFETY_RESERVED_MAX (0x7FFFFFFFU)
17518 
17519 /* DISPC_IRQ_EOI_SECURITY */
17520 
17521 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_SECURITY_EOI_MASK (0x00000001U)
17522 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_SECURITY_EOI_SHIFT (0x00000000U)
17523 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_SECURITY_EOI_MAX (0x00000001U)
17524 
17525 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_SECURITY_EOI_VAL_NOACTION (0x0U)
17526 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_SECURITY_EOI_VAL_EOI (0x1U)
17527 
17528 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_SECURITY_RESERVED_MASK (0xFFFFFFFEU)
17529 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_SECURITY_RESERVED_SHIFT (0x00000001U)
17530 #define CSL_DSS_COMMON_S2_DISPC_IRQ_EOI_SECURITY_RESERVED_MAX (0x7FFFFFFFU)
17531 
17532 #ifdef __cplusplus
17533 }
17534 #endif
17535 #endif
volatile uint32_t CSC_COEF4
Definition: cslr_dss.h:12810
volatile uint32_t ACCUH_1
Definition: cslr_dss.h:7200
volatile uint32_t VIRTUALVP
Definition: cslr_dss.h:8646
volatile uint32_t CONFIG
Definition: cslr_dss.h:9965
volatile uint32_t PIXEL_INC
Definition: cslr_dss.h:3494
volatile uint32_t CSC_COEF1
Definition: cslr_dss.h:13942
volatile uint32_t BA_UV_1
Definition: cslr_dss.h:3479
volatile uint32_t GAMMA_TABLE_12
Definition: cslr_dss.h:11513
volatile uint32_t SAFETY_LFSR_SEED
Definition: cslr_dss.h:4672
volatile uint32_t VID_IRQENABLE_3
Definition: cslr_dss.h:67
volatile uint32_t BA_EXT_1
Definition: cslr_dss.h:7245
volatile uint32_t CLUT_13
Definition: cslr_dss.h:4664
volatile uint32_t FBDC_ATTRIBUTES
Definition: cslr_dss.h:3508
volatile uint32_t DEFAULT_COLOR
Definition: cslr_dss.h:8647
volatile uint32_t SAFETY_CAPT_SIGNATURE
Definition: cslr_dss.h:4668
volatile uint32_t BUF_THRESHOLD
Definition: cslr_dss.h:4621
volatile uint32_t VP_IRQENABLE_1
Definition: cslr_dss.h:16173
volatile uint32_t BA_UV_0
Definition: cslr_dss.h:4618
volatile uint32_t ACCUH2_1
Definition: cslr_dss.h:5756
volatile uint32_t LUMAKEY
Definition: cslr_dss.h:3533
volatile uint32_t WB_IRQENABLE
Definition: cslr_dss.h:14797
volatile uint32_t GAMMA_TABLE_4
Definition: cslr_dss.h:8865
volatile uint32_t VP_IRQENABLE_3
Definition: cslr_dss.h:14792
volatile uint32_t CSC_COEF5
Definition: cslr_dss.h:10171
volatile uint32_t WB_IRQENABLE
Definition: cslr_dss.h:16180
volatile uint32_t VP_IRQENABLE_0
Definition: cslr_dss.h:14789
volatile uint32_t ACCUV_1
Definition: cslr_dss.h:5758
volatile uint32_t VID_IRQENABLE_2
Definition: cslr_dss.h:16166
volatile uint32_t DATA_CYCLE_2
Definition: cslr_dss.h:12801
volatile uint32_t SECURE
Definition: cslr_dss.h:12841
volatile uint32_t BUF_SIZE_STATUS
Definition: cslr_dss.h:7213
volatile uint32_t CLUT_13
Definition: cslr_dss.h:5823
volatile uint32_t BUF_SIZE_STATUS
Definition: cslr_dss.h:4620
volatile uint32_t DSS_OLDI_STATUS
Definition: cslr_dss.h:12838
volatile uint32_t SAFETY_REF_SIGNATURE
Definition: cslr_dss.h:7275
volatile uint32_t BA_UV_EXT_1
Definition: cslr_dss.h:13974
volatile uint32_t DISPC_CLKGATING_DISABLE
Definition: cslr_dss.h:94
volatile uint32_t CSC_COEF4
Definition: cslr_dss.h:8850
volatile uint32_t FIRH
Definition: cslr_dss.h:7222
volatile uint32_t DISPC_IRQ_EOI_FUNC
Definition: cslr_dss.h:14799
volatile uint32_t GAMMA_TABLE_14
Definition: cslr_dss.h:12835
volatile uint32_t TILE
Definition: cslr_dss.h:4646
volatile uint32_t TRANS_COLOR_MAX
Definition: cslr_dss.h:8649
volatile uint32_t VID_IRQENABLE_0
Definition: cslr_dss.h:14781
volatile uint32_t CLUT_2
Definition: cslr_dss.h:3513
volatile uint32_t CSC_COEF5
Definition: cslr_dss.h:7220
volatile uint32_t DSS_OLDI_STATUS
Definition: cslr_dss.h:10198
volatile uint32_t CONTROL
Definition: cslr_dss.h:11475
volatile uint32_t GAMMA_TABLE_7
Definition: cslr_dss.h:11508
volatile uint32_t VID_IRQSTATUS_0
Definition: cslr_dss.h:14785
volatile uint32_t VP_IRQENABLE_2
Definition: cslr_dss.h:14791
volatile uint32_t CLUT_2
Definition: cslr_dss.h:4653
volatile uint32_t CSC_COEF4
Definition: cslr_dss.h:5773
volatile uint32_t WB_IRQSTATUS
Definition: cslr_dss.h:16181
volatile uint32_t DISPC_IRQENABLE_SET
Definition: cslr_dss.h:2093
volatile uint32_t PICTURE_SIZE
Definition: cslr_dss.h:5791
volatile uint32_t CSC_COEF7
Definition: cslr_dss.h:13967
volatile uint32_t DEFAULT_COLOR
Definition: cslr_dss.h:11287
volatile uint32_t GAMMA_TABLE_4
Definition: cslr_dss.h:12825
volatile uint32_t GAMMA_TABLE_8
Definition: cslr_dss.h:11509
volatile uint32_t CSC_COEF0
Definition: cslr_dss.h:13941
volatile uint32_t DISPC_SECURE_DISABLE
Definition: cslr_dss.h:86
volatile uint32_t CLUT_11
Definition: cslr_dss.h:3522
volatile uint32_t FBDC_CLEAR_COLOR
Definition: cslr_dss.h:7254
volatile uint32_t DISPC_IRQSTATUS
Definition: cslr_dss.h:61
volatile uint32_t SECURE
Definition: cslr_dss.h:11521
volatile uint32_t SAFETY_LFSR_SEED
Definition: cslr_dss.h:7277
volatile uint32_t ROW_INC_UV
Definition: cslr_dss.h:5804
volatile uint32_t GLOBAL_ALPHA
Definition: cslr_dss.h:3490
volatile uint32_t BA_1
Definition: cslr_dss.h:4617
volatile uint32_t FBDC_CONSTANT_COLOR_0
Definition: cslr_dss.h:103
volatile uint32_t CSC_COEF6
Definition: cslr_dss.h:5775
volatile uint32_t DSS_REVISION
Definition: cslr_dss.h:55
volatile uint32_t PIPE_GO
Definition: cslr_dss.h:7282
volatile uint32_t MFLAG_THRESHOLD
Definition: cslr_dss.h:13961
volatile uint32_t GAMMA_TABLE_12
Definition: cslr_dss.h:12833
volatile uint32_t VID_IRQENABLE_0
Definition: cslr_dss.h:16164
Definition: cslr_dss.h:2089
volatile uint32_t BA_UV_EXT_0
Definition: cslr_dss.h:7246
volatile uint32_t GAMMA_TABLE_10
Definition: cslr_dss.h:8871
volatile uint32_t DEFAULT_COLOR2
Definition: cslr_dss.h:12608
volatile uint32_t CROP
Definition: cslr_dss.h:7280
volatile uint32_t GAMMA_TABLE_2
Definition: cslr_dss.h:11503
volatile uint32_t VP_IRQSTATUS_3
Definition: cslr_dss.h:79
volatile uint32_t CSC_COEF0
Definition: cslr_dss.h:8836
volatile uint32_t PIPE_GO
Definition: cslr_dss.h:3537
volatile uint32_t BA_UV_1
Definition: cslr_dss.h:5766
volatile uint32_t BA_UV_EXT_0
Definition: cslr_dss.h:13973
volatile uint32_t DISPC_IRQ_EOI_SAFETY
Definition: cslr_dss.h:2114
volatile uint32_t BA_0
Definition: cslr_dss.h:3476
volatile uint32_t VID_IRQENABLE_1
Definition: cslr_dss.h:2096
volatile uint32_t CLUT_15
Definition: cslr_dss.h:3526
volatile uint32_t DISPC_IRQENABLE_SET
Definition: cslr_dss.h:14779
volatile uint32_t PICTURE_SIZE
Definition: cslr_dss.h:4633
volatile uint32_t ATTRIBUTES2
Definition: cslr_dss.h:13934
volatile uint32_t CROP
Definition: cslr_dss.h:5834
volatile uint32_t TIMING_H
Definition: cslr_dss.h:12807
volatile uint32_t VID_IRQSTATUS_0
Definition: cslr_dss.h:16168
volatile uint32_t SAFETY_CAPT_SIGNATURE
Definition: cslr_dss.h:5827
volatile uint32_t GAMMA_TABLE_7
Definition: cslr_dss.h:10188
volatile uint32_t VID_IRQENABLE_2
Definition: cslr_dss.h:66
volatile uint32_t CLUT_2
Definition: cslr_dss.h:5812
volatile uint32_t CLUT_3
Definition: cslr_dss.h:3514
volatile uint32_t CSC_COEF0
Definition: cslr_dss.h:7215
volatile uint32_t CSC_COEF2
Definition: cslr_dss.h:7217
volatile uint32_t CSC_COEF6
Definition: cslr_dss.h:12812
volatile uint32_t MFLAG_THRESHOLD
Definition: cslr_dss.h:4632
volatile uint32_t VP_IRQSTATUS_1
Definition: cslr_dss.h:2108
volatile uint32_t ACCUV_1
Definition: cslr_dss.h:13930
volatile uint32_t PIXEL_INC
Definition: cslr_dss.h:5792
volatile uint32_t CSC_COEF3
Definition: cslr_dss.h:3485
volatile uint32_t CSC_COEF3
Definition: cslr_dss.h:11489
volatile uint32_t CSC_COEF1
Definition: cslr_dss.h:3483
volatile uint32_t GLOBAL_DMA_THREADSIZESTATUS
Definition: cslr_dss.h:110
volatile uint32_t FIRV
Definition: cslr_dss.h:7224
volatile uint32_t GAMMA_TABLE_6
Definition: cslr_dss.h:8867
volatile uint32_t DATA_CYCLE_2
Definition: cslr_dss.h:8841
volatile uint32_t FBDC_REVISION_4
Definition: cslr_dss.h:99
volatile uint32_t DSS_OLDI_STATUS
Definition: cslr_dss.h:8878
volatile uint32_t GAMMA_TABLE_10
Definition: cslr_dss.h:11511
volatile uint32_t FIRV
Definition: cslr_dss.h:13950
volatile uint32_t SECURE
Definition: cslr_dss.h:13976
volatile uint32_t GAMMA_TABLE_15
Definition: cslr_dss.h:12836
volatile uint32_t CSC_COEF6
Definition: cslr_dss.h:10172
volatile uint32_t VP_IRQENABLE_3
Definition: cslr_dss.h:75
volatile uint32_t GAMMA_TABLE_7
Definition: cslr_dss.h:8868
volatile uint32_t BUF_SIZE_STATUS
Definition: cslr_dss.h:5767
volatile uint32_t CSC_COEF7
Definition: cslr_dss.h:8853
volatile uint32_t ACCUH_0
Definition: cslr_dss.h:7199
volatile uint32_t CLUT_15
Definition: cslr_dss.h:4666
volatile uint32_t GAMMA_TABLE_5
Definition: cslr_dss.h:10186
volatile uint32_t ATTRIBUTES2
Definition: cslr_dss.h:7208
volatile uint32_t ACCUH2_0
Definition: cslr_dss.h:7201
Definition: cslr_dss.h:12604
volatile uint32_t GAMMA_TABLE_2
Definition: cslr_dss.h:8863
volatile uint32_t FBDC_REVISION_5
Definition: cslr_dss.h:100
volatile uint32_t BA_UV_1
Definition: cslr_dss.h:13938
volatile uint32_t CSC_COEF0
Definition: cslr_dss.h:4622
volatile uint32_t CSC_COEF5
Definition: cslr_dss.h:8851
volatile uint32_t MFLAG_THRESHOLD
Definition: cslr_dss.h:3492
volatile uint32_t BA_EXT_0
Definition: cslr_dss.h:5798
volatile uint32_t LUMAKEY
Definition: cslr_dss.h:4673
volatile uint32_t BA_EXT_0
Definition: cslr_dss.h:13971
volatile uint32_t BA_0
Definition: cslr_dss.h:13935
volatile uint32_t CSC_COEF4
Definition: cslr_dss.h:10170
volatile uint32_t LUMAKEY
Definition: cslr_dss.h:5832
volatile uint32_t CLUT_3
Definition: cslr_dss.h:5813
volatile uint32_t POL_FREQ
Definition: cslr_dss.h:10165
volatile uint32_t CSC_COEF6
Definition: cslr_dss.h:8852
volatile uint32_t GAMMA_TABLE_14
Definition: cslr_dss.h:10195
volatile uint32_t ROW_INC
Definition: cslr_dss.h:4637
volatile uint32_t DISPC_GLOBAL_MFLAG_ATTRIBUTE
Definition: cslr_dss.h:88
volatile uint32_t SECURE
Definition: cslr_dss.h:4676
volatile uint32_t CLUT_14
Definition: cslr_dss.h:7270
volatile uint32_t CLUT_1
Definition: cslr_dss.h:5811
volatile uint32_t VID_IRQENABLE_1
Definition: cslr_dss.h:14782
volatile uint32_t GAMMA_TABLE_13
Definition: cslr_dss.h:12834
volatile uint32_t CSC_COEF4
Definition: cslr_dss.h:11490
volatile uint32_t FBDC_REVISION_2
Definition: cslr_dss.h:97
volatile uint32_t BA_EXT_1
Definition: cslr_dss.h:5799
volatile uint32_t VID_IRQSTATUS_1
Definition: cslr_dss.h:16169
volatile uint32_t TIMING_H
Definition: cslr_dss.h:10167
volatile uint32_t GAMMA_TABLE_8
Definition: cslr_dss.h:12829
volatile uint32_t FIRV2
Definition: cslr_dss.h:7225
volatile uint32_t LINE_NUMBER
Definition: cslr_dss.h:10163
volatile uint32_t GAMMA_TABLE_1
Definition: cslr_dss.h:11502
volatile uint32_t FIRV
Definition: cslr_dss.h:5778
volatile uint32_t ACCUV2_0
Definition: cslr_dss.h:7205
volatile uint32_t CSC_COEF5
Definition: cslr_dss.h:3487
volatile uint32_t GAMMA_TABLE_3
Definition: cslr_dss.h:10184
Definition: cslr_dss.h:10153
volatile uint32_t DISPC_IRQENABLE_CLR
Definition: cslr_dss.h:14780
volatile uint32_t WB_IRQSTATUS
Definition: cslr_dss.h:2112
volatile uint32_t ACCUV2_0
Definition: cslr_dss.h:13931
volatile uint32_t GAMMA_TABLE_6
Definition: cslr_dss.h:10187
volatile uint32_t VP_IRQENABLE_0
Definition: cslr_dss.h:16172
volatile uint32_t SAFETY_SIZE
Definition: cslr_dss.h:7276
volatile uint32_t ACCUH2_1
Definition: cslr_dss.h:13928
volatile uint32_t GAMMA_TABLE_1
Definition: cslr_dss.h:12822
volatile uint32_t SECURE
Definition: cslr_dss.h:8655
volatile uint32_t CLUT_5
Definition: cslr_dss.h:7261
volatile uint32_t DATA_CYCLE_1
Definition: cslr_dss.h:10160
volatile uint32_t POL_FREQ
Definition: cslr_dss.h:8845
volatile uint32_t GAMMA_TABLE_15
Definition: cslr_dss.h:8876
volatile uint32_t FIRH
Definition: cslr_dss.h:13948
volatile uint32_t DISPC_IRQ_EOI_SAFETY
Definition: cslr_dss.h:14800
volatile uint32_t PIXEL_INC
Definition: cslr_dss.h:4634
volatile uint32_t TRANS_COLOR_MAX2
Definition: cslr_dss.h:9970
volatile uint32_t DMA_BUFSIZE
Definition: cslr_dss.h:4674
volatile uint32_t WB_IRQENABLE
Definition: cslr_dss.h:2111
Definition: cslr_dss.h:5752
volatile uint32_t SECURE
Definition: cslr_dss.h:12615
volatile uint32_t SAFETY_LFSR_SEED
Definition: cslr_dss.h:11499
volatile uint32_t CSC_COEF5
Definition: cslr_dss.h:4627
volatile uint32_t DISPC_IRQ_EOI_SECURITY
Definition: cslr_dss.h:2115
volatile uint32_t SAFETY_ATTRIBUTES
Definition: cslr_dss.h:4667
volatile uint32_t BA_0
Definition: cslr_dss.h:5763
volatile uint32_t BA_UV_EXT_0
Definition: cslr_dss.h:5800
volatile uint32_t VP_IRQENABLE_2
Definition: cslr_dss.h:16174
volatile uint32_t BA_EXT_1
Definition: cslr_dss.h:4640
volatile uint32_t DISPC_GLOBAL_BUFFER
Definition: cslr_dss.h:90
volatile uint32_t VP_IRQENABLE_1
Definition: cslr_dss.h:14790
volatile uint32_t ACCUV_0
Definition: cslr_dss.h:5757
volatile uint32_t GAMMA_TABLE_2
Definition: cslr_dss.h:12823
volatile uint32_t CSC_COEF2
Definition: cslr_dss.h:10158
volatile uint32_t ROW_INC_UV
Definition: cslr_dss.h:3505
volatile uint32_t VID_IRQSTATUS_2
Definition: cslr_dss.h:14787
volatile uint32_t ATTRIBUTES
Definition: cslr_dss.h:7207
volatile uint32_t CLUT_1
Definition: cslr_dss.h:3512
volatile uint32_t GAMMA_TABLE_9
Definition: cslr_dss.h:11510
volatile uint32_t VID_IRQSTATUS_3
Definition: cslr_dss.h:16171
volatile uint32_t SAFETY_SIZE
Definition: cslr_dss.h:3531
volatile uint32_t ROW_INC
Definition: cslr_dss.h:5795
volatile uint32_t TILE2
Definition: cslr_dss.h:3507
volatile uint32_t BA_EXT_0
Definition: cslr_dss.h:4639
volatile uint32_t CSC_COEF7
Definition: cslr_dss.h:12813
Definition: cslr_dss.h:8644
volatile uint32_t DSS_OLDI_LB
Definition: cslr_dss.h:10199
volatile uint32_t SAFETY_REF_SIGNATURE
Definition: cslr_dss.h:4670
volatile uint32_t CSC_COEF7
Definition: cslr_dss.h:10173
volatile uint32_t CLUT_0
Definition: cslr_dss.h:5810
volatile uint32_t CLUT_3
Definition: cslr_dss.h:4654
volatile uint32_t CLUT_4
Definition: cslr_dss.h:4655
volatile uint32_t CONFIG
Definition: cslr_dss.h:12794
Definition: cslr_dss.h:14775
volatile uint32_t CLUT_14
Definition: cslr_dss.h:3525
volatile uint32_t SAFETY_LFSR_SEED
Definition: cslr_dss.h:12819
volatile uint32_t GAMMA_TABLE_9
Definition: cslr_dss.h:12830
volatile uint32_t VP_IRQSTATUS_0
Definition: cslr_dss.h:2107
volatile uint32_t GAMMA_TABLE_10
Definition: cslr_dss.h:12831
volatile uint32_t SECURE
Definition: cslr_dss.h:5835
volatile uint32_t VP_IRQSTATUS_0
Definition: cslr_dss.h:76
volatile uint32_t SAFETY_ATTRIBUTES
Definition: cslr_dss.h:5826
volatile uint32_t SAFETY_SIZE
Definition: cslr_dss.h:4671
volatile uint32_t TIMING_H
Definition: cslr_dss.h:11487
volatile uint32_t TILE
Definition: cslr_dss.h:3506
volatile uint32_t VP_IRQENABLE_3
Definition: cslr_dss.h:2106
volatile uint32_t DISPC_IRQSTATUS_RAW
Definition: cslr_dss.h:14777
volatile uint32_t DISPC_IRQ_EOI_SECURITY
Definition: cslr_dss.h:14801
volatile uint32_t CLUT_1
Definition: cslr_dss.h:4652
volatile uint32_t VP_IRQSTATUS_2
Definition: cslr_dss.h:2109
volatile uint32_t CLUT_9
Definition: cslr_dss.h:5819
volatile uint32_t CLUT_1
Definition: cslr_dss.h:7257
volatile uint32_t PICTURE_SIZE
Definition: cslr_dss.h:3493
volatile uint32_t CSC_COEF3
Definition: cslr_dss.h:5772
volatile uint32_t CSC_COEF7
Definition: cslr_dss.h:11493
volatile uint32_t DISPC_CONNECTIONS
Definition: cslr_dss.h:106
volatile uint32_t DSS_OLDI_CFG
Definition: cslr_dss.h:8877
volatile uint32_t VID_IRQSTATUS_3
Definition: cslr_dss.h:71
volatile uint32_t FIRH2
Definition: cslr_dss.h:7223
volatile uint32_t CONTROL
Definition: cslr_dss.h:12795
volatile uint32_t WB_IRQSTATUS
Definition: cslr_dss.h:14798
Definition: cslr_dss.h:13924
volatile uint32_t DISPC_IRQ_EOI_SECURITY
Definition: cslr_dss.h:84
volatile uint32_t BUF_THRESHOLD
Definition: cslr_dss.h:5768
volatile uint32_t VP_IRQSTATUS_1
Definition: cslr_dss.h:16177
volatile uint32_t CSC_COEF1
Definition: cslr_dss.h:11477
volatile uint32_t TRANS_COLOR_MIN2
Definition: cslr_dss.h:11292
volatile uint32_t VID_IRQSTATUS_0
Definition: cslr_dss.h:68
volatile uint32_t VID_IRQENABLE_3
Definition: cslr_dss.h:2098
volatile uint32_t TRANS_COLOR_MAX2
Definition: cslr_dss.h:8650
Definition: cslr_dss.h:11473
volatile uint32_t SECURE
Definition: cslr_dss.h:9975
volatile uint32_t VP_IRQSTATUS_3
Definition: cslr_dss.h:16179
volatile uint32_t CSC_COEF2
Definition: cslr_dss.h:12798
volatile uint32_t PICTURE_SIZE
Definition: cslr_dss.h:13962
volatile uint32_t CSC_COEF5
Definition: cslr_dss.h:13946
volatile uint32_t BA_UV_0
Definition: cslr_dss.h:13937
volatile uint32_t VID_IRQSTATUS_0
Definition: cslr_dss.h:2099
volatile uint32_t POSITION
Definition: cslr_dss.h:13965
volatile uint32_t ATTRIBUTES
Definition: cslr_dss.h:4614
volatile uint32_t DATA_CYCLE_1
Definition: cslr_dss.h:11480
volatile uint32_t CSC_COEF6
Definition: cslr_dss.h:11492
volatile uint32_t GAMMA_TABLE_11
Definition: cslr_dss.h:8872
volatile uint32_t CLUT_5
Definition: cslr_dss.h:3516
volatile uint32_t DISPC_IRQENABLE_CLR
Definition: cslr_dss.h:16163
volatile uint32_t TRANS_COLOR_MAX
Definition: cslr_dss.h:11289
volatile uint32_t DISPC_IRQENABLE_CLR
Definition: cslr_dss.h:2094
volatile uint32_t CLUT_10
Definition: cslr_dss.h:3521
volatile uint32_t DISPC_DBG_STATUS
Definition: cslr_dss.h:93
volatile uint32_t CLUT_6
Definition: cslr_dss.h:5816
volatile uint32_t VP_IRQENABLE_1
Definition: cslr_dss.h:2104
volatile uint32_t CONFIG
Definition: cslr_dss.h:12605
volatile uint32_t LINE_NUMBER
Definition: cslr_dss.h:12803
volatile uint32_t TIMING_V
Definition: cslr_dss.h:12808
volatile uint32_t GAMMA_TABLE_15
Definition: cslr_dss.h:11516
volatile uint32_t BA_UV_EXT_0
Definition: cslr_dss.h:3501
volatile uint32_t SECURE
Definition: cslr_dss.h:3536
volatile uint32_t SAFETY_REF_SIGNATURE
Definition: cslr_dss.h:5829
volatile uint32_t CLUT_8
Definition: cslr_dss.h:7264
volatile uint32_t ROW_INC_UV
Definition: cslr_dss.h:4645
volatile uint32_t CSC_COEF6
Definition: cslr_dss.h:3488
volatile uint32_t VID_IRQSTATUS_1
Definition: cslr_dss.h:69
volatile uint32_t CSC_COEF2
Definition: cslr_dss.h:3484
volatile uint32_t CLUT_4
Definition: cslr_dss.h:7260
volatile uint32_t SAFETY_POSITION
Definition: cslr_dss.h:3529
volatile uint32_t BA_UV_EXT_0
Definition: cslr_dss.h:4641
volatile uint32_t DISPC_IRQ_EOI_SAFETY
Definition: cslr_dss.h:83
volatile uint32_t DISPC_GLOBAL_OUTPUT_ENABLE
Definition: cslr_dss.h:89
volatile uint32_t DSS_OLDI_LB
Definition: cslr_dss.h:11519
volatile uint32_t ACCUV2_1
Definition: cslr_dss.h:7206
volatile uint32_t CSC_COEF1
Definition: cslr_dss.h:7216
volatile uint32_t FBDC_CLEAR_COLOR
Definition: cslr_dss.h:3509
volatile uint32_t DSS_CBA_CFG
Definition: cslr_dss.h:91
volatile uint32_t SECURE
Definition: cslr_dss.h:8881
volatile uint32_t CSC_COEF7
Definition: cslr_dss.h:4643
volatile uint32_t SAFETY_LFSR_SEED
Definition: cslr_dss.h:5831
volatile uint32_t GAMMA_TABLE_0
Definition: cslr_dss.h:12821
volatile uint32_t CLUT_10
Definition: cslr_dss.h:7266
volatile uint32_t CROP
Definition: cslr_dss.h:3535
volatile uint32_t CSC_COEF2
Definition: cslr_dss.h:4624
volatile uint32_t PRELOAD
Definition: cslr_dss.h:5794
volatile uint32_t TIMING_V
Definition: cslr_dss.h:8848
volatile uint32_t TRANS_COLOR_MIN2
Definition: cslr_dss.h:9972
volatile uint32_t SIZE_SCREEN
Definition: cslr_dss.h:11486
volatile uint32_t FBDC_ATTRIBUTES
Definition: cslr_dss.h:7253
volatile uint32_t DSS_OLDI_CFG
Definition: cslr_dss.h:11517
volatile uint32_t ROW_INC
Definition: cslr_dss.h:7241
volatile uint32_t SIZE_SCREEN
Definition: cslr_dss.h:10166
volatile uint32_t LUMAKEY
Definition: cslr_dss.h:7278
volatile uint32_t TRANS_COLOR_MAX2
Definition: cslr_dss.h:12610
volatile uint32_t DSS_SYSCONFIG
Definition: cslr_dss.h:56
volatile uint32_t GLOBAL_ALPHA
Definition: cslr_dss.h:4630
volatile uint32_t WB_IRQENABLE
Definition: cslr_dss.h:80
volatile uint32_t BA_UV_0
Definition: cslr_dss.h:3478
volatile uint32_t CSC_COEF0
Definition: cslr_dss.h:11476
volatile uint32_t CLUT_0
Definition: cslr_dss.h:3511
volatile uint32_t VP_IRQENABLE_2
Definition: cslr_dss.h:2105
volatile uint32_t VP_IRQSTATUS_0
Definition: cslr_dss.h:16176
volatile uint32_t CONFIG
Definition: cslr_dss.h:10154
volatile uint32_t ACCUV_0
Definition: cslr_dss.h:13929
volatile uint32_t FIRH2
Definition: cslr_dss.h:13949
volatile uint32_t CSC_COEF5
Definition: cslr_dss.h:5774
volatile uint32_t CSC_COEF0
Definition: cslr_dss.h:10156
volatile uint32_t CSC_COEF0
Definition: cslr_dss.h:12796
volatile uint32_t CONFIG
Definition: cslr_dss.h:11474
volatile uint32_t PRELOAD
Definition: cslr_dss.h:4636
volatile uint32_t CSC_COEF3
Definition: cslr_dss.h:7218
volatile uint32_t SAFETY_ATTRIBUTES
Definition: cslr_dss.h:3527
volatile uint32_t CLUT_13
Definition: cslr_dss.h:7269
volatile uint32_t BA_EXT_0
Definition: cslr_dss.h:3499
volatile uint32_t FBDC_ATTRIBUTES
Definition: cslr_dss.h:4648
volatile uint32_t FBDC_CONSTANT_COLOR_1
Definition: cslr_dss.h:104
volatile uint32_t VID_IRQENABLE_2
Definition: cslr_dss.h:2097
volatile uint32_t VP_IRQSTATUS_1
Definition: cslr_dss.h:14794
volatile uint32_t GAMMA_TABLE_0
Definition: cslr_dss.h:11501
volatile uint32_t DATA_CYCLE_0
Definition: cslr_dss.h:11479
volatile uint32_t DSS_OLDI_LB
Definition: cslr_dss.h:8879
volatile uint32_t GAMMA_TABLE_4
Definition: cslr_dss.h:10185
volatile uint32_t BA_UV_EXT_1
Definition: cslr_dss.h:3502
volatile uint32_t VID_IRQENABLE_2
Definition: cslr_dss.h:14783
volatile uint32_t TRANS_COLOR_MAX
Definition: cslr_dss.h:9969
volatile uint32_t CSC_COEF4
Definition: cslr_dss.h:3486
volatile uint32_t CLUT_10
Definition: cslr_dss.h:5820
volatile uint32_t DISPC_IRQENABLE_CLR
Definition: cslr_dss.h:63
volatile uint32_t CLUT_15
Definition: cslr_dss.h:5825
volatile uint32_t BA_1
Definition: cslr_dss.h:5764
volatile uint32_t VID_IRQENABLE_1
Definition: cslr_dss.h:16165
volatile uint32_t VID_IRQSTATUS_2
Definition: cslr_dss.h:70
volatile uint32_t VP_IRQENABLE_1
Definition: cslr_dss.h:73
volatile uint32_t GAMMA_TABLE_7
Definition: cslr_dss.h:12828
volatile uint32_t PICTURE_SIZE
Definition: cslr_dss.h:7237
volatile uint32_t BA_UV_0
Definition: cslr_dss.h:5765
volatile uint32_t CLUT_12
Definition: cslr_dss.h:4663
volatile uint32_t VP_IRQENABLE_0
Definition: cslr_dss.h:72
volatile uint32_t CSC_COEF2
Definition: cslr_dss.h:5771
volatile uint32_t CLUT_0
Definition: cslr_dss.h:4651
volatile uint32_t VID_IRQSTATUS_3
Definition: cslr_dss.h:2102
volatile uint32_t DEFAULT_COLOR
Definition: cslr_dss.h:9967
volatile uint32_t CLUT_9
Definition: cslr_dss.h:7265
volatile uint32_t FIRH2
Definition: cslr_dss.h:5777
volatile uint32_t DEFAULT_COLOR
Definition: cslr_dss.h:12607
volatile uint32_t PIPE_GO
Definition: cslr_dss.h:4677
volatile uint32_t CLUT_9
Definition: cslr_dss.h:3520
Definition: cslr_dss.h:3472
volatile uint32_t DISPC_MSS_VP3
Definition: cslr_dss.h:108
volatile uint32_t TRANS_COLOR_MIN
Definition: cslr_dss.h:8651
volatile uint32_t GAMMA_TABLE_4
Definition: cslr_dss.h:11505
volatile uint32_t CLUT_15
Definition: cslr_dss.h:7271
volatile uint32_t GLOBAL_ALPHA
Definition: cslr_dss.h:7234
volatile uint32_t DISPC_IRQSTATUS_RAW
Definition: cslr_dss.h:2091
volatile uint32_t BA_UV_0
Definition: cslr_dss.h:7211
volatile uint32_t GLOBAL_ALPHA
Definition: cslr_dss.h:5788
volatile uint32_t DISPC_IRQ_EOI_FUNC
Definition: cslr_dss.h:2113
volatile uint32_t ACCUH_1
Definition: cslr_dss.h:5754
volatile uint32_t CSC_COEF1
Definition: cslr_dss.h:10157
volatile uint32_t VID_IRQSTATUS_2
Definition: cslr_dss.h:2101
volatile uint32_t CONTROL
Definition: cslr_dss.h:10155
volatile uint32_t CLUT_5
Definition: cslr_dss.h:4656
volatile uint32_t TILE
Definition: cslr_dss.h:5805
volatile uint32_t ROW_INC
Definition: cslr_dss.h:13969
volatile uint32_t DISPC_IRQSTATUS_RAW
Definition: cslr_dss.h:60
volatile uint32_t ACCUH_0
Definition: cslr_dss.h:5753
volatile uint32_t ATTRIBUTES2
Definition: cslr_dss.h:4615
Definition: cslr_dss.h:11284
volatile uint32_t DEFAULT_COLOR2
Definition: cslr_dss.h:9968
volatile uint32_t CLUT_6
Definition: cslr_dss.h:3517
volatile uint32_t CLUT_9
Definition: cslr_dss.h:4660
volatile uint32_t GAMMA_TABLE_14
Definition: cslr_dss.h:8875
volatile uint32_t CSC_COEF7
Definition: cslr_dss.h:3503
volatile uint32_t VP_IRQSTATUS_2
Definition: cslr_dss.h:78
volatile uint32_t CLUT_11
Definition: cslr_dss.h:7267
volatile uint32_t MFLAG_THRESHOLD
Definition: cslr_dss.h:5790
volatile uint32_t DISPC_IRQ_EOI_SECURITY
Definition: cslr_dss.h:16184
volatile uint32_t BA_UV_1
Definition: cslr_dss.h:4619
volatile uint32_t CSC_COEF2
Definition: cslr_dss.h:13943
volatile uint32_t FIRH
Definition: cslr_dss.h:5776
volatile uint32_t ACCUV_1
Definition: cslr_dss.h:7204
volatile uint32_t TRANS_COLOR_MIN
Definition: cslr_dss.h:9971
volatile uint32_t CSC_COEF3
Definition: cslr_dss.h:8849
volatile uint32_t DATA_CYCLE_0
Definition: cslr_dss.h:8839
volatile uint32_t FIRV2
Definition: cslr_dss.h:5779
volatile uint32_t FBDC_CLEAR_COLOR
Definition: cslr_dss.h:5808
volatile uint32_t FBDC_CLEAR_COLOR
Definition: cslr_dss.h:4649
volatile uint32_t GAMMA_TABLE_0
Definition: cslr_dss.h:10181
volatile uint32_t ROW_INC_UV
Definition: cslr_dss.h:7250
volatile uint32_t CLUT_12
Definition: cslr_dss.h:7268
volatile uint32_t DISPC_IRQSTATUS
Definition: cslr_dss.h:16161
volatile uint32_t BA_EXT_1
Definition: cslr_dss.h:3500
volatile uint32_t CSC_COEF7
Definition: cslr_dss.h:7248
volatile uint32_t VP_IRQSTATUS_2
Definition: cslr_dss.h:16178
volatile uint32_t VP_IRQSTATUS_3
Definition: cslr_dss.h:2110
volatile uint32_t CSC_COEF2
Definition: cslr_dss.h:8838
volatile uint32_t GAMMA_TABLE_5
Definition: cslr_dss.h:12826
volatile uint32_t WB_IRQSTATUS
Definition: cslr_dss.h:81
volatile uint32_t ACCUH2_1
Definition: cslr_dss.h:7202
volatile uint32_t TILE2
Definition: cslr_dss.h:5806
volatile uint32_t CLUT_11
Definition: cslr_dss.h:4662
volatile uint32_t SIZE
Definition: cslr_dss.h:13964
volatile uint32_t VID_IRQSTATUS_1
Definition: cslr_dss.h:2100
volatile uint32_t PIXEL_INC
Definition: cslr_dss.h:7238
volatile uint32_t BA_0
Definition: cslr_dss.h:7209
volatile uint32_t ATTRIBUTES
Definition: cslr_dss.h:13933
Definition: cslr_dss.h:8833
volatile uint32_t BUF_SIZE_STATUS
Definition: cslr_dss.h:13939
volatile uint32_t FBDC_COMMON_CONTROL
Definition: cslr_dss.h:102
volatile uint32_t SIZE
Definition: cslr_dss.h:5796
volatile uint32_t CLUT_6
Definition: cslr_dss.h:4657
volatile uint32_t VP_IRQENABLE_3
Definition: cslr_dss.h:16175
volatile uint32_t GAMMA_TABLE_5
Definition: cslr_dss.h:11506
volatile uint32_t DISPC_IRQENABLE_SET
Definition: cslr_dss.h:62
volatile uint32_t DATA_CYCLE_0
Definition: cslr_dss.h:10159
volatile uint32_t FBDC_REVISION_6
Definition: cslr_dss.h:101
volatile uint32_t SAFETY_ATTRIBUTES
Definition: cslr_dss.h:7272
volatile uint32_t TRANS_COLOR_MAX
Definition: cslr_dss.h:12609
volatile uint32_t DATA_CYCLE_2
Definition: cslr_dss.h:11481
volatile uint32_t TIMING_V
Definition: cslr_dss.h:10168
volatile uint32_t BUF_THRESHOLD
Definition: cslr_dss.h:3481
volatile uint32_t SECURE
Definition: cslr_dss.h:10201
volatile uint32_t BA_1
Definition: cslr_dss.h:13936
volatile uint32_t DSS_OLDI_CFG
Definition: cslr_dss.h:12837
volatile uint32_t TRANS_COLOR_MIN2
Definition: cslr_dss.h:12612
volatile uint32_t ROW_INC
Definition: cslr_dss.h:3497
volatile uint32_t CLUT_5
Definition: cslr_dss.h:5815
volatile uint32_t SAFETY_POSITION
Definition: cslr_dss.h:7274
volatile uint32_t CLUT_4
Definition: cslr_dss.h:3515
volatile uint32_t VID_IRQENABLE_3
Definition: cslr_dss.h:16167
volatile uint32_t VID_IRQENABLE_0
Definition: cslr_dss.h:2095
volatile uint32_t ATTRIBUTES
Definition: cslr_dss.h:5761
volatile uint32_t SECURE
Definition: cslr_dss.h:11295
volatile uint32_t ROW_INC_UV
Definition: cslr_dss.h:13970
volatile uint32_t GAMMA_TABLE_10
Definition: cslr_dss.h:10191
volatile uint32_t POL_FREQ
Definition: cslr_dss.h:12805
volatile uint32_t TILE2
Definition: cslr_dss.h:4647
volatile uint32_t GAMMA_TABLE_14
Definition: cslr_dss.h:11515
volatile uint32_t SAFETY_POSITION
Definition: cslr_dss.h:4669
volatile uint32_t CONFIG
Definition: cslr_dss.h:11285
volatile uint32_t CSC_COEF3
Definition: cslr_dss.h:10169
volatile uint32_t CSC_COEF6
Definition: cslr_dss.h:4628
volatile uint32_t SAFETY_SIZE
Definition: cslr_dss.h:5830
volatile uint32_t CSC_COEF3
Definition: cslr_dss.h:13944
volatile uint32_t VP_IRQSTATUS_1
Definition: cslr_dss.h:77
volatile uint32_t BA_EXT_0
Definition: cslr_dss.h:7244
volatile uint32_t DSS_OLDI_LB
Definition: cslr_dss.h:12839
volatile uint32_t CONTROL
Definition: cslr_dss.h:8835
volatile uint32_t VID_IRQSTATUS_1
Definition: cslr_dss.h:14786
volatile uint32_t CSC_COEF4
Definition: cslr_dss.h:7219
volatile uint32_t DATA_CYCLE_2
Definition: cslr_dss.h:10161
volatile uint32_t VP_IRQENABLE_0
Definition: cslr_dss.h:2103
volatile uint32_t ACCUH_1
Definition: cslr_dss.h:13926
volatile uint32_t DSS_SYSSTATUS
Definition: cslr_dss.h:58
volatile uint32_t SAFETY_POSITION
Definition: cslr_dss.h:5828
volatile uint32_t CSC_COEF1
Definition: cslr_dss.h:8837
volatile uint32_t CLUT_14
Definition: cslr_dss.h:4665
volatile uint32_t TILE
Definition: cslr_dss.h:7251
volatile uint32_t CSC_COEF2
Definition: cslr_dss.h:11478
volatile uint32_t GLOBAL_DMA_THREADSIZE
Definition: cslr_dss.h:109
volatile uint32_t CSC_COEF0
Definition: cslr_dss.h:5769
volatile uint32_t CSC_COEF3
Definition: cslr_dss.h:4625
volatile uint32_t CLUT_8
Definition: cslr_dss.h:5818
volatile uint32_t GAMMA_TABLE_0
Definition: cslr_dss.h:8861
volatile uint32_t CLUT_7
Definition: cslr_dss.h:4658
volatile uint32_t GAMMA_TABLE_15
Definition: cslr_dss.h:10196
volatile uint32_t SAFETY_LFSR_SEED
Definition: cslr_dss.h:3532
volatile uint32_t CSC_COEF1
Definition: cslr_dss.h:5770
volatile uint32_t TRANS_COLOR_MIN2
Definition: cslr_dss.h:8652
volatile uint32_t ACCUH2_0
Definition: cslr_dss.h:5755
volatile uint32_t DISPC_IRQ_EOI_FUNC
Definition: cslr_dss.h:16182
volatile uint32_t BA_0
Definition: cslr_dss.h:4616
volatile uint32_t GAMMA_TABLE_1
Definition: cslr_dss.h:8862
volatile uint32_t CLUT_14
Definition: cslr_dss.h:5824
volatile uint32_t GAMMA_TABLE_9
Definition: cslr_dss.h:8870
volatile uint32_t TILE2
Definition: cslr_dss.h:7252
volatile uint32_t BUF_THRESHOLD
Definition: cslr_dss.h:7214
volatile uint32_t CLUT_8
Definition: cslr_dss.h:3519
volatile uint32_t CSC_COEF6
Definition: cslr_dss.h:13947
volatile uint32_t SAFETY_CAPT_SIGNATURE
Definition: cslr_dss.h:7273
volatile uint32_t VID_IRQENABLE_3
Definition: cslr_dss.h:14784
volatile uint32_t GAMMA_TABLE_13
Definition: cslr_dss.h:11514
volatile uint32_t FBDC_REVISION_3
Definition: cslr_dss.h:98
volatile uint32_t GAMMA_TABLE_12
Definition: cslr_dss.h:10193
volatile uint32_t MFLAG_THRESHOLD
Definition: cslr_dss.h:7236
Definition: cslr_dss.h:53
volatile uint32_t GLOBAL_GOBITMODE
Definition: cslr_dss.h:111
volatile uint32_t GAMMA_TABLE_11
Definition: cslr_dss.h:10192
volatile uint32_t SIZE_SCREEN
Definition: cslr_dss.h:12806
volatile uint32_t BA_EXT_1
Definition: cslr_dss.h:13972
volatile uint32_t VP_IRQSTATUS_2
Definition: cslr_dss.h:14795
volatile uint32_t DISPC_IRQENABLE_SET
Definition: cslr_dss.h:16162
volatile uint32_t VID_IRQENABLE_1
Definition: cslr_dss.h:65
volatile uint32_t GAMMA_TABLE_3
Definition: cslr_dss.h:11504
volatile uint32_t ACCUV2_0
Definition: cslr_dss.h:5759
volatile uint32_t TIMING_V
Definition: cslr_dss.h:11488
volatile uint32_t DISPC_MSS_VP1
Definition: cslr_dss.h:107
volatile uint32_t GAMMA_TABLE_6
Definition: cslr_dss.h:12827
volatile uint32_t GAMMA_TABLE_12
Definition: cslr_dss.h:8873
volatile uint32_t BA_UV_EXT_1
Definition: cslr_dss.h:5801
volatile uint32_t DATA_CYCLE_1
Definition: cslr_dss.h:8840
volatile uint32_t CSC_COEF4
Definition: cslr_dss.h:13945
volatile uint32_t FBDC_ATTRIBUTES
Definition: cslr_dss.h:5807
volatile uint32_t GAMMA_TABLE_1
Definition: cslr_dss.h:10182
volatile uint32_t CLUT_13
Definition: cslr_dss.h:3524
volatile uint32_t LINE_NUMBER
Definition: cslr_dss.h:8843
volatile uint32_t CSC_COEF5
Definition: cslr_dss.h:12811
volatile uint32_t BA_UV_EXT_1
Definition: cslr_dss.h:7247
volatile uint32_t TRANS_COLOR_MAX2
Definition: cslr_dss.h:11290
volatile uint32_t DISPC_IRQSTATUS
Definition: cslr_dss.h:14778
volatile uint32_t BA_UV_EXT_1
Definition: cslr_dss.h:4642
volatile uint32_t GAMMA_TABLE_3
Definition: cslr_dss.h:8864
volatile uint32_t POL_FREQ
Definition: cslr_dss.h:11485
volatile uint32_t VIRTUALVP
Definition: cslr_dss.h:12606
volatile uint32_t SECURE
Definition: cslr_dss.h:7281
volatile uint32_t CLUT_7
Definition: cslr_dss.h:7263
volatile uint32_t GAMMA_TABLE_8
Definition: cslr_dss.h:8869
Definition: cslr_dss.h:7198
volatile uint32_t ATTRIBUTES2
Definition: cslr_dss.h:3475
volatile uint32_t PIPE_GO
Definition: cslr_dss.h:5836
volatile uint32_t CSC_COEF4
Definition: cslr_dss.h:4626
volatile uint32_t CSC_COEF0
Definition: cslr_dss.h:3482
volatile uint32_t GAMMA_TABLE_13
Definition: cslr_dss.h:10194
volatile uint32_t SIZE_SCREEN
Definition: cslr_dss.h:8846
volatile uint32_t CLUT_3
Definition: cslr_dss.h:7259
volatile uint32_t CSC_COEF6
Definition: cslr_dss.h:7221
volatile uint32_t BUF_SIZE_STATUS
Definition: cslr_dss.h:3480
volatile uint32_t GAMMA_TABLE_13
Definition: cslr_dss.h:8874
volatile uint32_t SAFETY_CAPT_SIGNATURE
Definition: cslr_dss.h:3528
volatile uint32_t CLUT_7
Definition: cslr_dss.h:5817
volatile uint32_t ATTRIBUTES2
Definition: cslr_dss.h:5762
volatile uint32_t CLUT_2
Definition: cslr_dss.h:7258
volatile uint32_t VID_IRQENABLE_0
Definition: cslr_dss.h:64
volatile uint32_t CLUT_12
Definition: cslr_dss.h:3523
volatile uint32_t FBDC_REVISION_1
Definition: cslr_dss.h:96
volatile uint32_t GAMMA_TABLE_11
Definition: cslr_dss.h:12832
volatile uint32_t CLUT_0
Definition: cslr_dss.h:7256
volatile uint32_t DSS_OLDI_CFG
Definition: cslr_dss.h:10197
volatile uint32_t SAFETY_REF_SIGNATURE
Definition: cslr_dss.h:3530
volatile uint32_t DEFAULT_COLOR2
Definition: cslr_dss.h:8648
volatile uint32_t GAMMA_TABLE_2
Definition: cslr_dss.h:10183
volatile uint32_t DISPC_DBG_CONTROL
Definition: cslr_dss.h:92
volatile uint32_t CLUT_7
Definition: cslr_dss.h:3518
volatile uint32_t VIRTUALVP
Definition: cslr_dss.h:11286
volatile uint32_t DSS_OLDI_STATUS
Definition: cslr_dss.h:11518
volatile uint32_t CLUT_10
Definition: cslr_dss.h:4661
Definition: cslr_dss.h:9964
volatile uint32_t DATA_CYCLE_0
Definition: cslr_dss.h:12799
volatile uint32_t TRANS_COLOR_MIN
Definition: cslr_dss.h:12611
volatile uint32_t SIZE
Definition: cslr_dss.h:7242
volatile uint32_t CLUT_6
Definition: cslr_dss.h:7262
volatile uint32_t DMA_BUFSIZE
Definition: cslr_dss.h:7279
volatile uint32_t DISPC_IRQSTATUS
Definition: cslr_dss.h:2092
volatile uint32_t TRANS_COLOR_MIN
Definition: cslr_dss.h:11291
volatile uint32_t ACCUH_0
Definition: cslr_dss.h:13925
volatile uint32_t GAMMA_TABLE_8
Definition: cslr_dss.h:10189
volatile uint32_t CSC_COEF7
Definition: cslr_dss.h:5802
volatile uint32_t CSC_COEF1
Definition: cslr_dss.h:4623
volatile uint32_t GAMMA_TABLE_6
Definition: cslr_dss.h:11507
volatile uint32_t DISPC_IRQ_EOI_SAFETY
Definition: cslr_dss.h:16183
Definition: cslr_dss.h:16158
volatile uint32_t VP_IRQSTATUS_0
Definition: cslr_dss.h:14793
volatile uint32_t PRELOAD
Definition: cslr_dss.h:7240
volatile uint32_t DISPC_IRQ_EOI_FUNC
Definition: cslr_dss.h:82
volatile uint32_t ATTRIBUTES
Definition: cslr_dss.h:3474
volatile uint32_t CSC_COEF1
Definition: cslr_dss.h:12797
volatile uint32_t CONFIG
Definition: cslr_dss.h:8834
volatile uint32_t ACCUV_0
Definition: cslr_dss.h:7203
volatile uint32_t BA_1
Definition: cslr_dss.h:3477
volatile uint32_t CLUT_8
Definition: cslr_dss.h:4659
volatile uint32_t GAMMA_TABLE_3
Definition: cslr_dss.h:12824
volatile uint32_t BA_1
Definition: cslr_dss.h:7210
volatile uint32_t PRELOAD
Definition: cslr_dss.h:3496
volatile uint32_t CSC_COEF5
Definition: cslr_dss.h:11491
volatile uint32_t FIRV2
Definition: cslr_dss.h:13951
volatile uint32_t CSC_COEF3
Definition: cslr_dss.h:12809
volatile uint32_t VID_IRQSTATUS_3
Definition: cslr_dss.h:14788
volatile uint32_t VP_IRQENABLE_2
Definition: cslr_dss.h:74
volatile uint32_t TIMING_H
Definition: cslr_dss.h:8847
volatile uint32_t DMA_BUFSIZE
Definition: cslr_dss.h:5833
volatile uint32_t BA_UV_1
Definition: cslr_dss.h:7212
volatile uint32_t VID_IRQSTATUS_2
Definition: cslr_dss.h:16170
volatile uint32_t GAMMA_TABLE_5
Definition: cslr_dss.h:8866
volatile uint32_t GAMMA_TABLE_11
Definition: cslr_dss.h:11512
volatile uint32_t SAFETY_LFSR_SEED
Definition: cslr_dss.h:8859
volatile uint32_t DATA_CYCLE_1
Definition: cslr_dss.h:12800
volatile uint32_t SAFETY_LFSR_SEED
Definition: cslr_dss.h:10179
volatile uint32_t DISPC_IRQSTATUS_RAW
Definition: cslr_dss.h:16160
volatile uint32_t BUF_THRESHOLD
Definition: cslr_dss.h:13940
Definition: cslr_dss.h:4612
volatile uint32_t CLUT_12
Definition: cslr_dss.h:5822
volatile uint32_t VIRTUALVP
Definition: cslr_dss.h:9966
volatile uint32_t ACCUV2_1
Definition: cslr_dss.h:5760
volatile uint32_t CLUT_11
Definition: cslr_dss.h:5821
volatile uint32_t LINE_NUMBER
Definition: cslr_dss.h:11483
Definition: cslr_dss.h:12793
volatile uint32_t DEFAULT_COLOR2
Definition: cslr_dss.h:11288
volatile uint32_t CLUT_4
Definition: cslr_dss.h:5814
volatile uint32_t ACCUV2_1
Definition: cslr_dss.h:13932
volatile uint32_t ACCUH2_0
Definition: cslr_dss.h:13927
volatile uint32_t GAMMA_TABLE_9
Definition: cslr_dss.h:10190
volatile uint32_t VP_IRQSTATUS_3
Definition: cslr_dss.h:14796
volatile uint32_t CONFIG
Definition: cslr_dss.h:8645
volatile uint32_t CROP
Definition: cslr_dss.h:4675
volatile uint32_t DMA_BUFSIZE
Definition: cslr_dss.h:3534